A hardware/software partitioning algorithm for processor cores of digital signal processing
A hardware/software cosynthesis system for processor cores of digital signal processing has
been developed. This paper focuses on a hardware/software partitioning algorithm which is
one of the key issues in the system. Given an input assembly code generated by the
compiler in the system, the proposed hardware/software partitioning algorithm first
determines the types and the numbers of required hardware units, such as multiple
functional units, hardware loop units, and particular addressing units, for a processor core …
been developed. This paper focuses on a hardware/software partitioning algorithm which is
one of the key issues in the system. Given an input assembly code generated by the
compiler in the system, the proposed hardware/software partitioning algorithm first
determines the types and the numbers of required hardware units, such as multiple
functional units, hardware loop units, and particular addressing units, for a processor core …
[PDF][PDF] A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing
NTTSM Yanagisawa, T Ohtsuki - websrv.cecs.uci.edu
A hardware/software cosynthesis system for processor cores of digital signal processing has
been developed. This paper focuses on a hardware/software partitioning algorithm which is
one of the key issues in the system. Given an input assembly code generated by the
compiler in the system, the proposed hardware/software partitioning algorithm rst
determines the types and the numbers of required hardware units, such as multiple
functional units, hardware loop units, and particular addressing units, for a processor core …
been developed. This paper focuses on a hardware/software partitioning algorithm which is
one of the key issues in the system. Given an input assembly code generated by the
compiler in the system, the proposed hardware/software partitioning algorithm rst
determines the types and the numbers of required hardware units, such as multiple
functional units, hardware loop units, and particular addressing units, for a processor core …
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