Design space exploration is crucial to an optimal application mapping in Network-on-Chip. However, the optimality evaluation of the explored solution has been neglected in previous studies. In this paper, we propose an efficient and credible statistical estimation approach to evaluate the optimality of explored solutions with respect to the mapped communication, which is directly related to power dissipation in the network. Our approach is motivated by a basic statistical property on the solution space, and we consider the diversities in different complex on-chip network designs to make it more applicable. The statistical estimation and the optimality evaluation are validated in experiments by real and synthetic applications. It demonstrates an estimating error around 6% on average, which tends to be even smaller when problem scales up. We envision that the fidelity of our statistical estimation approach will promote its applicability in the promising Network-on-Chip designs.