User profiles for Chirag Sudarshan
Chirag SudarshanPost-Doc, Forschungszentrum Jülich Verified email at fz-juelich.de Cited by 472 |
Ultra-low power flexible precision FeFET based analog in-memory computing
This paper presents an efficient crossbar design and implementation intended for analog
compute-in-memory (ACiM) acceleration of artificial neural networks based on ferroelectric FET …
compute-in-memory (ACiM) acceleration of artificial neural networks based on ferroelectric FET …
Analog in-memory computing attention mechanism for fast and energy-efficient large language models
Transformer networks, driven by self-attention, are central to large language models. In
generative transformers, self-attention uses cache memory to store token projections, avoiding …
generative transformers, self-attention uses cache memory to store token projections, avoiding …
[BOOK][B] Processing-in-Memory DRAM Architectures for Neural Network Applications
C Sudarshan - 2024 - kluedo.ub.rptu.de
Emerging applications based on machine learning and Deep Neural Networks (DNNs) are
data-driven and memory-intensive. Hence, there is a recent shift from compute-centric …
data-driven and memory-intensive. Hence, there is a recent shift from compute-centric …
Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving
Autonomous driving is disrupting conventional automotive development. Underlying reasons
include control unit consolidation, the use of components originally developed for the …
include control unit consolidation, the use of components originally developed for the …
ZuSE Ki-Avf: application-specific AI processor for intelligent sensor signal processing in autonomous driving
Modern and future AI-based automotive applications, such as autonomous driving, require
the efficient real-time processing of huge amounts of data from different sensors, like camera, …
the efficient real-time processing of huge amounts of data from different sensors, like camera, …
A critical assessment of dram-pim architectures-trends, challenges and solutions
Recently, we are witnessing a surge in DRAM-based Processing in Memory (PIM) publications
from academia and industry. The architectures and design techniques proposed in these …
from academia and industry. The architectures and design techniques proposed in these …
A lean, low power, low latency DRAM memory controller for transprecision computing
Energy consumption is one of the major challenges for the advanced System on Chips (SoC).
This is addressed by adopting heterogeneous and approximate computing techniques. …
This is addressed by adopting heterogeneous and approximate computing techniques. …
An in-dram neural network processing engine
Many advanced neural network inference engines are bounded by the available memory
bandwidth. The conventional approach to address this issue is to employ high bandwidth …
bandwidth. The conventional approach to address this issue is to employ high bandwidth …
An analysis on retention error behavior and power consumption of recent DDR4 DRAMs
…, CC Rheinländer, C Sudarshan… - … , Automation & Test …, 2018 - ieeexplore.ieee.org
DRAM technology is scaling aggressively that results in high leakage power, worse data
retention time behavior, and large process variations. Due to these process variations, vendors …
retention time behavior, and large process variations. Due to these process variations, vendors …
Improving the error behavior of DRAM by exploiting its Z-channel property
In this paper, we present a new communication theoretic channel model for Dynamic Random
Access Memory (DRAM) retention errors, that relies on the fully asymmetric retention error …
Access Memory (DRAM) retention errors, that relies on the fully asymmetric retention error …