This work firstly investigates the problem of how designing data-driven (ie, toggling based)
clock gating can be closely integrated with the synthesis of flip-flops, which has never been
addressed in the prior clock gating works. Our key observation is that some internal part of a
flip-flop cell can be reused to generate its clock gating enable signal. Based on this, we
propose a newly optimized flip-flop wiring structure, called eXOR-FF, in which an internal
logic can be reused for every clock cycle to decide if the flip-flop is to be activated or …

In this paper, we introduce dynamic power optimization techniques applicable for various
design stage from standard cell to placement stage. This work firstly investigates the
problem of how designing data-driven (ie, toggling based) clock gating can be closely
integrated with the synthesis of flip-flops, which has never been addressed in the prior clock
gating works. Our key observation is that some internal part of a flip-flop cell can be reused
to generate its clock gating enable signal. Based on this, we propose a newly optimized flip …