This paper proposes a new spur reducing architecture of phase‐locked loop‐based frequency synthesizer. With an array of switched capacitors and a delay locked loop, the charge coming from its charge pump is evenly transferred to its loop filter at a fixed number of equi‐spaced time intervals. It results in the reduction of fundamental and higher‐order harmonics of the reference spur. The proposed architecture has been designed and fabricated in 180 nm CMOS technology. Randomization scheme has also been incorporated in the proposed architecture to reduce the effect of implementation mismatch on the output spur. Measured result shows about 5.47 dB reduction of fundamental spur compared to that of the conventional architecture with almost no degradation of noise performance. Copyright © 2014 John Wiley & Sons, Ltd.