Synthesis of linear-phase FIR filters with a complex exponential impulse response
XX Zheng, J Yang, SY Yang, W Chen… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
IEEE Transactions on Signal Processing, 2021•ieeexplore.ieee.org
In this paper, a novel recursive realization method with word length reduced is proposed to
synthesize linear-phase FIR filters for arbitrary bandwidth. By exploring the sparsity in the
frequency domain, it constructs the desired impulse response with few complex exponential
series (CES) and very sparse additional coefficients (AC) with equal length. The design
problem is formulated as a combinatorial optimization problem by confining the frequencies
of CES to a finite dictionary. To reduce the computational complexity at optimization, an …
synthesize linear-phase FIR filters for arbitrary bandwidth. By exploring the sparsity in the
frequency domain, it constructs the desired impulse response with few complex exponential
series (CES) and very sparse additional coefficients (AC) with equal length. The design
problem is formulated as a combinatorial optimization problem by confining the frequencies
of CES to a finite dictionary. To reduce the computational complexity at optimization, an …
In this paper, a novel recursive realization method with word length reduced is proposed to synthesize linear-phase FIR filters for arbitrary bandwidth. By exploring the sparsity in the frequency domain, it constructs the desired impulse response with few complex exponential series (CES) and very sparse additional coefficients (AC) with equal length. The design problem is formulated as a combinatorial optimization problem by confining the frequencies of CES to a finite dictionary. To reduce the computational complexity at optimization, an iterative algorithm is presented, where appropriate frequencies of CES and zero locations of AC can be quickly determined. Thereafter, an efficient parallel structure is introduced to implement the proposed filter. To verify the performance of the proposed method, MATLAB simulation and Field-programmable gate array (FPGA) implementation are made. It shows that the proposed method requires 18 bits × 23 bits word length while the existing advanced recursive realization method —the piecewise-polynomial-sinusoidal recursive—needs 59 bits × 59 bits for the same filter specifications. Meanwhile, the method can achieve comparable multiplier reduction compared with the state-of-the-art low-complexity techniques but produce a low extra group delay. Moreover, it can realize variable bandedges with a fixed filter structure.
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