- AutorIn
- Prof. Dr.-Ing. Wolfgang Lehner Technische Universität Dresden, Fakultät Informatik, Institut für Systemarchitektur, Professur Datenbanken
- Dr.-Ing. Tomas KarnagelTechnische Universität Dresden, Fakultät Informatik, Institut für Systemarchitektur, Dresden Database Research Group
- Roman Dementiev
- Ravi Rajwar
- Konrad Lai
- Thomas Legler
- Dr.-Ing. Benjamin Schlegel
- Titel
- Improving in-memory database index performance with Intel® Transactional Synchronization Extensions
- Zitierfähige Url:
- https://nbn-resolving.org/urn:nbn:de:bsz:14-qucosa2-819033
- Konferenz
- IEEE 20th International Symposium on High Performance Computer Architecture (HPCA). Orlando, 15.02.-19.02.2014
- Quellenangabe
- 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
Erscheinungsort: New York
Verlag: IEEE
Erscheinungsjahr: 2014
Seiten: 476-487 - Erstveröffentlichung
- 2014
- Abstract (EN)
- The increasing number of cores every generation poses challenges for high-performance in-memory database systems. While these systems use sophisticated high-level algorithms to partition a query or run multiple queries in parallel, they also utilize low-level synchronization mechanisms to synchronize access to internal database data structures. Developers often spend significant development and verification effort to improve concurrency in the presence of such synchronization. The Intel ® Transactional Synchronization Extensions (Intel ® TSX) in the 4th Generation Core™ Processors enable hardware to dynamically determine whether threads actually need to synchronize even in the presence of conservatively used synchronization. This paper evaluates the effectiveness of such hardware support in a commercial database. We focus on two index implementations: a B+Tree Index and the Delta Storage Index used in the SAP HANA ® database system. We demonstrate that such support can improve performance of database data structures such as index trees and presents a compelling opportunity for the development of simpler, scalable, and easy-to-verify algorithms.
- Andere Ausgabe
- Link zum Artikel, der zuerst in der IEEE Xplore Digital Library erschienen ist.
DOI: 10.1109/HPCA.2014.6835957 - Freie Schlagwörter (DE)
- Indizes, Hardware, Synchronisierung, Programm-Prozessoren, Sockets, Wörterbücher
- Freie Schlagwörter (EN)
- Indexes, Hardware, Synchronization, Program processors, Sockets, Dictionaries
- Klassifikation (DDC)
- 004
- Verlag
- IEEE, New York
- Förder- / Projektangaben
- Deutsche Forschungsgemeinschaft (DFG)
Exzellenzcluster
Center for Advancing Electronics Dresden
(cfaed)
ID: 194636624 - Version / Begutachtungsstatus
- angenommene Version / Postprint / Autorenversion
- URN Qucosa
- urn:nbn:de:bsz:14-qucosa2-819033
- Veröffentlichungsdatum Qucosa
- 12.01.2023
- Dokumenttyp
- Konferenzbeitrag
- Sprache des Dokumentes
- Englisch
- Lizenz / Rechtehinweis