VIA C3
| General Details | Name | VIA C3 | |
| Codename |
Nehemiah C5XL (1x RNG) Nehemiah C5P (2x RNG, ACE) Nehemiah C5Q (0.13 µm TSMC C5P with VIA bus) Nehemiah C5R (0.11 µm TSMC C5P with VIA bus) Esther C5I (2x RNG, ACE, SHA-1) Esther C5J (2x RNG, ACE, SHA-1, SHA-256, MontMul) aka C7 C3 (desktop) Antaur (mobile) Eden (embedded) |
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| Family/Generation | 80586, 6th Generation, MMX, SSE, SSE2/SSE3 (0.09 µm) | ||
| Vendor | Centaur | ||
| Manufacturer |
TSMC (0.13 µm) IBM (0.09 µm) |
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| First Introduction |
Jan 22, 2003 (1000B MHz 0.13 µm C3) Mar 13, 2003 (Mark CoreFusion = C3/NB/GFX/RAM module) Jul 8, 2003 (1000B MHz 0.13 µm Antaur) Aug 19, 2003 (733B MHz 0.13 µm Eden ESP 7000) Oct 14, 2003 (533B, 800B, and 1000B MHz 0.13 µm Eden-N) Feb 10, 2004 (800B MHz 0.13 µm Eden ESP 8000) Feb 10, 2004 (1000B MHz 0.13 µm Eden ESP 10000) Apr 29, 2004 (1200B MHz 0.13 µm Eden ESP 12000) May 18, 2004 (Esther C5J name announced) Sep 17, 2004 (Esther C7 name announced) Jan 31, 2005 (1300C MHz 0.13 µm Eden ESP 13000) Mar 8, 2005 (Luke CoreFusion = Eden-N/NB/GFX/RAM module) May 27, 2005 (Esther C7 details announced) Jan 17, 2006 (400, 500, 600, 800, 1000, and 1200 MHz C7) Jan 17, 2006 (1000 and 1500 MHz C7 ULV) |
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| Physical Details | Package Type |
370 Pin CPGA 368 Ball EBGA 324 Ball nanoBGA ??? Ball nanoBGA2 (C7) |
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| Package Size |
4.95 cm x 4.95 cm (CPGA) 3.50 cm x 3.50 cm (EBGA) 1.50 cm x 1.50 cm (nanoBGA) 2.10 cm x 2.10 cm (nanoBGA2) |
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| Socket or Slot |
Socket 370 (CPGA) Proprietary (EBGA) Proprietary (nanoBGA) Proprietary (nanoBGA2) |
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| Transistors |
20,500,000 (0.13 µm, includes 2x 64 KB L1 + 64 KB L2, C5XL) 20,400,000 (0.13 µm, includes 2x 64 KB L1 + 64 KB L2, C5P) 26,200,000 (0.09 µm, includes 2x 64 KB L1 + 128 KB L2, C7) |
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| Process Technology |
7M, 0.13 µm, CMOS, Cu ?M, 0.09 µm, CMOS, Cu, SOI |
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| Die Size |
52 mm² (0.13 µm C5XL) 47 mm² (0.13 µm C5P) 31.7 mm² (0.09 µm C7) |
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| Electrical Details | Split Voltage | Yes (automatically determined via VID pins) | |
| Core Voltage |
1.40 V (0.13 µm) 1.25 V (0.13 µm) ??? V (0.09 µm) |
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| I/O Voltage | 3.3 V | ||
| Typical Power |
1000B MHz: 15 W (0.13 µm CPGA @ 1.45 V @ 70 C) 1133B MHz: 15 W (0.13 µm CPGA @ 1.45 V @ 70 C) 1200B MHz: 19 W (0.13 µm CPGA @ 1.45 V @ 70 C) 1000B MHz: 7 W (0.13 µm EBGA @ 1.05 V @ 85 C) 1000B MHz: 11 W (0.13 µm EBGA @ 1.25 V @ 85 C) 1133B MHz: 12 W (0.13 µm EBGA @ 1.25 V @ 85 C) 1200B MHz: 12 W (0.13 µm EBGA @ 1.25 V @ 85 C) 1333B MHz: 18 W (0.13 µm EBGA @ 1.45 V @ 85 C) 1400B MHz: 19 W (0.13 µm EBGA @ 1.45 V @ 85 C) 1200C MHz: 12 W (0.13 µm EBGA @ 1.45 V @ 85 C) 1300C MHz: 18 W (0.13 µm EBGA @ 1.45 V @ 85 C) 1400C MHz: 19 W (0.13 µm EBGA @ 1.45 V @ 85 C) 533B MHz: 2.5 W (0.13 µm nanoBGA @ 0.90 V @ 85 C) 733B MHz: 3.0 W (0.13 µm nanoBGA @ 0.90 V @ 85 C) 800B MHz: 5.0 W (0.13 µm nanoBGA @ 0.95 V @ 85 C) 1000B MHz: 7.0 W (0.13 µm nanoBGA @ 1.00 V @ 85 C) note: always add 0.30 W for I/O |
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| Maximum Power |
1000B MHz: ??? W (0.13 µm CPGA @ 1.45 V @ 70 C) 1133B MHz: ??? W (0.13 µm CPGA @ 1.45 V @ 70 C) 1200B MHz: ??? W (0.13 µm CPGA @ 1.45 V @ 70 C) 1000B MHz: ??? W (0.13 µm EBGA @ 1.05 V @ 85 C) 1000B MHz: ??? W (0.13 µm EBGA @ 1.25 V @ 85 C) 1133B MHz: ??? W (0.13 µm EBGA @ 1.25 V @ 85 C) 1200B MHz: ??? W (0.13 µm EBGA @ 1.25 V @ 85 C) 1333B MHz: ??? W (0.13 µm EBGA @ 1.45 V @ 85 C) 1400B MHz: ??? W (0.13 µm EBGA @ 1.45 V @ 85 C) 1200C MHz: ??? W (0.13 µm EBGA @ 1.45 V @ 85 C) 1300C MHz: ??? W (0.13 µm EBGA @ 1.45 V @ 85 C) 1400C MHz: ??? W (0.13 µm EBGA @ 1.45 V @ 85 C) 533B MHz: ??? W (0.13 µm nanoBGA @ 0.90 V @ 85 C) 733B MHz: ??? W (0.13 µm nanoBGA @ 0.90 V @ 85 C) 800B MHz: ??? W (0.13 µm nanoBGA @ 0.95 V @ 85 C) 1000B MHz: ??? W (0.13 µm nanoBGA @ 1.00 V @ 85 C) note: always add 1.20 W for I/O |
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| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed |
533B, 733B, 800B, 1000B, 1200B, 1300C MHz (0.13 µm) 400, 500, 600, 800, 1000, 1200, 1500 MHz (0.09 µm) |
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| L1 Cache Speed | 1.0x Core Speed | ||
| L2 Cache Speed | 1.0x Core Speed | ||
| External Bus Speed |
133 (aka B) or 200 (aka C) MHz P6 bus (0.13 µm) 100 MHz Quad-Pumped P4 bus with enhancements (0.09 µm) overlapped write response cycles (higher write bandwidth), sparse write-combining, linear addressing modes, 4 address cycles per clock instead of 2 (fewer pins), 32-bit data mode (fewer pins) |
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| Core/Bus Ratio |
4.0x, 5.5x, 6.0x, 6.5x, 7.5x, 9.0x (0.13 µm) 4.0x, 5.0x, 6.0x, 8.0x, 10.0x, 12.0x, 15.0x (0.09 µm) |
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| Miscellaneous | usual Motherboard | Single Processor Socket 370 or Proprietary | |
| usual Chipset | non-Intel | ||
| Pictures |
0.13 µm C5P Die (75 KB JPG) 0.09 µm C7 Die (286 KB JPG) CPGA and EBGA Top (48 KB JPG) EBGA Top and Bottom (32 KB JPG) nanoBGA Top and Bottom (44 KB JPG) nanoBGA2 Top and Bottom (64 KB JPG) EBGA and nanoBGA Top (37 KB JPG) Mark CoreFusion Top (34 KB JPG) | ||
| Processor Core | Generic Details | RISC, In-order and Pipelined Execution | |
| Specific Details | Single Pipeline Design | ||
| Registers |
32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE separate FP and MM |
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| Pipeline Depth |
16 Stages (includes 9 RISC Stages for Execution), 6 additional Stages for FPU Instructions ??? Instruction Integer-to-FP FIFO Queue |
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| Instruction Decoder | 1x IA-32/Cycle, up to ??? µOPs/Cycle | ||
| Execution Units | Integer, AGU, Branch, Pipelined FP, Pipelined MMX, Pipelined SSE | ||
| Execution Speed | 1x IA-32/Cycle | ||
| Processor Buses | Address Bus Width | 32 Bit | |
| Data Bus Width | 64 Bit | ||
| Physical Memory | 2^32 Bit = 4 GB | ||
| Virtual Memory | 2^32 Bit = 4 GB | ||
| Logical Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | N/A | ||
| Power Management |
HLT, STPCLK, SMI/SMM, Sleep, Deep Sleep LongHaul Technology TM1, TM2, Dual PLL (0.09 µm) |
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| Processor Caches | Level 0 | N/A | |
| Level 1 | Code (C5XL) | 64 KB, 4-Way, 32 Byte/Line, pseudo-LRU | |
| Code (C5P) | 64 KB, 2-Way, 32 Byte/Line, pseudo-LRU | ||
| Code (C7) | 64 KB, 4-Way, 32 Byte/Line, pseudo-LRU | ||
| Data (C5XL) | 64 KB, 4-Way, 32 Byte/Line, pseudo-LRU | ||
| Data (C5P) | 64 KB, 2-Way, 32 Byte/Line, pseudo-LRU | ||
| Data (C7) | 64 KB, 4-Way, 32 Byte/Line, pseudo-LRU | ||
| Level 2 | Unified (0.13 µm) |
64 KB, 16-Way, 32 Byte/Line, pseudo-LRU?, Exclusive |
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| Unified (0.09 µm) |
128 KB, 32-Way, 32 Byte/Line, pseudo-LRU?, Exclusive |
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| Processor Buffers | Buffer | ??? Entry fetch/decode/xlate-to-execute FIFO (XIQ) | |
| Write Buffer | ??? Byte Store Queue / WC Buffer | ||
| Prefetch Queue | ??? Byte | ||
| Branch Prediction | Static | Yes | |
| Dynamic | ??? Entry ???-Way BTB | ||
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1-Bit Agree/Disagree (with Static Predictor, instead of 2-Bit Counters) for these three (???): 8,192 Simple Counters, 8,192 Entry Global History (G-Share), 8,192 Entry Select Table (for the above two) |
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| 1,024 Entry BTAC | |||
| RSB | ??? Entries, ???-Way | ||
| TLB | Code | 128 Entries, 8-Way, pseudo-LRU | |
| Data | 128 Entries, 8-Way, pseudo-LRU | ||
| Code PDC (PDEs) | ??? Entries, ???, pseudo-LRU | ||
| Data PDC (PDEs) | ??? Entries, ???, pseudo-LRU | ||
| Instruction Set | Regular | IA-32 | |
| Floating Point | Integrated | ||
| Multi Media | MMX, FEMMS, SSE, SSE2/SSE3 (0.09 µm) | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM | ||
