VIA C3
| General Details | Name |
VIA Cyrix III (0.18 µm) VIA C3 (0.15 µm and 0.13 µm) |
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| Codename |
C5A, Samuel (0.18 µm) C5B, Samuel 2 (0.15 µm) C5C, Samuel 3 or Ezra (0.13 µm) C5N, Ezra-T (0.13 µm, support for Tualatin bus) Eden (C5 bundled with a VIA North and South Bridge) |
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| Family/Generation | 80586, 5th Generation, MMX, 3DNow! | ||
| Vendor | Centaur | ||
| Manufacturer | TSMC | ||
| First Introduction |
Aug 5, 1999 (VIA/Centaur Aquisition announced) Sep 16, 1999 (VIA/Centaur Aquisition final, $51M) Jun 6, 2000 (533..667 MHz 0.18 µm) Sep 20, 2000 (500..600 MHz 0.18 µm mobile) Nov 30, 2000 (650 and 667 MHz 0.18 µm) Dec 12, 2000 (0.13 µm samples) Jan 12, 2001 (700 MHz 0.18 µm) Mar 25, 2001 (733 MHz 0.15 µm) May 28, 2001 (750 MHz 0.15 µm) Jun 5, 2001 (800 MHz 0.13 µm) Sep 11, 2001 (866 MHz 0.13 µm) Dec 11, 2001 (Eden) Dec 19, 2001 (933 MHz 0.13 µm) Jun 3, 2002 (1000 MHz 0.13 µm) |
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| Physical Details | Package Type |
370 Pin CPGA 336 Ball EBGA (0.13 µm) 496 Pin µPGA (0.13 µm) 478 Pin µBGA (0.13 µm) |
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| Package Size |
4.95 cm x 4.95 cm (CPGA) 3.50 cm x 3.50 cm (EBGA) ??? cm x ??? cm (µPGA) ??? cm x ??? cm (µBGA) |
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| Socket or Slot |
Socket 370 (CPGA) Proprietary (EBGA) Proprietary (µPGA) Proprietary (µBGA) |
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| Transistors |
11,300,000 (0.18 µm, includes 2x 64 KB L1 Cache) 15,200,000 (0.15 µm, includes 2x 64 KB L1 and 64 KB L2 Cache) 15,400,000 (0.13 µm, includes 2x 64 KB L1 and 64 KB L2 Cache) 15,500,000 (0.13 µm, includes 2x 64 KB L1 and 64 KB L2 Cache) |
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| Process Technology |
???M, 0.18 µm, CMOS ???M, 0.15 µm, CMOS 7M, 0.13 µm, CMOS 7M, 0.13 µm, CMOS, Cu |
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| Die Size |
75 mm² (0.18 µm) 52 mm² (0.15 µm) 52 mm² (0.13 µm Process, but 0.15 µm Geometry) 56 mm² (0.13 µm Process, but 0.15 µm Geometry) |
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| Electrical Details | Split Voltage | Yes (automatically determined via VID pins) | |
| Core Voltage |
2.0 V (0.18 µm) 1.9 V (0.18 µm) 1.6 V (0.15 µm) 1.35 V (0.13 µm) |
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| I/O Voltage | 3.3 V | ||
| Typical Power |
400 MHz: 3.0 W (0.18 µm @ 1.5 V) 500 MHz: 6.8 W (0.18 µm @ 1.9 V) 500 MHz: 7.5 W (0.18 µm @ 2.0 V) 550 MHz: 7.3 W (0.18 µm @ 1.9 V) 550 MHz: 8.1 W (0.18 µm @ 2.0 V) 600 MHz: 7.8 W (0.18 µm @ 1.9 V) 600 MHz: 8.6 W (0.18 µm @ 2.0 V) 650 MHz: 8.4 W (0.18 µm @ 1.9 V) 650 MHz: 9.3 W (0.18 µm @ 2.0 V) 667 MHz: 8.7 W (0.18 µm @ 1.9 V) 667 MHz: 9.6 W (0.18 µm @ 2.0 V) 700 MHz: 9.2 W (0.18 µm @ 1.9 V) 700 MHz: 10.2 W (0.18 µm @ 2.0 V) 733 MHz: 9.6 W (0.18 µm @ 1.9 V) 733 MHz: 10.6 W (0.18 µm @ 2.0 V) 750 MHz: 9.8 W (0.18 µm @ 1.9 V) 750 MHz: 10.9 W (0.18 µm @ 2.0 V) 800 MHz: 10.4 W (0.18 µm @ 1.9 V) 800 MHz: 11.5 W (0.18 µm @ 2.0 V) 300 MHz: 1.4 W (0.15 µm @ 1.05 V) 400 MHz: 1.7 W (0.15 µm @ 1.05 V) 533 MHz: 2.8 W (0.15 µm @ 1.20 V) 600 MHz: 3.2 W (0.15 µm @ 1.20 V) 667 MHz: 6.0 W (0.15 µm @ 1.6 V) 733 MHz: 6.6 W (0.15 µm @ 1.6 V) 733 MHz: 5.81 W (0.15 µm @ 1.6 V) 733 MHz: 6.09 W (0.15 µm @ 1.6 V) 750 MHz: 6.23 W (0.15 µm @ 1.6 V) 800 MHz: 6.65 W (0.15 µm @ 1.6 V) 733 MHz: 4.4 W (0.13 µm @ 1.05 V) 800 MHz: 5.0 W (0.13 µm @ 1.35 V) 850 MHz: 5.5 W (0.13 µm @ 1.35 V) 866 MHz: 5.6 W (0.13 µm @ 1.35 V) 900 MHz: 5.7 W (0.13 µm @ 1.35 V) 933 MHz: 5.9 W (0.13 µm @ 1.35 V) 1000 MHz: 17.8 W (0.13 µm @ 1.40 V) 1000 MHz: 11.8 W (0.13 µm @ 1.25 V) note: always add 0.30 W for I/O |
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| Maximum Power |
400 MHz: 5.6 W (0.18 µm @ 1.5 V) 500 MHz: 11.2 W (0.18 µm @ 1.9 V) 500 MHz: 12.4 W (0.18 µm @ 2.0 V) 550 MHz: 12.2 W (0.18 µm @ 1.9 V) 550 MHz: 13.5 W (0.18 µm @ 2.0 V) 600 MHz: 13.1 W (0.18 µm @ 1.9 V) 600 MHz: 14.5 W (0.18 µm @ 2.0 V) 650 MHz: 14.2 W (0.18 µm @ 1.9 V) 650 MHz: 15.7 W (0.18 µm @ 2.0 V) 667 MHz: 14.5 W (0.18 µm @ 1.9 V) 667 MHz: 16.1 W (0.18 µm @ 2.0 V) 700 MHz: 15.3 W (0.18 µm @ 1.9 V) 700 MHz: 16.9 W (0.18 µm @ 2.0 V) 733 MHz: 16.0 W (0.18 µm @ 1.9 V) 733 MHz: 17.7 W (0.18 µm @ 2.0 V) 750 MHz: 16.3 W (0.18 µm @ 1.9 V) 750 MHz: 16.3 W (0.18 µm @ 2.0 V) 800 MHz: 18.1 W (0.18 µm @ 1.9 V) 800 MHz: 19.3 W (0.18 µm @ 2.0 V) 300 MHz: 2.5 W (0.15 µm @ 1.05 V) 400 MHz: 3.0 W (0.15 µm @ 1.05 V) 533 MHz: 5.0 W (0.15 µm @ 1.20 V) 600 MHz: 6.0 W (0.15 µm @ 1.20 V) 667 MHz: 10.1 W (0.15 µm @ 1.6 V) 733 MHz: 11.1 W (0.15 µm @ 1.6 V) 733 MHz: 9.88 W (0.15 µm @ 1.6 V) 733 MHz: 10.35 W (0.15 µm @ 1.6 V) 750 MHz: 10.59 W (0.15 µm @ 1.6 V) 800 MHz: 11.30 W (0.15 µm @ 1.6 V) 733 MHz: 6.0 W (0.13 µm @ 1.05 V) 800 MHz: 8.3 W (0.13 µm @ 1.35 V) 850 MHz: 9.0 W (0.13 µm @ 1.35 V) 866 MHz: 9.2 W (0.13 µm @ 1.35 V) 900 MHz: 9.4 W (0.13 µm @ 1.35 V) 933 MHz: 10.0 W (0.13 µm @ 1.35 V) 1000 MHz: 18.5 W (0.13 µm @ 1.40 V) 1000 MHz: 12.0 W (0.13 µm @ 1.25 V) note: always add 0.82 W for I/O (or 1.20 W for 1 GHz parts) |
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| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed |
0.18 µm 100 MHz bus: 500, 550, 600, 650, 700 MHz 0.18 µm 133 MHz bus: 600, 667, 733 MHz 0.15 µm 100 MHz bus: 750 MHz 0.15 µm 133 MHz bus: 733 MHz 0.13 µm 100 MHz bus: 800 MHz 0.13 µm 133 MHz bus: 866 MHz |
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| L1 Cache Speed | 1.0x Core Speed | ||
| L2 Cache Speed |
n/a (0.18 µm) 1.0x Core Speed (0.15 µm and 0.13 µm) |
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| External Bus Speed |
66, 100, or 133 MHz, GTL+ up to 4 outstanding Transactions (0.18 µm) up to 8 outstanding Transactions (0.15 µm and 0.13 µm) |
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| Core/Bus Ratio | 4.5x, 5.0x, 5.5x, 6.0x, 6.5x, 7.0x, 7.5x, 8.0x | ||
| Miscellaneous | usual Motherboard | Single Processor Socket 370 | |
| usual Chipset | non-Intel | ||
| Pictures |
0.18 µm C5 Top (34 KB JPG) 0.18 µm C5A Top (82 KB JPG) 0.18 µm C5A Top and Bottom (108 KB JPG) 0.18 µm C5B Bottom (124 KB JPG) 0.15 µm C5B Top and Bottom (137 KB JPG) 0.13 µm C5C Top and Bottom (185 KB JPG) 0.13 µm C5N Top and Bottom (147 KB JPG) CPGA Top (52 KB JPG) and Bottom (115 KB JPG) EBGA Top (46 KB JPG) and Bottom (117 KB JPG) µPGA Top (19 KB JPG) and Bottom (88 KB JPG) µBGA Top (51 KB JPG) and Bottom (124 KB JPG) | ||
| Processor Core | Generic Details | RISC, In-order and Pipelined Execution | |
| Specific Details | Single Pipeline Design | ||
| Registers | 32 Bit Integer, 80 Bit FP, 64 Bit MM, separate FP and MM | ||
| Pipeline Depth |
12 Stages (includes 7 RISC Stages for Execution), 6 additional Stages for FPU Instructions 8 Instruction Integer-to-FP FIFO Queue (0.15 µm and 0.13 µm) |
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| Instruction Decoder | 1x IA-32/Cycle, up to 3 µOPs/Cycle | ||
| Execution Units |
Integer, Partially Pipelined FPU (1/2 Core Speed), Fully Pipelined MMX, Fully Pipelined 3DNow! |
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| Execution Speed | 1x IA-32/Cycle | ||
| Processor Buses | Address Bus Width | 32 Bit | |
| Data Bus Width | 64 Bit | ||
| Physical Memory | 2^32 Bit = 4 GB | ||
| Virtual Memory | 2^32 Bit = 4 GB | ||
| Logical Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | N/A | ||
| Power Management | HLT, STPCLK, SMI/SMM | ||
| Processor Caches | Level 0 | N/A | |
| Level 1 | Code | 64 KB, 4-Way, 32 Byte/Line, pseudo-LRU | |
| Data | 64 KB, 4-Way, 32 Byte/Line, pseudo-LRU | ||
| Level 2 | Unified (0.18 µm) | N/A | |
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Unified (0.15 µm) Unified (0.13 µm) |
64 KB, 4-Way, 32 Byte/Line, pseudo-LRU, Exclusive |
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| Processor Buffers | Buffer | 5 Entry fetch/decode/xlate-to-execute FIFO (XIQ) | |
| Write Buffer | 4x 8 Byte Store Queue / WC Buffer | ||
| Prefetch Queue | 3x 16 Byte | ||
| Branch Prediction | Static | Yes | |
| Dynamic (0.18 µm) | 64 Entry 4-Way BTB | ||
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1-Bit Agree/Disagree (with Static Predictor, instead of 2-Bit Counters) for these three: 4,096 Simple Counters, 4,096 Entry Global History (G-Share), 4,096 Entry Select Table (for the above two) |
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Dynamic (0.15 µm) Dynamic (0.13 µm) |
128 Entry 8-Way BTB | ||
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1-Bit Agree/Disagree (with Static Predictor, instead of 2-Bit Counters) for these three: 8,192 Simple Counters, 8,192 Entry Global History (G-Share), 8,192 Entry Select Table (for the above two) |
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| RSB | 16 Entries, 4-Way | ||
| TLB | Code | 128 Entries, 8-Way, pseudo-LRU | |
| Data | 128 Entries, 8-Way, pseudo-LRU | ||
| Code PDC (PDEs) | 8 Entries, ???, pseudo-LRU | ||
| Data PDC (PDEs) | 8 Entries, ???, pseudo-LRU | ||
| Instruction Set | Regular | IA-32 | |
| Floating Point | Integrated | ||
| Multi Media | MMX, 3DNow! | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM | ||
