sparcv8 函数输入参数的寄存器分配策略-CSDN博客

static const int hard_32bit_mode_classes[] = {
  S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
  T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
  T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
  T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,

  OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
  OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
  OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
  OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,

  /* FP regs f32 to f63.  Only the even numbered registers actually exist,
     and none can hold SFmode/SImode values.  */
  OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
  OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
  OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
  OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,

  /* %fcc[0123] */
  CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,

  /* %icc, %sfp, %gsr */
  CC_MODES, 0, D_MODES
};

static void
sparc_init_modes (void)
{
  int i;

  for (i = 0; i < NUM_MACHINE_MODES; i++)
    {
      machine_mode m = (machine_mode) i;
      unsigned int size = GET_MODE_SIZE (m);

      switch (GET_MODE_CLASS (m))
	{
	case MODE_INT:
	case MODE_PARTIAL_INT:
	case MODE_COMPLEX_INT:
	  if (size < 4)
	    sparc_mode_class[i] = 1 << (int) H_MODE;
	  else if (size == 4)
	    sparc_mode_class[i] = 1 << (int) S_MODE;
	  else if (size == 8)
	    sparc_mode_class[i] = 1 << (int) D_MODE;
	  else if (size == 16)
	    sparc_mode_class[i] = 1 << (int) T_MODE;
	  else if (size == 32)
	    sparc_mode_class[i] = 1 << (int) O_MODE;
	  else
	    sparc_mode_class[i] = 0;
	  break;
	case MODE_VECTOR_INT:
	  if (size == 4)
	    sparc_mode_class[i] = 1 << (int) SF_MODE;
	  else if (size == 8)
	    sparc_mode_class[i] = 1 << (int) DF_MODE;
	  else
	    sparc_mode_class[i] = 0;
	  break;
	case MODE_FLOAT:
	case MODE_COMPLEX_FLOAT:
	  if (size == 4)
	    sparc_mode_class[i] = 1 << (int) SF_MODE;
	  else if (size == 8)
	    sparc_mode_class[i] = 1 << (int) DF_MODE;
	  else if (size == 16)
	    sparc_mode_class[i] = 1 << (int) TF_MODE;
	  else if (size == 32)
	    sparc_mode_class[i] = 1 << (int) OF_MODE;
	  else
	    sparc_mode_class[i] = 0;
	  break;
	case MODE_CC:
	  if (m == CCFPmode || m == CCFPEmode)
	    sparc_mode_class[i] = 1 << (int) CCFP_MODE;
	  else
	    sparc_mode_class[i] = 1 << (int) CC_MODE;
	  break;
	default:
	  sparc_mode_class[i] = 0;
	  break;
	}
    }

  if (TARGET_ARCH64)
    hard_regno_mode_classes = hard_64bit_mode_classes;
  else
    hard_regno_mode_classes = hard_32bit_mode_classes;

  /* Initialize the array used by REGNO_REG_CLASS.  */
  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
    {
      if (i < 16 && TARGET_V8PLUS)
	sparc_regno_reg_class[i] = I64_REGS;
      else if (i < 32 || i == FRAME_POINTER_REGNUM)
	sparc_regno_reg_class[i] = GENERAL_REGS;
      else if (i < 64)
	sparc_regno_reg_class[i] = FP_REGS;
      else if (i < 96)
	sparc_regno_reg_class[i] = EXTRA_FP_REGS;
      else if (i < 100)
	sparc_regno_reg_class[i] = FPCC_REGS;
      else
	sparc_regno_reg_class[i] = NO_REGS;
    }
}

/* Implement TARGET_HARD_REGNO_MODE_OK.

   ??? Because of the funny way we pass parameters we should allow certain
   ??? types of float/complex values to be in integer registers during
   ??? RTL generation.  This only matters on arch32.  */

static bool
sparc_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
  return (hard_regno_mode_classes[regno] & sparc_mode_class[mode]) != 0;
}

// Dump full hard_regno_mode_classes (typically 0 to FIRST_PSEUDO_REGISTER)
    fprintf(stderr, "Full hard_regno_mode_classes[]:\n");
    for (int i = 0; i < FIRST_PSEUDO_REGISTER; i++) {
        fprintf(stderr, "  [%2d] = 0x%x\n", i, hard_regno_mode_classes[i]);
    }

    // Dump full sparc_mode_class[]
//    extern const char * const mode_name[]; // If not already declared
    fprintf(stderr, "Full sparc_mode_class[]:\n");
    for (int i = 0; i < NUM_MACHINE_MODES; i++) {
        fprintf(stderr, "  [%2d] (%s) = 0x%x\n", i, GET_MODE_NAME((machine_mode)i), sparc_mode_class[i]);
    }

    fprintf(stderr, "============================\n");

Full hard_regno_mode_classes[]:
  [ 0] = 0x23
  [ 1] = 0x23
  [ 2] = 0xef
  [ 3] = 0x23
  [ 4] = 0xef
  [ 5] = 0x23
  [ 6] = 0x67
  [ 7] = 0x23
  [ 8] = 0xef
  [ 9] = 0x23
  [10] = 0xef
  [11] = 0x23
  [12] = 0x67
  [13] = 0x23
  [14] = 0x67
  [15] = 0x23
  [16] = 0xef
  [17] = 0x23
  [18] = 0xef
  [19] = 0x23
  [20] = 0xef
  [21] = 0x23
  [22] = 0x67
  [23] = 0x23
  [24] = 0xef
  [25] = 0x23
  [26] = 0xef
  [27] = 0x23
  [28] = 0x67
  [29] = 0x23
  [30] = 0x67
  [31] = 0x23
  [32] = 0x1e6
  [33] = 0x22
  [34] = 0x66
  [35] = 0x22
  [36] = 0x1e6
  [37] = 0x22
  [38] = 0x66
  [39] = 0x22
  [40] = 0x1e6
  [41] = 0x22
  [42] = 0x66
  [43] = 0x22
  [44] = 0x1e6
  [45] = 0x22
  [46] = 0x66
  [47] = 0x22
  [48] = 0x1e6
  [49] = 0x22
  [50] = 0x66
  [51] = 0x22
  [52] = 0x1e6
  [53] = 0x22
  [54] = 0x66
  [55] = 0x22
  [56] = 0x1e6
  [57] = 0x22
  [58] = 0x66
  [59] = 0x22
  [60] = 0xe6
  [61] = 0x22
  [62] = 0x66
  [63] = 0x22
  [64] = 0x1c4
  [65] = 0x0
  [66] = 0x44
  [67] = 0x0
  [68] = 0x1c4
  [69] = 0x0
  [70] = 0x44
  [71] = 0x0
  [72] = 0x1c4
  [73] = 0x0
  [74] = 0x44
  [75] = 0x0
  [76] = 0x1c4
  [77] = 0x0
  [78] = 0x44
  [79] = 0x0
  [80] = 0x1c4
  [81] = 0x0
  [82] = 0x44
  [83] = 0x0
  [84] = 0x1c4
  [85] = 0x0
  [86] = 0x44
  [87] = 0x0
  [88] = 0x1c4
  [89] = 0x0
  [90] = 0x44
  [91] = 0x0
  [92] = 0xc4
  [93] = 0x0
  [94] = 0x44
  [95] = 0x0
  [96] = 0x400
  [97] = 0x400
  [98] = 0x400
  [99] = 0x400
  [100] = 0x200
  [101] = 0x0
  [102] = 0x67

Full sparc_mode_class[]:
  [ 0] (VOID) = 0x0
  [ 1] (BLK) = 0x0
  [ 2] (CC) = 0x200
  [ 3] (CCX) = 0x200
  [ 4] (CCNZ) = 0x200
  [ 5] (CCXNZ) = 0x200
  [ 6] (CCC) = 0x200
  [ 7] (CCXC) = 0x200
  [ 8] (CCV) = 0x200
  [ 9] (CCXV) = 0x200
  [10] (CCFP) = 0x400
  [11] (CCFPE) = 0x400
  [12] (BI) = 0x1
  [13] (QI) = 0x1
  [14] (HI) = 0x1
  [15] (SI) = 0x2
  [16] (DI) = 0x4
  [17] (TI) = 0x8
  [18] (QQ) = 0x0
  [19] (HQ) = 0x0
  [20] (SQ) = 0x0
  [21] (DQ) = 0x0
  [22] (TQ) = 0x0
  [23] (UQQ) = 0x0
  [24] (UHQ) = 0x0
  [25] (USQ) = 0x0
  [26] (UDQ) = 0x0
  [27] (UTQ) = 0x0
  [28] (HA) = 0x0
  [29] (SA) = 0x0
  [30] (DA) = 0x0
  [31] (TA) = 0x0
  [32] (UHA) = 0x0
  [33] (USA) = 0x0
  [34] (UDA) = 0x0
  [35] (UTA) = 0x0
  [36] (SF) = 0x20
  [37] (DF) = 0x40
  [38] (TF) = 0x80
  [39] (SD) = 0x0
  [40] (DD) = 0x0
  [41] (TD) = 0x0
  [42] (CQI) = 0x1
  [43] (CHI) = 0x2
  [44] (CSI) = 0x4
  [45] (CDI) = 0x8
  [46] (CTI) = 0x10
  [47] (SC) = 0x40
  [48] (DC) = 0x80
  [49] (TC) = 0x100
  [50] (V4QI) = 0x20
  [51] (V2HI) = 0x20
  [52] (V1SI) = 0x20
  [53] (V8QI) = 0x40
  [54] (V4HI) = 0x40
  [55] (V2SI) = 0x40
  [56] (V1DI) = 0x40
  [57] (V16QI) = 0x0
  [58] (V8HI) = 0x0
  [59] (V4SI) = 0x0
  [60] (V2DI) = 0x0