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![Fig. 5: All Digital Delay Locked Loop Architecture the digital controlled delay lines). a small pulse on the internal up_int hold the last status. This kind of this problem by using digital con PFDs are common for A they have a major drawback to be very susceptible to glit issing clock edges due to glitches cause fault detection. This AD-DLL solves trolled delay lines (DCD generate glitches when switched to a different delay value of the DCDL is constructed by using 32 glitch-free NAND- (DE) structure in a special three step switching scheme proposed by [18] (see Depending if clk_in or the delay_clk is leading or down_int port will be generated. To enable the digital DLL Controller to detect these ports a RS-NA D latch is used to 1-Digital DLLs, but ches at their input. L) that suppress to s. The coarse delay based delay element Fig. 6a). The fine delay is implemented by two standard invertes and a RC- Delay where the capacitor is trimmable with a 4bit resolution. The trimmable capacitor is build out of MOSFETS were drain and source are connected to the signal. By switching the gate to VDD or to VSS the capacitor changes its value.](https://figures.academia-assets.com/115704336/figure_005.jpg)
Figure 5 All Digital Delay Locked Loop Architecture the digital controlled delay lines). a small pulse on the internal up_int hold the last status. This kind of this problem by using digital con PFDs are common for A they have a major drawback to be very susceptible to glit issing clock edges due to glitches cause fault detection. This AD-DLL solves trolled delay lines (DCD generate glitches when switched to a different delay value of the DCDL is constructed by using 32 glitch-free NAND- (DE) structure in a special three step switching scheme proposed by [18] (see Depending if clk_in or the delay_clk is leading or down_int port will be generated. To enable the digital DLL Controller to detect these ports a RS-NA D latch is used to 1-Digital DLLs, but ches at their input. L) that suppress to s. The coarse delay based delay element Fig. 6a). The fine delay is implemented by two standard invertes and a RC- Delay where the capacitor is trimmable with a 4bit resolution. The trimmable capacitor is build out of MOSFETS were drain and source are connected to the signal. By switching the gate to VDD or to VSS the capacitor changes its value.
Related Figures (8)
![being accessed will be precharged at the end of the read or write access. Fur- ther, the DRAM device is issued an Auto-Refresh (AREF) command at every tREFI duration that internally performs refresh operation. Table 1 shows the key timings of DDR3 DRAM device and its values as defined in [12].](https://figures.academia-assets.com/115704336/table_001.jpg)
![t b ibra m DQ ») ust The bidirectional Data Bus consists of nine Data Transceivers, eight for data [7:0]) and one differential data strobe (DQS, nDQS). Each transceiver is im- lemented by seven parallel push-pull drivers where each of them has the pull-up OS) and the pull-down (NMOS) path calibrated by the Of-Chip Driver Cal- tion Unit to Rg; = 2402. The push-pull driver transistors are build with hick-oxide transistors (60A gate oxide thickness). This allows a simple and ro- ESD protection of the driver transistors and avoids complicated and fragile Ss tacked transistor design with thin-oxide transistors as presented in [15]. This seven parallel push-pull drivers can be individual selected to set the required on-chip-termination value and to implement different driving strengths depend- ing on write or read operations. The on-chip-termination impedance is then (Rari/Nari—set)/2 and off-chip-driver impedance Ra,i/Nari—set- Where Nari—sel is the number of selected drivers. The overall driver architecture is based on [16]. The reeeivere for the data trangeeivere are einole-ended receivers with their](https://figures.academia-assets.com/115704336/figure_003.jpg)
A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing
Abstract:Energy consumption is one of the major challenges for the advanced System on Chips (SoC). This is addressed by adopting heterogeneous and approximate computing techniques. One of the recent evolution in this context is transprecision computing paradigm. The idea of the transprecision computing is to consume adequate amount of energy for each operation by performing dynamic precision reduction. The impact of the memory subsystem plays a crucial role in such systems. Hence, the energy efficiency of a transprecision system can be further optimized by tailoring the memory subsystem to the transprecision computing. In this work, we present a lean, low power, low latency memory controller that is appropriate for transprecision methodology. The memory controller consumes an average power of 129.33 mW at a frequency of 500 MHz and has a total area of 4.71 mm 2 for UMC 65 nm process.