F70 Service Manual
F70 Service Manual
MANUAL
VHF TRANSCEIVER
INTRODUCTION
This service manual describes the latest service information
for the IC-F70DT/DS and IC-F70T/S VHF TRANSCEIVER
at the time of publication.
DANGER
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 7.2 V. This will ruin the
transceiver.
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
<SAMPLE ORDER>
1130010100 S.IC LMX2352TM IC-F70DS MAIN UNIT 5 pieces
8810010120 Screw PH B0 M2×8 SUS ZK IC-F70DS CHASSIS 10 pieces
REPAIR NOTES
1. Make sure a problem is internal before disassembling the transceiver.
2. DO NOT open the transceiver until the transceiver is disconnected from its power source.
3. DO NOT force any of the variable components. Turn them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the transceiver is defective.
6. DO NOT transmit power into a signal generator or a sweep generator.
7. ALWAYS connect a 50 dB to 60 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when
using such test equipment.
8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.
Icom, Icom Inc. and are registered trademarks of Icom Incorporated (Japan) in the United States, the United Kingdom,
Germany, France, Spain, Russia and/or other countries.
TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASSEMBLY INSTRUCTIONS
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVE CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 1
4-2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 3
4-3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 4
4-4 POWER SUPPLY CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 4
4-5 DIGITAL CIRCUIT (IC-F70DT/DS only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 5
4-6 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 5
SECTION 5 ADJUSTMENT PROCEDURES
5-1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 - 1
5-2 SOFTWARE ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 - 4
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS AND DISASSEMBLY
SECTION 8 SEMICONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
9-1 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 1
9-2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 3
9-3 FUSE BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 3
9-4 ANT BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 3
9-5 DSP UNIT (IC-F70DT/DS only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 5
9-6 VR BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 5
SECTION 10 BLOCK DIAGRAM
SECTION 11 VOLTAGE DIAGRAMS
11 - 1 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 - 1
11 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 - 2
11 - 3 DSP UNIT (IC-F70DT/DS only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 - 4
SECTION 1 SPECIFICATIONS
M GENERAL
• Frequency coverage : 136–174 MHz
• Type of emission : 11K0F3E (Narrow)
16K0F3E (Wide)
• Number of conventional channels : 256 channels (Max.)
• Antenna impedance : 50 Ω (Nominal)
• Operating temperature range : −22°F to 140°F
• Power supply requirement : Specified Icom's battery pack only
(Operatable voltage; 7.2 V DC negative ground)
• Current drain (At 7.2 V DC ; approx.) :
RECEIVING TRANSMITTING
Stand-by Max.audio High (5 W) Low (1 W)
150 mA 450 mA 2.2 A 1.5 A
• Dimensions (Projections not included) : 2 5/16 (W)× 5 31/32 (H)× 1 1/2 (D) in
• Weight (Except anntena, battery pack) : 8 13/16 oz (Approx.)
M TRANSMITTER
• Output power (At 7.2 V DC) : High; 5 W, Low; 1 W
• Modulation : Variable reactance frequency modulation
• Maximum permissible deviation : ±2.5 kHz (Narrow)
±5.0 kHz (Wide)
• Frequency error : ±2.00 ppm
• Spurious emissions : 70 dB typ.
• Adjacent channel power : 60 dB min. (Narrow)
70 dB min. (Wide)
• Audio harmonic distortion : 3% typ. at 40% deviation
• Limiting charactor of modulator : 60–100% of max. deviation
• FM hum and noise (Without CCITT filter) : 34 dB min. (40 dB typ. ; Narrow)
40 dB min. (45 dB typ. ; Wide)
• Audio frequency response : +2 dB to −8 dB of 6 dB/octave from 300 Hz to 2550 Hz (Narrow)
+2 dB to −8 dB of 6 dB/octave from 300 Hz to 3000 Hz (Wide)
• Microphone impedance : 2.2 kΩ
M RECEIVER
• Receive system : Double conversion superheterodyne system
• Intermediate frequencies : 1st IF; 46.35 MHz, 2nd IF; 450 kHz
• Sensitivity : 0.25 µV typ. at 12 dB SINAD
• Squelch sensitivity (At threshold) : 0.25 µV typ.
• Adjacent channel selectivity : 60 dB min. (70 dB typ. ; Narrow)
70 dB min. (75 dB typ. ; Wide)
• Spurious response : 70 dB min. (80 dB typ.)
• Intermodulation rejection ratio : 70 dB min. (73 dB typ.)
• Hum and Noise (Without CCITT filter) : 34 dB min. (40 dB typ. ; Narrow)
40 dB min. (45 dB typ. ; Wide)
• Audio output power : 0.5 W typ. at 10% distortion with an 8 Ω load
• Output impedance (Audio) :8 Ω
1-1
SECTION 2 INSIDE VIEWS
• FRONT UNIT
TOP VIEW BOTTOM VIEW
AF MUTEcontrol
Speaker
Q207: DTC144EU
Q209: RSR025N03
Q208: 2SC4116
Q210: RSR025N03
Q209: RSR025N03
Q210: RSR025N03
Microphone
(MC201: EM-140)
3.0V regulator
(IC101: S-812C30AMC-C2K)
Mic switch
Expanders
Expander (IC204: TC4S66F)
LCD (IC1, IC2: M62320FP)
(DS2: M4-0078TAY-2) Mic amplifier
(IC203: NJM12902V)
AF mute
mutingswitch
(IC205: TC4S66F)
AF amplifier
(IC201: TA7368F)
• MAIN UNIT
TOP VIEW BOTTOM VIEW
CPU5V regulator
Antenna switch (IC311: TK11250CM)
(D12, D22: 1SV307)
Power amplifier
(Q13: RD07MVS1) APC
ALC amplifier
amplifier
(IC5: TA75S01F)
YGR amplifier
(Q11: 2SC5110-O)
RF amplifier
(Q18: 3SK293)
VCO circuit
D/A converter
(IC310: M62334FP)
PLL IC
AF
D/Avolume
converter Mixer (IC1: LMX2352TM)
(IC303: M62364FP) (IC4: SPM5001)
FM
IF ICIF IC
(IC3: TA31136FN)
Audio processor
DSP unit (IC301: AK2346)
[IC-F70DT/DS]
[IC-F70DS/DT] only
DTMF
DecodeDECODE
IC Digital/Analog switch
(IC300: LC73872M) (IC302: BU4053BCFV)
EEPROM
(IC308: HN58X24128FPI) CPU
(IC307: HD64F2268TF)
2-1
SECTION 3 DISASSEMBLY INSTRUCTIONS
F J I ×9
A E
B E
*O-ring E DSP unit
K
I ×3
ANT
K
K
I ×2
J3 K
J2
* Be careful not to H
lost the O-rings.
MAIN unit
5 Disconnect the cable G from J1 and remove the CHASSIS
unit from the front panel.
G
L
J201
M
J2
J1
Front panel
Front panel
FRONT unit
3-1
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS The signals from the two-stage tunable BPF are converted
4-1-1 ANTENNA SWITCHING CIRCUIT into the 46.35 MHz 1st IF signal at the double-balanced
The antenna switching circuit toggles the receive line and type 1st mixer (IC14, L30, L31, L33) by being mixed with
the transmit line. This circuit does not allow transmit signals the 1st LO signal generated at the RX VCOs (Q4, D4, D5,
to enter the receiver circuits. D24, D26 or Q20, D27 to D30).
Received signals from the antenna connector (CHASSIS The 1st IF signal from the 1st mixer is passed through the
UNIT; J1) are passed through a two-stage low-pass filter crystal filter (FI3) to suppress unwanted signals, and then
(LPF; L22, L23, C204–C207, C209) and applied to the λ/4 amplified at the 1st IF amplifier (Q17). The amplified 1st IF
type antenna switching circuit (D12, D22). signal is applied to the FM IF IC (IC3, pin 16).
4-1-3 1st IF CIRCUITS The filtered signal is applied to IC3 (pin 5) again, and
The 1st mixer circuit converts the received signals into fixed amplified at the limiter amplifier section and demodulated
frequency of the 1st intermediate frequency (IF) signal by the quadrature detector.
by mixing with the local oscillator (LO) signals which con-
trolled by the PLL circuit. The IF is shifted by changing LO
frequency to track the receive signal. The converted 1st IF
signal is filtered at the 1st IF filter, then amplified at the 1st
IF amplifier.
4-1
The quadrature detector is a detection method which uses a demodulated AF signals, the squelch circuit switches the
ceramic discriminator (X2). AF mute swithch and AF power amplifier controller ON and
OFF.
The demodulated AF signals are output from pin 9, and
applied to the AF cricuits. A portion of the demodulated AF signals from the FM IF IC
(IC3, pin 9) are applied to the converter (IC303, pin 1) to
be adjusted its level. The level controlled signals are output
4-1-5 AF CIRCUITS from pin 2 and applied to the active filter (IC3, pins 7, 8;
The demodulated AF signals from the FM IF IC are ampli- R74, R75, R77 C137–C139). The filtered signals are applied
fied and filtered at AF circuit. This transceiver employs the to the filter amplifier section to amplify the noise components
base band IC for audio signal processing for both transmit only.
and receive. The base band IC is an audio processor and
composed of pre-amplifier, compressor, expander, scram- The amplified noise components are converted into the
bler, etc. in its package. pulse-type signal at the noise detector section, and output
from pin 13 as the “NOIS” signal and applied to the CPU
The AF signals from FM IF IC (IC3, pin 9) are applied to the (IC307, pin 37). Then the CPU outputs “AFON” signal from
base band IC (IC301, pin 23) via the digital/analog switch pin 18 according to the “NOIS” signal level to toggle the AF
(IC302, pins 12, 14). mute circuit (FRONT UNIT; IC205) and AF amplifier control-
ler (FRONT UNIT; Q202, Q203) ON/OFF.
The applied AF signals are amplified at the amplifier section
and level adjusted at the volume control section, and then • CTCSS AND DTCS
suppressed unwanted 3 kHz and higher audio signals at The tone squelch circuit detects tone signals and opens the
LPF section. The filtered AF signals are applied or bypassed squelch only when receiving a signal containing a matched
the TX/RX HPF, scrambler, de-emphasis, sections in sub audible tone (CTCSS or DTCS). When the tone squelch
sequence, then applied to another volume controller. is in use, and a signal with a mismatched or no sub audible
tone is received, the tone squelch circuit mutes the AF sig-
The TX/RX HPF filters out 250 Hz and lower audio signals, nals even when the noise squelch is open.
and the de-emphasis obtains –6 dB/oct of audio character-
istics. The expander expands the compressed audio signals A portion of the demodulated AF signals are passed through
and also noise reduction function is provided. the LPF (IC12, pins 12, 14) to filters CTCSS/DTCS signal.
The filtered signal is applied to the CPU (IC307, pin 46)
The AF signals are level adjusted at the volume controller after being amplified at the buffer amplifier (IC2, pins 1, 3).
and amplified at the amplifier section. The amplified AF sig-
nals are output from pin 20 and applied to the D/A coverter The CPU compares the applied signal and the set CTCSS/
(IC303, pin 16) to be adjusted its level, and then applied to DTCS, then output the AF mute switch (IC205) AF amplifier
the FRONT UNIT via J3 (pin 28). controller (Q202, Q203) control signal from pin 18.
TX/RX Scrambler/
HPF De-scrambler
RXIN 23 VR3 RX
De- 18
(HPF) LPF Expander VR4
emphasis
RXA1
SDEC 21 19
MTDT 10 20 SIGNAL
MSK
MTCK 9 Modulator
RXA2
MDIO 11
MSK MSK
MRDF 12 BPF Demodulator
Control
MSCK 13 Register
MDIR 14
4-2
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT The CTCSS/DTCS signals are generated by the CPU (IC307)
The microphone amplifier circuit amplifies the audio signals and output from pins 89–91 (“CENC0,” “CENC1,” ”CENC2”).
from microphone within +6 dB/oct pre-emphasis characteris- The CTCSS/DTCS signals are passed through 3 regis-
tic. The microphone signals are processed in the base band ters (R374–R376) to change its wave form. The wave form
IC which contains microphone amplifier, compressor, scram- changed CTCSS/DTCS signals are then passed through the
bler, limiter, splatter filter, etc. in its package. LPF (IC12, pins 8, 10) and applied to the converter (IC303,
pin 9) to be adjusted its level, and output from pin 10.
The audio signals from the microphone (FRONT UNIT;
MC201) are passed through the microphone mute switch The level adjusted CTCSS/DTCS signals are applied to
(FRONT UNIT; IC204). The switched signals are amplified at the AF mixer (IC12, pin 2) to be mixed with MIC signals.
the microphone amplifiers (FRONT UNIT; IC203, pins 1, 2, The mixed CTCSS/DTCS signals are output from pin 1 and
13, 14) to obtain within +6 dB/oct pre-emphasis characteris- applied to the D/A converter (IC303, pin 4) to be adjusted its
tics. The amplified signals are applied to the MAIN UNIT via level again, then output from pin 3. The CTCSS/DTCS sig-
J1 (pin 2). nals from the D/A converter are applied to the both of refer-
ence frequency oscillator (X1) and modulation circuit (D8) to
The amplified MIC signals from the FRONT UNIT are modulate the reference frequency signal and VCO oscillating
applied to the base band IC (IC301, pin 3). The applied signal.
MIC signals are amplified at the amplifier section, and level
adjusted at the volume control section. The level adjusted The modulated VCO output signal is amplified at the buffer
MIC signals are applied or bypassed the compressor sec- amplifiers (Q6, Q10) and is then applied to the YGR ampli-
tion, pre-emphasis section, TX/RX HPF, de-scrambler, lim- fier (Q11) via the TX/RX switch (D10).
iter, splatter, in sequence, then applied to another volume
controller.
4-2-3 TRANSMIT AMPLIFIERS
The compressor compresses the MIC signals to provide The VCO output signal is amplified to transmit output power
high S/N ratio for receive side, and the pre-emphasis obtains level by the transmit amplifiers .
+6 dB/oct audio characteristics. The TX/RX HPF filters out
250 Hz and lower audio signals, the limiter limits its level The buffer-amplified signal from the TX/RX switch is applied
and the splatter filters out 3 kHz and higher audio signals. to the YGR (Q11), the driver (Q12), and power (Q13)
amplifiers, to be amplified to the transmit output power level.
The filtered MIC signals are level adjusted at another vol- The power amplified transmit signal is passed through the
ume control section and amplified at the amplifier section, power detector (D11), antenna switch (D12), and two-stage
and then output from pin 7 via smoothing section (SMF). LPFs (L22, L23, C204–C207, C209), and then applied to the
antenna connector (CHASSIS UNIT; J1).
+ IC5
T2
ALC
– amp. D11
TMUT
4-3
4-3 PLL CIRCUITS A portion of the signal from the buffer amplifier (Q6) is fed
4-3-1 PLL CIRCUIT (MAIN UNIT) back to the PLL IC (IC1, pin 6) via the buffer amplifier (Q9)
The PLL circuit provides stable oscillation of the transmit and the BPF (Q1, D1, D2, L2, L56, L57, L302, C12, C15,
frequency and receive 1st LO frequency. The PLL circuit C20, C22, C25 to C28, C32) as the comparison signal.
compares the phase of the divided VCO frequency with the
reference frequency. The PLL output frequency is controlled
by the divided ratio (N-data) of the programmable divider.
4-4 POWER SUPPLY CIRCUITS
The PLL circuit contains the two RX VCOs (Q4, D4, D5,
D24, D26 for 154–174 MHz, Q20, D27–D30 for 136–
4-4-1 VOLTAGE LINES (MAIN UNIT)
153.995 MHz) and one TX VCO (Q5, D6, D7, D25). The LINE DESCRIPTION
oscillated signal is amplified at the buffer amplifiers (Q6, Q9) The voltage from the attached battery pack passed
and applied to the PLL IC (IC1, pin 6) after being passed VCC
through the power switch (Q309).
through the BPF (Q1, D1, D2, L2, L56, L57, L302, C12,
Common 5 V for the CPU (IC307) converted from the
C15, C20, C22, C25–C28, C32). CPU5V
VCC line at the CPU5V regulator (IC311).
Q1, D1 and D2 compose of a BPF switch which toggles the Common 5 V line converted from the VCC line at the
+5V
filtering frequencies for TX and RX, controlled by “T5C” sig- +5V regulator (Q307, Q308).
nal from the CPU (IC307 pin 16). 5 V for the transmit circuits regulated from the +5V line
by the T5V switch (Q305).
T5V
The applied signal is divided at the prescaler and program- The switch is controlled by the "T5C" signal from the
mable divider section by the N-data ratio from the CPU. CPU (IC307, pin 16).
The divided signal is detected at the phase detector sec- 5 V for the power save line regulated from the +5V line
tion via divided ratio adjustment section using the reference by the S5V switch (Q304).
S5V
frequency passed through the reference divider and output The switch is controlled by the "S5C" signal from the
from pin 4 after being passed through the charge pump sec- CPU (IC307, pin 27).
tion. The output signal is passed through the loop filter (R16, 5 V for the receive circuits regulated from the +5V line
R17, C17, C24, C29, C31) and is then applied to the VCO by the R5V switch (Q306).
circuits. R5V
The regulator is controlled by the "R5C" signal from
the CPU (IC307, pin 26).
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency. 4-4-2 VOLTAGE LINES (DSP UNIT)
LINE DESCRIPTION
4-3-2 VCO CIRCUITS 3.3 V for the CPU (IC12; DSP UNIT), DSP IC (IC7)
The VCO circuits contain separate two RX VCOs (Q4, D4, DVDD3.3V and EEPROM (IC17) regulated from the +5V line by
D5, D24, D26 for 154–174 MHz, Q20, D27–D30 for 136– the +3VC regulator (IC1).
153.995 MHz) and one TX VCO (Q5, D6, D7, D25). The 1.5 V for the DSP IC (IC7) converted from the +5V
CVDD1.5V
oscillated signal is amplified at the buffer amplifiers (Q6, line at the +1.5VA regulator (IC2).
Q10) and is then applied to the TX/RX switch (D9, D10). 3.3 V for the A/D converter (IC8) and LINER CODEC
Then the receive 1st LO (RX) signal is applied to the 1st +3VD
IC (IC9) from the +5V line at the +3VD regulator (IC3).
mixer (IC14, L30, L31, L33), and the transmit (TX) signal is
applied to the YGR amplifier (Q11).
• PLL CIRCUIT
4-4
4-5 DIGITAL CIRCUIT (IC-F70DT/DS only) The audio signals from the DSP UNIT are applied to the
• WHILE RECEIVING base band IC (MAIN UNIT; IC301, pin 20) after being
A portion of the 2nd IF sigal from the limiter amplifier section passed through the digital/analog switch (MAIN UNIT; IC302 ).
in the FM IF IC (IC3) is output from pin 11 and is applied to
the 2nd IF amplifier (Q303). The amplified 2nd IF signal is • WHILE TRANSMITTING
applied to the DSP UNIT via J2 (pin 11). The microphone signals from the base band IC (IC301, pin 7)
are applied to the DSP UNIT via J2 (pin 4).
The 2nd IF signal from the MAIN UNIT is passed through
the ceramic BPF (DSP UNIT; FI1) to suppress heterodyne The microphone signals from the MAIN UNIT are applied
noise, and amplified again at the digital IF amplifier (DSP to the LINER CODEC IC (DSP UNIT; IC9, pin 2) to convert
UNIT; IC5, pin 4). The amplified 2nd IF signal is applied to into the digital audio signal.
the A/D converter (DSP UNIT; IC8, pin 3) to be converted
into digital IF data, then applied to the DSP IC (DSP UNIT; The converted digital audio signal is processed by the DSP
IC7). The DSP IC converts the digital IF into the digital audio IC (DSP UNIT; IC7), and applied to the LINER CODEC IC
signal. (DSP UNIT; IC9) again. The signal from the LINER CODEC
IC (IC9, pin 15) is passed through the LPFs (DSP UNIT;
The digital audio signal from the DSP IC are converted into IC4, pins 3, 4, 5, 7) and applied to the MAIN UNIT via J1,
analog audio signals at the LINER CODEC IC (IC9) and out- and then passed through the microphone switch (MAIN
put from pin 16. The audio signals from the LINER CODEC UNIT; IC302, pins 3, 4), FM filter (R328, C335), FM/PM
IC are applied to the MAIN UNIT via J1 (pin 22). switch (IC302, pins 2, 15).
4-5
4-6-1 CPU (continued) Pin Port
Description
Pin Port number name
Description
number name CENC0–
89–91 Output the CTCSS/DTCS signals.
Input port for the noise signal from CENC2
37 NOIS
the FM IF IC (IC3, pin 13). Input port for [MONITOR] switch (MAIN
Input port for the [VOL] control (VR 92 SIDE3 UNIT; S4).
38 PWRSW UNIT; R1). Low: While [MONITOR] switch is pushed.
Low: While power is ON. Outputs the MSK data to the base
93 MTDT
Input port for the decodedDTMF sig- band IC (IC301, pin 10).
39 DDST nals from the DTMF decoder IC (IC300, Outputs serial data control signal to
pin 11). 94 MDIR
the base band IC (IC301, pin 14 ).
Inputs offering signal from the optional I/O port for the serial data signals
40 CIRQ unit and DSP unit. 95 MDIO from/to the base band IC (IC301,
Low: Offering signal is output. pin 11).
Outputs control signal for the power Outputs clock signal for the base
41 PWRO switch circuit (Q309, Q310). 96 MSCK
band IC (IC301, pin 13).
High: Power ON.
Outputs the the FM/PM switch (IC302,
43 SENC Outputs single tone encode signal. 97 PMFM pin 11) control signal.
44 BEEP Outputs beep audio signals. High:While PM is selected.
Input port for single tone decode sig- I/O port for data signals from/to the
98 ESDA
45 SDEC nal from the base band IC (IC301, EEPROM (IC308, pin 5).
pin 1). Outputs clock signal to the EEPROM
99 ESCL
Input port for CTCSS/DTCS signal (IC308, pin 6).
46 CDEC
from the LPF (IC12, pin 7). 100 CODE8 Output port for "CODE8" signal.
Input port for the PLL unlock signal.
47 ULCK
Low: The PLL circuit is unlocked.
Input port for the connected battery pack 4-6-2 D/A CONVERTER (MAIN UNIT; IC303)
48 BATV for the low battery voltage detection. Pin Port
Low: The battery voltage is low. Description
number name
49 LVIN Input port for the PLL lock voltage. Outputs AF signals to the squelch cir-
2 SQL
Input port for the "RSSI" signal from cuit (IC3, pin 8).
50 RSSI
the FM IF IC (IC3, pin 12). Outputs modulation signals to the
3 MOD
• Input port for the transceiver’s internal modulation circuit (D8).
temperature detecting signal. 10 TENC Outputs CTCSS/DTCS signals.
High: Internal temperature is high.
TEMP/ 11 BAL Outputs deviation balance control signal.
51 • Input port for the optional unit detecting
OPTV
signal. Outputs beep audio signals to the
High: While connecting optional unit 14 BEPV speaker via the AF amplifier (FRONT
to the multiconnector. UNIT; IC201).
Input port for [UP] switch (MAIN UNIT; S1). Outputs AF signals to the speaker via
55 SIDE1 15 SIGNAL
Low: While [UP] switch is pushed. the AF amplifiers (FRONT UNIT; IC201).
Outputs strobe signals to the D/A 22 TONE Outputs single tone signal.
68 DAST
converter (IC303, pin 6).
23 REF Outputs reference oscillator control signal.
I/O port for data signal to the D/A con-
69 DSDA
verter (IC310, pin 6).
Outputs "SPCON" signal. 4-6-3 D/A CONVERTER (MAIN UNIT; IC310)
72 SPCON
Low: Audio output. Pin Port
Description
Input port for transmitting MSK clock number name
78 MTCK signal from the base band IC (IC301, Outputs the bandpass filters (D18,
pin 9). 1 T1
D19) tuning signal.
Input port for key matrix. • While receiving:
79 KR Low: While any of key on the 10-keypad Outputs the bandpass filters (D15, D16)
(including [P0]–[P3]) is pushed. tuning signal.
I/O port for the serial data signal for 2 T2 • While transmitting:
80 FSDA Outputs the TX power control signal
the expander (FRONT UNIT; IC2).
which selects TX output power of HIGH
Outputs clock signal to the expander
81 FSCL or LOW. The output signal is applied to
(FRONT UNIT; IC2).
the ALC amplifier (IC5, pin 1).
Input port for [DOWN] switch (MAIN UNIT;
3 TXLVA Outputs TX VCO lock voltage.
88 SIDE2 S2).
Low: While [DOWN] switch is pushed. 4 RXLVA Outputs RX VCO lock voltage.
4-6
SECTION 5 ADJUSTMENT PROCEDURES
5-1 PREPARATION
When adjusting IC-F70DS/DT/S/D, the optional CS-F70/F1700 ADJ ADJUSTMENT SOFTWARE (Rev. 1.1 or later), OPC-966 JIG
CABLE(modified OPC-966 CLONING CABLE; see illustration page 5-2) are required.
▄ REQUIRED TEST EQUIPMENT
EQUIPMENT GRADE AND RANGE EQUIPMENT GRADE AND RANGE
Output voltage : 7.2 V DC Frequency range : 300–3000 Hz
DC power supply Audio generator
Current capacity : 3 A or more Measuring range : 1–500 mV
Frequency range : DC–300 MHz Power attenuation : 50 or 60 dB
FM deviation meter Attenuator
Measuring range : 0 to ±10 kHz Capacity : 10 W
Frequency range : 0.1–300 MHz : 0.1–300 MHz
Standard signal Frequency range
Frequency counter Frequency accuracy : ±1 ppm or better : 0.1 µV to 32 mV
generator (SSG) Output level
Sensitivity : 100 mV or better (–127 to –17 dBm)
Digital multimeter Input impedance : 10 MΩ/V DC or more AC millivoltmeter Measuring range : 10 mV to 10 V
5-1
• CONNECTION