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LABORATORY MANUAL OF IC- APPLICATIONS AND ECAD 3rd Year, I-Sem ECE
LAB INCHARGE

B.SATHEESH DEPARTMENT OF ELECTRONICS AND COMMUNCATION ENGINEERING

PART-A LINEAR IC APPLICATIONS LAB

S.NO. LIST OF EXPERIMENTS

1 2 3 4 5 6 7

OP AMP APPLICATIONS ADDER, SUBTRACTOR, COMPARATOR CIRCUITS ACTIVE FILTER APPLICATIONS LPF, HPF (FIRST ORDER) FUNCTION GENERATOR USING OP AMPS IC 555 TIMER MONOSTABLE OPERATION CIRCUITS, ASTABLE OPERATION CIRCUITS IC 566 VCO APPLICATIONS VOLTAGE REGULATOR USING IC 723 4 BIT DAC USING OP AMP

EXPERIMENTS 1 OP-AMP APPLICATIONS ADDER, SUBTRACTOR, &COMPARATOR CIRCUITS

AIM: To Design and study the OP-AMP Applications adder, sub tractor &comparator circuit using 741 IC. Op-Amp. APPARATUS REQUIRED: 1. IC 741 Op-Amps. 2. Resistors (1k-4, 2.2k-1, 3.3k -1) 3. Function generator 4. RPS(0-30v), 5. Fixed DC power supply (+/- 15v) 6. CRO with probes. 7. Breadboard. 8. Connecting wires. CIRCUIT DIAGRAM:

Fig (a). Adder circuit.

Fig(b). Subtractor circuit.

Fig(c). Comparator circuit. PROCEDURE:

Connections are made as shown in the fig. an Adder circuit. Give the three different (or) same DC voltages to inverting and measure Vo by DMM. DC supply is given at 7 and 4 pins of IC 741, +Vcc,-Vcc respectively. Repeat the above steps 2 for different resistors. Note down readings in the observation table 1 and compare the theoretical with practical value. Connections are made as shown in the fig. Subtractor circuit. Give the three different (or) same DC voltages to both inverting and non inverting Terminals and measure Vo by DMM. Repeat the above steps 6 for different resistors Note down readings in the observation table 2 and compare the theoretical with practical values. Give the connections as per the Non- inverting comparator circuit in fig C. Give the Vi A.C supply from function generator at 1Kz, 2 Vp-p to non inverting terminal +Vref (0.5v) DC supply to inverting terminal. Observe the output wave forms at +Vref on the CRO. Repeat the above step 12 same for -Vref (0.5v) DC supply, and trace the waveforms for both reference voltages.

OBSERVATION TABLE (1) At constant: V1=V2=V3=2V S No 1 2 R1 1k R2 1.k 2.2k R3 1k Rf 1K Rcom Vo (practical) Vo (Theoretical)

1k

3.3k

1K

OBSERVATION TABLE (2) At constant: V1=4v, V2=3v. S No 1 2 R1 1k R2 1.k 2.2k R3 1k Rf 1K Vo (practical) Vo (Theoretical)

3.3K

2.2k

1K

IDEAL UTPUT WAVE FORMS OF COMPARATOR:

RESULT:

VIVA VOCE QUISTIONS: 1. What are the Characteristics of an OP-Amp?

2. What are basic OP-Amp applications? 3. What is a summing amplifier? 4. How many modes are present in the OP-Amp? 5. What is the necessity of Rcom in the summer amplifier? 6. Which is a basic amplifier can be used as a sub tractor 7. What is the range of saturation voltage for an OP-Amp? 8. What is a slew rate? 9. What is a CMMR? 10. What is a SVVR? 11. What is the CMRR typical value of 741 IC? 12. What is an input offset voltage? 13. What is an input offset current? 14. What are the electrical parameters of OP-Amp? 15. What is comparator? 16. What is an out put of a comparator with any reference voltage? 17. What are the DC-characteristics? 18. What are the AC-characteristics? 19. What is a thermal drift? 20. What are the applications of comparators?

EXPERIMENT 2

ACTIVE FILTER APPLICATIONS LPF/HPF (FIRST ORDER)

AIM: 1. To design and study the circuit operation of active filter applications for LPF and HPF using Op-amp 741 IC. 2. Plot the frequency response for both LPF and HPF. EQUIPMENT: 1. 2. 3. 4. 5. 6. 7. 8. Resistors (10k -2),DRB IC 741 op-amp. Capacitor (0.01uF) Function generator DC power supply (+/- 15v) CRO with probes. Bread Board. Connecting wires.

CIRCUIT DIAGRAM: (a). I ORDER LPF:

Fig.a

DESIGN: -

1. Equate the given frequency to;

fh =

uF) and calculate value of R. 2. Pass band gain A0= 1+( Rf /Ri ), damping factor =1.414=3-A0 and for minimum DC offset Ri||Rf =2R from these Calculate Rf and Ri values Rf A0 ( dB ) = 20 log1 + Ri (b).I- ORDER HPF:

1 assume a value for C (0.1 2RC

Fig(b)

DESIGN: 1. Equate the given frequency to ,

fl = uF) and calculate value of R. 2. Pass band gain A0= 1+( Rf /Ri ), damping factor =1.414=3-A0 and for minimum DC offset Ri||Rf =2R from these calculate Rf and Ri values Rf A0 ( dB ) = 20 log1 + Ri 1 assume a value for C (0.1 2RC

PROCEDURE:

1. Connect the circuit as shown in fig A. 2. Give the input voltage Vi = 100mVpp at 1KHz form function generator and take the Vo by CRO at 6TH terminal of 741 IC. 3. Vary the input frequency from 10 Hz to 100 KHz in 1-2-5 sequence. 4. Measure the Vo at corresponding frequency, gain (AF) and also measure AF in dB. 5. Note down the readings in the observation table. 6. Plot the frequency response curve in semi log graph sheet from this compare Vo/Vi at lower 3dB with theoretical AF (i.e., f = fH). 7. Connect the circuit diagram as shown fig. B. 8. Repeat the same above steps from 2 to 6.

OBSERVATION TABLE:
INPUT FREQUENCY (Hz) LPF AF = AF(dB) = Vo/Vi 20 log Vo/Vi HPF AF = Vo/Vi

Vo

Vo

AF(dB) = 20 log Vo/Vi

MODEL GRAPH:
I-ORDER LPF:

I-ORDER HPF:

RESULT:

VIVA VOCE QUISTIONS:

1. Why the name given as an active filters? 2. What is the difference between passive filters and active filters? 3. Draw the frequency response curve of filters like (a) LPF (b) HPF (c) BPF (d) BSF. 4. Which order is having an improved filters response for a LPF? 5. Draw the third order active LPF? 6. If the order of the filter increases what about roll-off rate? 7. Write the transfer function of first order LPF? 8. Write the transfer function of second order LPF? 9. Write the transfer function of first order HPF? 10. Write the transfer function of second order HPF? 11. How many OP-Amps are required to design a state variable filter? 12. Which type filter technique gives maximally flat pass band? 13. What is an all pass filter?

EXPERIMENT 3 FUNCTION GENERATOR USING 741 IC

AIM: To design & study the circuit of triangular wave generator using Op-amp 741 IC. APPARATUS REQUIRED: 1. Resistors (15k, 47k), DRB 2. IC 741 op-amp - 2 Nos. 3. Capacitor (0.1uF) 4. DC power supply (+/- 15v) 5. CRO with probes. 6. Bread Board. 7. Connecting wires. CIRCUIT DIAGRAM:

DESIGN:

1. Peak to peak amplitude of output triangular wave is

vo ( pp) = 2 2. Frequency of output triangular wave (fo) is 1 R3 = T 4 R1C1 R2 R2 Vsat R3

fo =

PROCEDURE: 1. Connect the circuit as shown in figure. 2. Take the output wave form at 6TH terminal of IC 741 by CRO. 3. Switch on the power supply. 4. Observe the triangular wave from CRO. 5. Vary R vary the frequency of triangular wave and tabulate as per table. 6. Calculate the theoretical frequency (RC) which upon R1and Ct(RC=R1Ct) 7. Compare the theoretical value and practical values. OBSERVATION TABLE: S.NO R1 THEORETI CAL (T) PRACTICAL Vo (T) (+/Vsat) Vo=R2/R3(TH EORETICAL) *Vo Vo(PRAC TICAL)

IDEAL WAVE FORMS:

RESULTS:

VIVA VOCE QUISTIONS:

1. How many out put signals can be generated using function generator using OP-Amp? 2. What is the out put wave of 1st stage of function generator using OP-Amp? 3. How many OP-Amps are required to design a triangular wave generator? 4. The frequency of oscillation fo for a triangular wave generator using IC 741.? 5. The first stage of triangular wave generator is a comparator, how is it? 6. What is out put voltage of an inverting amplifier using IC 741 for an input sine wave signal 1 Vpp with Ri=1K ohm & Rf=200K ohm? 7. What is the circuit of the second stage triangular wave generator? 8. What are applications of function generator?

EXPERIMENT 4 MONOSTABLE CIRCUIT OPERATION -IC555 AIM: To design and Implement the monostable circuit using IC 555 Timer. APPARATUS REQUIRED:
1. Bread board 2. IC NE 555 3. CRO, with Probe 4. Fixed DC Supply (5v) 5. Resistors 6. Capacitors: 0.01F,0.1 F 7. Function Generator (1MHz) 8. Diode: 1N4007, Connecting wires etc.

CIRCUIT DIAGRAM:

DESIGN: - 1. Output pulse width T is given by T= 1.1 RC.

2. Trigger pulse must be a negative going input signal with an amplitude larger than Vcc/3 .

PROCEDURE:
1. Connect the circuits as shown in above using Component values obtained in the design. 2. Observe and sketch the output waveforms. 3. for pulse width modulation circuit apply the modulating input signal (square wave) and continuous trigger input signal and observe output pulse width modulating signal along with modulating signal and Sketch them. 4. Give the input square signal at 1k Hz Function Generator to the pin-2 of the IC 555 and take the output wave form at the pin-3 of IC 555. 5. Observe the capacitor voltage across the capacitor(c) 6. Measure the pulse width of out put wave form. 7. Calculate the theoretical pulse width by Pw=1.1RC. 8. Compare theoretical pulse value note down in Observation Table.

OBSERVATION TABLE: S.Nos 1. 2. Value of R Value of C Pw=1.1RC (Thoretical) Pw (Practical)

IDEAL OUTPUT WAVE FORMS:

RESULT:

VIVA VOCE QUISTIONS:

1. Draw the pin configuration of IC 555 Timer? 2. Why the name given as Timer for an IC 555? 3. What is the supply voltage range requirement of an IC 555? 4. What are the specifications of IC 555? 5. What are the Applifications of IC 555? 6. Draw the function block diagram of 555 timer ? 7. Explain the Operation of Monostable circuit using IC 555? 8. How many Comparators required in Monstable circuit? 9. What type of Triggering suppose to give Monostable Circuit/ 10. The pulse width of Monostable circuit is given by equivation? What are the applications of Monostable circuit using IC555?

ASTABLE CIRCUIT OPERATION USING IC 555 TIMERS AIM: To design and Implement an Astable circuit using IC 555 Timer. APPARATUS REQUIRED:
1. IC 555 Timer 2. Bread board 3. Fixed DC 5v supply 4. CRO, with Probe 5. Resistors 6. Capacitors 7. Diode 1N 4007 8. Conecting wires etc.

CIRCUIT DIAGRAM:

DESIGN: - Unsymmetrical square wave generator

1.For given frequency and Duty cycle greater than 50%: Tc = 0.69(RA+RB)Ct Td = 0.69(RB)Ct T = Tc+Td % Duty Cycle = (Tc/T)*100

2. For given frequency and Duty cycle less than 50%: Tc = 0.69(RA)Ct Td = 0.69(RB)Ct T = Tc+Td % Duty Cycle = (Tc/T)*100

PROCEDURE:
1. Connect the circuits as shown in above using component values obtained in the design. Assume Ct = 0.1F. 2. Take the output at the pin-3 of the IC555. 3. Also observe the output across Ct and Calculate the values of D<50%,D>50%,Ct and Cd. 4. Compare the Theoretical values and Practical values ,also note down in the Observation Table.

OBESRVATION TABLE: T (Theoreti (Practi cal) cal) Tc (Theoreti (Practi cal) cal) Td (Theoreti (Practi cal) cal) Duty cycle (Theoreti (Practi cal) cal)

IDEAL OUTPUT WAVE FORMS:

RESULT:

VIVA VOCE QUISTIONS:

1. Draw the block diagram of Astable circuit using IC 555? 2. How many stable stable states present in Astable Multivibrator ? 3. What is frequency of Oscillations fo is given by equivation in an Astable Multivibrator circuit? 4. Draw the Circuit diagram an Astable circuit using Ic555? 5. What is the necessity of SR-Flip flop in the Ic 555? 6. What is a Duty Cycle? 7. What is the necessity of Diode in an Astable Multivibrator? 8. To get Square wave output using IC555 timing What is condition require ?

9. How can be an Astable circuit designed using IC 741? 10. What is the necessity of Capacitor between Pin-1 and pin-5?

EXPERIMENT-5 IC566 VCO APPLICATIONS

AIM: - To design and implement the Monostable multivibrator using 566 IC and its applications
Pulse width modulation and Frequency divider

APPARATUS: 1.566 IC. 2. Bread board. 3. Fixed DC Power supply. 4. Resistors. 5. CRO with probe. 6. Capacitors. 7. Function generator and connecting wires etc.

CIRCUIT DIAGRAM: -

DESIGN:
1. Frequency of output waveform is given by 2( + V VC ) R1C1 ( + V )

fo =

Where

VC is control voltage and +V=12v is supply voltage 3 ( + V ) VC +V 2. Here 2K<R1<20K and 4 3. For a constant R1C1 Product the frequency fo can be Modulated over a 10:1 range by the control voltage VC. Here maximum output frequency is 1MHz

PROCEDURE:
1. Connect the circuit as shown in above diagram. 2. Apply the modulating input signal 3. Using voltage divider rule find control voltage Vc at terminal 5 i.e Vc= ( (R3 / (R3+ R2 )) (12) 4. Calculate frequency of output wave form fo 5. Observe the output triangular and square wave forms and sketch them.

IDEAL OUTPUT WAVE FORMS:

RESULTS:

VIVA VOCE QUESTIONS:

1. VCO stands for? 2. How many pins are present in the VCO pin configuration? 3. What is the necessity of Schmitt trigger in VCO? 4. What are output waveforms at pin-4 and pin-3 respective in VCO circuit? 5. Explain the operation of VCO circuit? 6. Explain the basic Principle of Voltage control oscillator circuit? 7. What is the equavation of free-running frequency for VCO circuit at Vc=0.85Vcc. 8. What are the Applications of VCO Circuit?

EXPERIMENT6 VOLTAGE REGULATOR USING IC723

AIM: To study the operation of 723 regulators IC and its application as current fold back circuit. APPARATUS REQUIRED:
1. 723IC, 2. Resistors, 3. Capacitor, 4. Potentiometer. 5. Power supply, 6. Ammeter and 7. Oscilloscope. 8. Breadboard and 9. Connecting wires etc.

CIRCUIT DIAGRAM:

PROCEDURE:
1. Connect the 723 regulator as shown in Figure. 2. Set the dc power supply voltage Vin to +10v.measure and record Vref with respect to ground. With load RL (10K pot) removed from the circuit (output open) measure the minimum and maximum output voltages by rotating the 1K pot through its full range. 3. Now adjust 1K pot so that Vo is +5V dc. Measure the voltage between the wiper arm of the 1K pot and ground. 4. Adjust the load RL until the load current IL=1Ma.record VL. repeat for different values of load currents;5mA,10maA,15mA and 18mAcalculate load regulation and compare with the manufacturers specifications. 5. Gradually increase the load current above 18mA .you will see that the load voltage suddenly decreases when load current is about 18 to 20mA.now the voltage across RSC is enough to begin current limiting. Measure and record a few values of load current and load voltage below and above the current limiting point. plot a graph of VL versus IL from the data obtained in steps 4 and 5. 6. Replace RL with a short circuit and measure the load current. this gives ISC. 7. Make RSC=0.With Vin=10V, measure and record IL and VL FOR IL: 5mA, 10mA, upto IL (max) where IL(max) is 5mA greater than the value of Isc measured in step6. CAUTION: do not short circuit the output of the regulator. it is better to connect a 100 ohm resistor in series with RL to avoid accidental short circuit. 8.with Rsc=0,adjust RL for a load current IL of 1mA,.to determine the line regulation, measure and record VL for Vin:10V,15V,up to 35V in 5V increments. Calculate percent line regulation.

OBSERVATION TABLE: S.Nos Ifl (m A)

Vfl(v)

%Reg=(VNL-Vfl)/VNL*100

MODEL GRAPH:

RESULT:

VIVA VOCE QUESTIONS:

1. What type of IC 723 Regulator? 2 Explain the basic Principle of Voltage regulator ? 3. What is the difference between the irregular and regulated? 4What are the specifications of IC 723? 5. What is a Load Regulation ? 6. What is a Line Regulation? 7. Draw the circuit diagram of Regulator using IC 723? 8. What is the need of Potentiometer in the IC 723 Voltage Regulator? 9. What is the load regulation range of IC 723? 10. What are the Applications of Regulator IC 723?

EXPERIMENT-7 4-BIT DAC USING OP-AMP AIM: To design and Implement the operation of 4-bit DAC with R-2R Ladder network using IC
741.

APPARATUS REQUIRED:
1. Bread board 2.741IC 3. Resistors 4. DC Supply(+/-15) 5. Digital Input Trainer Kit 6. DMM 7. Connecting wires etc.

CIRCUIT DIAGRAM:

PROCEDURE:
1. Connections are made as Shown in the Above diagram 2. Give the digital input from digital Trainer kit at Vref= 5v 3. Start the binary input from MSB at B3 to B0(i.e0001 to 1111) 4. Record the analog output Voltage by DMM at pin-6 of 741 at corresponding binary inputs. 5. Note down the reading in the Observation table. 6. Calculate the Theoretical Vo and compare the Practical with theoretical values. 7. Draw the graph between decimal equivalents of binary inputs verses output voltage

OBSERVATION TABLE: Decimal Equivalent of Binary input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input (Binary) B3B2B1B0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vo(Practical) Vo= -Vref(B3/2+B2/4+B1/8+B0/16 ) (Theoretical)

MODEL GRAPH:

RESULT:

VIVA VOCE QUESTION:

1. What is purpose of DAC? 2. What are the main Applifications A/D and D/A Converters? 3. How many types of D/A Converters? 4. What are major advantages of R-2R Ladder D/A Converters over weighted D/A converter? 5. Explain the operation of 4-bit DAC using Op-Amp? 6. What is purpose of R-2R ladder network in the 4-bit DAC using Op-Amp? 7. What is use of IC 741 Op-Amp in the 4-bit DAC Circuit ? 8. What are the Characteristics of ADC and DAC ? 9. Define Resolution? 10. Define Accuracy? 11. Define Linearity? 12. How many types A/D Converters?

PART-B ELECTRONIC COMPUTER AIDED DESIGN LAB

S.NO.

LIST OF EXPERIMENTS

1 2 3 4 5 6

D FLIP-FLOP DECADE COUNTER SHIFT REGISTERS 3-8 DECODER 4-BIT COMPARATOR 8 X 1 MULTIPLEXER

EXPERIMENT-1 D FLIPFLOP AIM: To design and Simulate D flipflop using VHDL. And verify using hardware APPARATUS: 1. Trainer kit. 2. Patch chords. 3. IC 7474. 4. XILINX 8.1 software.

ALGORITHM: 1. Define entity. 2. Specify I/O ports d, clk, pr_l, clr_l in input mode standard logic and q, qn in output mode standard logic. 3. End entity with name. 4. Define signals pr,clr and begin the description. Use process statement which include pr_l, pr_l, clr, pr, clk in sensitivity list. 5. The D flipflop has asynchronous active low preset and clear. When pr and clr both are high then outputs q and qn both are high. When only clr is high then q is low and qn is high. When only pr is high then q is high and qn is low. When pr and clr are low and rising edge of clock occurs then q follows d and qn follows not of d. Use if statements. 6. End all statements and end architecture as well as program.

PROGRAM: Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity dffis Port ( d: in std_logic; clk: in std_logic; pr_l : std_logic; clr_l: std_logic; q : out std_logic; qn : out std_logic); end dff; Architecture behavioral of dff is Signal pr,clr: std_logic; Begin Process (clr_l, clr,pr_l,clk) Begin Pr<=not pr_l;clr<=not clr_l; If(clr and pr)=1 then q<=1; qn<=1; Elsif clr=1 then q<=0; qn<=1; Elsif pr=1 thenq<=1; qn<=0; Elsif (clkevent and clk=1) then q<=d;qn<=not d; End if; End process; End behavioral;

SIMULATION RESULTS:

VIVA-VOCE: 1. Explain operation of D flipflops? 2. What are the types of flipflops? 3. What is a flipflop?

4. What are sequential circuits? 5. What are combinational circuits? 6. Give some examples for sequential circuits? 7. Name some of combinational circuits? 8. How many bits can be stored by a flipflop? 9. What are the merits of D flipflop? 10. What are the Demerits of flipflop? 11. What is ieee? 12. What do you mean by bit vector? 13. How many levels of clocks are there? 14. What are the features of IC 7474? 15. Applications of flipflop? 16. compare flip flop and a register?

EXPERIMENT-2 DECADE COUNTER AIM: To design and Simulate Decade counter using VHDL. And verify using hardware. APPARATUS: 1. Trainer kit. 2. Patch chords. 3. IC 7490. 4. XILINX 8.1 software. ALGORITHM: 1. Define entity. 2. Specify ports r, s in input mode 2 bit logic vector, clk in input mode standard logic q in output mode 4 bit logic vector. 3. End entity with name. 4. In architecture declare a signal q1 4 bit logic vector, initially 0000. Begin the architectural behavior of decade counter with asynchronous reset and select(s). When r is 11 and any of s(1), s(0) are low then reset q. When s is 11 then assign q has 1001. When each clock pulse occurs start incrementing q1, until q1 is 1001 then reset q1. Use if else statements. 5. End all statements, assign q1 to output q use <= operator and end architecture as well as program. PROGRAM: Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity decadecounter is Port ( clk: in std_logic; r :in std_logic_vector(1 downto 0); s :in std_logic_vector(1 downto 0); q : out std_logic_vector(3 downto 0); end decadecounter; Architecture behavioral of decadecounter is Signal q1: std_logic_vector(3 downto 0);=0000; Begin Process (r,s,clk) Begin If r=11 then If (s(1)and s(0)) =0 then Q<=0000; End if; Elsif s=11 then q<=1001; Elsif (clkevent and clk=1) then q1<=q1+1; end if; if q1=1001 then q1<=0000;

end if; q<=q1; end process; end behavioral;

SIMULATION RESULTS:

VIVA-VOCE: 1. Define a counter? 2. How many counts are possible by decade counter and Why? 3. What are the other counters?

4. Why to use STD_LOGIC vector? 5. What is the use of Process? 6. Why to use signal? 7. What are the other ICs? Which performs counting? 8. What are the applications of counter? 9. Design the same program to count 5 counts? 10. What is modulo n counter? 11. Design the same program in data flow model? 12. What is Jhonson counter? 13. What are the features of IC 7490? 14. Why to use VHDL? 15. Give syntax of WHILE statement? 16. Define RING counter? 17. What is the value of VCC for IC 7490? EXPERIMENT-3 SHIFT REGISTER AIM: To design and Simulate Shift Register using VHDL. And verify using hardware. APPARATUS: 1. Trainer kit. 1. Patch chords. 2. IC 7495. 3. XILINX 8.1 software. ALGORITHM: 1. Define entity. 2. Specify ports: mc, clkl, clkr in input mode standard logic vector, Ds, d0, d1 d2, d3, q0, q1, q2, q3 in buffer mode standard logic. 3. End entity with name. 4. In architecture, the behavior of shift register is as follows. When mc and clkl are high then there is no change in q.

When mc high and clkl is low then q follows d input and shifts to the right one bit. When mc, clkr attribute is low and ds is high then q is left shifted and MSB of q is assigned high. Otherwise q is left shifted and MSB of q is assigned low. When mc is low then there is no change in q. Use if else statements. 5. End all statements and end architecture as well as program. PROGRAM: Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity shifteregisters is Port ( mc :in std_logic; Clkl : in std_logic; Clkr : in std_logic; d : buffer std_logic_vector(3 downto 0); ds : buffer std_logic; q : buffer std_logic_vector(3 downto 0); end shiftregisters; Architecture behavioral of shiftregisters is Signal ct: std_logic_vector(3 downto 0); Begin Process (mc,clkl,clkr,d0,d1,d2,d3) Begin If (mc and clkl)=1 then q0<=q0;q1<=q1;q2<=q2;q3<=q3; elsif mc=1and clklevent and clkl=0and (d0=q1) and (d1=q2) and (d2=q3) and (d3=q3) then q0<=q1; q1<=q2; q2<=q3; q3<=q3; elsif mc=0and clkl=0and clkr=1then q0<=q0;q1<=q1;q2<=q2;q3<=q3; elsif mc=0and clkrevent and clkr=0 then if ds=1 then q0<=1; q2<=q1; q1<=q0; q3<=q2; else q0<=0; q1<=q0; q2<=q1; q3<=q2; end if; end if; end process; end behavioral;

SIMULATION RESULTS:

VIVA-VOCE:

1. Define a register? 2. How many bits can be stored by using a register? 3. What are the applications of registers? 4. How many bits are shifted by using 4 bit register? 5. What do you mean by left shift? 6. What do you mean by right shift? 7. Give specifications of IC 7495? 8. How many flip-flops are used in 8 bit shift register? 9. What do you mean by parallel shifting? 10. What do you mean by serial shifting? 11. Where we can use the parallel shifting? 12. Where we can use the serial shifting? 13. Why to assigned clock?

14. Can we design the same program by using WHILE statement? 15. Why do we get the undefined outputs? 16. What are the logics other than 0 and 1? EXPERIMENT-4 3-8 DECODER AIM: To design and Simulate 3-8 decoder using VHDL.and verify using hardware. APPARATUS: 1. Trainer kit. 2. Patch chords. 3. IC 74138. 4. XILINX 8.1 software. ALGORITHM: 1. Define entity. 2. Specify ports: a in input mode 3 bit vector and y in output mode 8 bit logic vector. 3. End entity with name. 4. In the architecture, define a signal for active low output and begin the operation using selected concurrent signal assignment statements, With a as 3 bit input lines, select output, using truth table. (Use case, when and others statements). 5. End all statements and end architecture as well as program. PROGRAM: Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity decoder is Port ( x : in std_logic_vector (2 down to 0); Z: in std_logic_vector(7 downto 0); end decoder; Architecture behavioral of decoder is Begin Process (x) Begin Case x is When 000=> z<=00000001; When 001=> z<=00000010; When 010=> z<=00000100; When 011=> z<=00001000; When 100=> z<=00010000; When 101=> z<=00100000; When 110=> z<=01000000; When 111=> z<=10000000;

When others n<= null; end case ; end process; end behavioral; SIMULATION RESULTS:

VIVA-VOCE: 1. Explain the operation of 3 to 8 decoder 2. What does a decoder decodes. 3. For a decoder to get 32 outputs how many inputs are required. 4. What do you mean by delay. 5. How to assign time delay. 6. What do you mean by driver. 7. Is decoder combinational circuit or sequential circuit. 8. What is the difference between a combinational circuit and sequential circuit? 9. Give the syntax for for loop 10. What do you mean by Finite state machine. 11. What do you mean by transition table. 12. Explain about generic statement. 13. What do you mean by test bench waveform. 14. Give the applications of decoder.

EXPERIMENT-5 4 BIT COMPARATOR AIM: To design and Simulate 4 bit comparator using VHDL.and verify using hardware. APPARATUS: 1. Trainer kit. 2. Patch chords. 3. IC 7485. 4. XILINX 8.1 software. ALGORITHM: 1. Define entity. 2. Specify ports a, b in input mode 4 bit logic vector EQ, NE, GT, LT, LE in output mode standard logic. 3. End entity with name. 4. In the architecture, begin the description of comparator in behavioural model for 4 bit unsigned integers, First reset all the outputs. Give conditions for inputs for comparison. Use if then statements. 5. End all statements and end architecture as well as program.

PROGRAM Library ieee; use ieee. Std_logic_1164 all; use ieee. Std_logic_ arith.all; use ieee. Std_logic_unsigned.all; entity com is port (a,b: in std_logic_vector (3 down to 0); aeqb, altb, agtb: out std-logic_vector); end comp; architecture behavioural of comp is begin aeqb <=1 when a=b else0; altb <=1 when a<b else0; agtb <=1 when a>b else0; end behavioural;

SIMULATION RESULTS:

VIVA-VOCE: 1. What do you mean by comparator? 2. Explain the functionality of a comparator . 3. Comparator is a sequential circuit or combinational circuit . 4. Give the applications of comparator.

5. The circuit for comparing two n-bit numbers has----------- entries in the truth table. 6. Basic gates used to construct a 4-bit comparator. 7. What are the features of combinational circuits? 8. What does a RESET signal indicates. 9. Combinational circuits require a clock or not. 10. Whether clock is necessary for comparator or not.

EXPERIMENT-6 8x1 MULTIPLEXER AIM: To design and simulate 8x1 multiplexer using VHDL APPARATUS: 1. Trainer kit 2. Patch cards 3. IC 74151 4. XILINX 8.1 software ALGORITHM: 1. Define entity 2. Specify ports a in input mode 8 bit logic vector, S in input mode 3 bit logic vector, f in output mode standard logic 3. End entity with name 4. In architecture, begin the behavioral description of multiplexer The three select lines s(2),s(1),s(0) select one of eight inputs and assign it to the output f Use selected concurrent signal assignment statement with when and others 5. End architecture as well as program. Program Library ieee; use ieee. Std_logic_1164 all; use ieee. Std_logic_ arith.all; use ieee. Std_logic_unsigned.all; entity mux is port( d: in std_logic_vector(7 down to 0); s: in std_logic_vector(2 down to 0); y: out_std_logic); end mux; architecture behavioral of mux is begin process(s ) begin case s is when 000=> y<=d0; when 001=> y<=d1; when 010=> y<=d2; when 011=> y<=d3; when 100=> y<=d4; when 101=> y<=d5; when 110=> y<=d6; when 111=> y<=d7; end case; end process; end behavioral; SIMULATION RESULTS: