An Ultra Sparse Matrix Converter

with a Novel Active Clamp Circuit

J. Schönberger, T. Friedli, S. D. Round, and J. W. Kolar

ETH Zurich, Power Electronic Systems Laboratory

Physikstrasse 3, CH-8092 Zürich, Switzerland

Abstract— The Ultra Sparse Matrix Converter (USMC) is

a AC-DC-AC converter that requires only 9 power switches
compared to the 18 switches required for a conventional matrix a A
converter. The simplified input switch configuration restricts this b B
c C
converter to unidirectional power flow applications in which the
maximum displacement angle between input and output voltages
and currents is ±π/6. A novel clamp circuit is therefore used to
protect the converter from overvoltages incurred under regen-
eration conditions. This paper presents the design of a 5.5 kVA (a) Unidirectional Ultra Sparse Matrix converter
USMC which uses space vector modulation in combination with a
zero current commutation scheme at the input rectifier stage. The
design of the system is detailed and the hardware implementation
of the converter is described. Experimental results demonstrate
the operation of the clamp circuit and show that the converter a A
draws sinusoidal currents from the input and supplies sinusoidal b u B
currents to the output with a conversion efficiency of up to 94%.
c C

Index Terms— Active clamp, matrix converter, reverse current,

ultra sparse.
(b) Bidirectional Sparse Matrix Converter
I. I NTRODUCTION
Fig. 1. Reduced switch indirect matrix converter topologies
The interest in matrix converters is increasing since they
can convert AC-AC without using large electrolytic storage
capacitors as conventional back to back converters do [1]. zero-current switching of the input stage. Since the output
Matrix converters consequently offer higher reliability and stage makes two transitions for each input cycle, it effectively
reduced size and weight since they are essentially an ’all- operates at twice the frequency of the input stage.
silicon’ converter [2]. A matrix converter that is of particular The main difference between the IMC and SMC is that
interest is the indirect matrix converter (IMC) since its two- the USMC only permits unidirectional power flow due to
stage structure affords simpler switch commutation require- the arrangement of the input switches. An additional clamp
ments and a simplified modulation strategy [3]. circuit is consequently employed to protect the converter from
From the IMC topology, a number of novel sparse converter experiencing excessive voltages under regeneration conditions.
topologies can be derived [3]. These topologies, the sparse, Clamp circuits for matrix converters have previously been
very sparse and ultra sparse matrix converter, are functionally- presented [4], [5]; however, the clamp circuit presented in
equivalent to the standard IMC converter but have a reduced this paper uses an active topology to achieve a greater degree
number of input switches. The ultrasparse matrix converter of controllability. The active clamp circuit is integrated with
(USMC), shown in Fig. 1(a), is the most simple form of the the auxiliary power supply capacitor since this configuration
IMC, comprising only 9 individual switches and 18 diodes. offers advantages such as the ability to achieve controlled ride-
The USMC itself is a variant of the sparse matrix converter through during power outages.
(SMC), shown in Fig. 1(b). Although the inability to sustain reverse power flow may be
The USMC and SMC operate by creating a dc link, u, viewed as a disadvantage, one niche field of application that
with the input stage and by using the output stage to provide can use this feature to its advantage is the aerospace industry,
inversion. The converter is switched using a modulation strat- as stringent regulations prohibit reverse power flow into an
egy which synchronizes the switching of the input and output aircraft’s power system. For this application, the USMC is
stages to reduce switching losses. The output switches are set typically required to convert a variable frequency ac input of
into a free-wheeling state during input transitions to allow 360 to 800 Hz into a variable frequency output for motor
loads. The reliability and compact size afforded by the matrix i

topology make it well-suited for this area of application. Sa Sb Sc

SA SB SC
In this paper, the design of a USMC is presented. The
a A
complete specifications for the USMC design are given in b u B
Table I. The converter has a thermal rating of up to 5.5 kVA c C
and operates at a switching frequency of 50 kHz to ensure
high-quality current waveforms are produced for aerospace-
type applications as the input and output frequencies increase.
This paper explains the operation of the USMC, describes the (a) State 1: u = uac , i = iA
hardware implementation of the converter and presents the
operating principles and design of the clamp circuit. Experi- i
mental results are included to demonstrate the performance of Sa Sb Sc
the converter with a resistive-inductive (RL) and permanent SA SB SC
a
magnet (PM) motor load. b u
A
B
c C
TABLE I
S YSTEM S PECIFICATIONS

Input voltage 3 x 230 Vrms, 50 Hz

(b) State 2: u = uac , i = −iC
Output voltage 3 x 0-199 Vrms, 0-200 Hz
Power rating 5.5 kVA
i
Input stage switching frequency 25 kHz
Sa Sb Sc
Output stage switching frequency 50 kHz SA SB SC
a A
b u B
c C
II. P RINCIPLE OF O PERATION
In a conventional matrix converter, a complex, multi-step
commutation strategy is employed to prevent short-circuits
between the input phases and open circuits in the output (c) State 3, 4: u switched from uac to uab , i = 0
phases [2]. However, with the USMC, a simpler zero dc link
current commutation scheme can be used since the converter i
is separated into input and output stages [3]. To commutate the Sa Sb Sc

input stage, the output inverter stage is set into freewheeling SA SB SC

a A
mode, allowing the input stage to commutate under zero b u B
current. Consequently the input stage does not incur switching c C
losses.
A. Modulation
A space vector modulation strategy which permits zero-
(d) State 5: u = uab , i = −iC
current commutation is employed to provide sinusoidal input
and output currents for the USMC [3]. The input phase with Fig. 2. Figure summarizing the operation of the modulation strategy and
the highest absolute value is clamped for a sector that is π/6 zero-current commutation during an output switching cycle
wide while the other two phases are switched. Switching of
the output stage is coordinated with the input stage to ensure
the output stage is in freewheeling mode when input stage is In state 1 input phase a is at its peak positive value and is
switched. clamped to the positive dc link rail by input switch Sa . Switch
This modulation strategy is summarized in Fig 2. The Sc is also turned on to conduct the return current. During this
operation of the converter is shown with the input stage and interval output leg SA has its high side switch active while
output stages both operating in sector 1, where input phase the other output switches have their low side switches active.
a has the most positive value for a π/6 interval and the In state 2, the input stage remains unchanged while the
output stage is formed by a combination of the (100) and output leg SB switches from low side to high side operation.
(110) vectors of the output stage. However, it should be noted In states 3 and 4, the zero current switching of the input stage
that under normal operation, the input and output sectors are occurs. Firstly output leg SC is switch to high-side operation
not necessarily synchronized. It is assumed that the output to create a freewheeling state at the output. The input stage
current remains constant during the switching cycle due to the then commutates from Sc to Sb under zero current.
inductive nature of the load. The converter then switches into state 5, which is similar to
state 2 except the dc link voltage is now uab and input switch The USMC power circuit is designed with a low inductance
Sb conducts the return current. In the final state, which is not layout to help minimize switching losses in the output stage.
shown, output leg B switches from high to low side operation A custom made bank of high-performance ceramic capacitors
such that the output stage is the same as shown in state 1. is situated in the center of the power PCB to supply the
The time intervals for the different switching states of ripple currents drawn by the input stage. All power switching
both input and output stages, τn , are calculated based on components are then placed directly around this bank to
space vector modulation to ensure sinusoidal input and output minimize the series parasitic inductance.
currents [3]. The EMC filter is designed to mitigate conducted electro-
magnetic emissions such that the converter meets the CISPR
B. Reverse Current Flow
11 specifications for Class A equipment. Optimized for size,
Reverse current flow occurs in the USMC when the output the filter consists of two common mode and differential stages.
current is more than 30◦ out of phase with the output voltage. The common mode stage provides an attenuation of -36 dB at
The conditions under which reverse current flow occurs are 150 kHz and the differential stage an attenuation of -94 dB.
described mathematically in [3] and are depicted in Fig. 3 for The power switches are based on IXYS IGBT modules.
a particular operating point. Each output phase leg is a FII50-12E module and each input
The desired output voltage vector, u∗2 , is formed by a switch and inner diode combination is an FII50-12BD module.
combination of the A and -C vectors, which correspond to Both input and output modules have an average current rating
bridge leg combinations of (100) and (110) respectively. The of 32 A at 90◦ C.
dc link current is thus a combination of iA and −iC as shown
The power board accommodates an auxiliary supply rated at
in Fig. 2. For the depicted operating conditions, reverse current
25 W to supply the voltages needed by the measurement and
flows during the time intervals that vector A is switched since
control circuits. The supply, based on the flyback topology,
the projection of i2 onto the A axis is negative. However,
provides the auxiliary voltages needed for the measurement
reverse current flow into the mains is prevented by the outer
and control circuitry. The flyback converter is integrated
diodes in each input stage leg. In order to avoid reverse
with the clamp to provide extra dissipation and ride through
current flow for all operating points, the output current phase
operation.
angle must therefore meet the condition −30◦ < Φ2 < 30◦ .
The control circuit is divided into a DSP board and measure-
However, it should be mentioned operating conditions exist
ment board as shown in Fig. 6. The DSP board contains an
where Φ2 can exceed ±30◦ without causing reverse current.
Analogue Devices ADSP-2199x DSP which implements the
For example, while u∗2 is aligned directly with vector (100),
main motor control loop. The signal interface board provides
Φ2 can be up to ±90◦ .
level shifting and signal conditioning for the measurement and
Due to this operating restriction, the USMC is not well-
control signals travelling between the DSP and power board,
suited for supplying induction motor loads since the output
allowing the DSP to measure bipolar values. In addition, it
current typically exceeds the ±30◦ limit in the steady state.
includes an FPGA to convert the vector times calculated by the
However, the USMC can be used for PM motors, where load
current typically stays within this limit under normal operation.
III. H ARDWARE I MPLEMENTATION
A schematic diagram of the USMC is shown in Fig. 4 and Gate drive
circuits
the hardware implementation of the final system is depicted Ceramic capacitor
bank
in Fig 5. The schematic shows the main system components
and in particular the connection of the clamp circuit. Auxiliary supply

B
-C
(110) Input EMI filter

i2 u2* Power semiconductors

Heat sink
F2
A
-A 60°
(100)

Fans

-B
C
Fig. 5. Implementation of USMC. DSP and measurement boards are not
shown. Dimensions are 76 x 120 x 260 mm and power density is 2.32 kW/dm3
Fig. 3. Example of conditions that cause reverse current flow (38 W/in3 )
 FII 50-12E

FII 50-12BD D1

+
External
a V R Resistor A
EMC Aux
b Filter Power B
C Supply
c C
-

D2 Clamp circuit
DSEP 60-12AR

Fig. 4. Ultra Sparse matrix converter schematic

DSP into physical interlocked gate drive signals. Both control Level Voltage/current
boards are stacked and plugged directly on top of the main Shifting Signals
V
power PCB. +
-
The losses are calculated according to the equations derived Vt Clamp
in [6] and [7] for the worst-case conditions of Φ2 = 0◦ and DAC
Switch
FPGA
M = 1, where Φ2 is the output current phase angle and Switch Gate
Input/Output
M the modulation index. The semiconductor loss parameters DSP Timing 9 Signals
Switches
for the IGBT bridge-leg modules (FII50-12E) are adopted
from [8], whereas the on-state parameters of the additional DSP board Measurement board Power board
rectifier stage diodes (IXYS DSEP 60-12AR) are extracted
from characteristics provided by the datasheet. Fig. 6. Block diagram of USMC control circuit

Table II summarizes the worst case rectifier and inverter

losses for an inverter switching frequency fS,Inv of 50 kHz, a
modulation index M12 of 1 and a junction temperature Tj = IV. C LAMP C IRCUIT D ESIGN
125◦ C. At the nominal operating point (U1 = 230 V, P2 = For dynamic regenerative loads such as motors, reverse
5.5 kW) the worst case efficiency ηW C is 94.3% neglecting current flow is unavoidable and a clamp circuit is needed to
auxiliary power supply losses and assuming 27 W of EMC protect the converter from experiencing overvoltages on the
filter losses. dc link. Clamp circuits have been proposed for bidirectional
matrix converters to prevent the switching devices from incur-
TABLE II
ring overvoltages and to permit ride-through under overvoltage
S EMICONDUCTOR L OSSES
conditions.
The clamp circuit typically used for conventional matrix
Rectifier stage Inverter stage Total semi-
fS,Inv Conduction Conduction Switching conductor converters connects the input and output lines via two B6 diode
losses losses losses losses bridges to a common capacitor which absorbs the voltage
50 kHz 92 W 39 W 157 W 288 W spikes [4]. This topology has been adapted to permit ride-
through for a conventional matrix converter during mains
failure. The motor is operated in a regenerative manner, such
The cooling system is designed to ensure the maximum that power flows back into the clamp capacitor, which is used
junction temperature of the semiconductors does not ex- to power the control circuits [10]. This topology has been
ceed 130◦ C. The cooling system, comprising three high- further extended to permit braking during mains failure by
performance SanAce 40/28 fans and a custom-designed connecting a resistive chopper across the clamp capacitor [11].
heatsink, was designed in accordance with principles presented The conventional clamp circuit can easily be applied to the
in [9]. The resultant thermal resistance of the heatsink is USMC by connecting a single B6 diode bridge to the output
0.07 K/W. lines as shown in Fig.7(a). Although this clamp circuit could
A simulation showing the thermal gradient of the heatsink be adapted to permit reverse power flow using the technique
was performed using ICEPAK to ascertain the maximum outlined in [11], other simpler clamp topologies permit this
surface temperature and to place the output leg modules to adaptation also.
prevent the occurrence of hotspots. For an ambient temperature Another clamp circuit that has been proposed for the 9-
of 45◦ C the simulation showed that the surface temperature switch ultra sparse matrix converter consists of a single ca-
under maximum power conditions did not exceed 89◦ C. The pacitor and diode connected across the dc bus [5]. This clamp
maximum junction temperature of the hottest devices, the circuit, shown in Fig.7(b), can only be used for overvoltage
output modules, was calculated to be 139◦ C. protection as it has no capability for dissipating significant
 DC link DC link DC link

Power A
Output B
Stage C R
C

C
C

(a) (b) (c)

Fig. 7. Clamp topology options. (a) Conventional clamp circuit (b) Capacitor-diode clamp with optional switch (c) Active clamp circuit

voltage rises caused by reverse current flow. An improvement V

Vt
to this circuit which involves connecting an optional switch
across the diode to allow the flow of stored energy back into Vnom
the system has been proposed [12]. td
Although this diode-capacitor clamp topology is incapable Clamp Switch

of sustaining reverse current flow, the active clamp circuit,

shown in Fig.7(c) can. This topology, chosen for the USMC, Fig. 8. Ideal time response of clamp circuit
allows the connection of a power resistor across the capacitor
to dissipate any reverse power. The actual implementation, i(t)

shown in Fig. 4, is integrated with the auxiliary supply +

C R
capacitor.
V(t)
The advantage of connecting the clamp circuit across the
auxiliary supply instead of directly across the dc link is -
twofold: the auxiliary supply bus voltage provides a more
stable voltage measurement than the dc link voltage. If Fig. 9. Equivalent clamp circuit when clamp is active
clamping were performed on the dc link it would fluctuate
significantly since it contains no storage. In addition the
steering diodes D1 and D2 can provide the converter with a If the clamp resistor is sufficiently large to dissipate the reverse
controlled ride-through or shut-down capability during power current, the clamp will operate in a variable frequency pulse
outages. During mains failure, the motor can be decelerated mode that is dependent on the instantaneous value of the dc
to provide sufficient power to the auxiliary supply, keeping bus. Otherwise it will remain on constantly for the duration
the controller active and thereby ensuring a controlled ride- of the reverse current flow.
through or shutdown of the system. The clamp resistor can be sized with the aid of an equivalent
A number of techniques for activating the clamp circuit are RC circuit, shown in Fig. 9. In the simplified circuit, the
possible. One technique is to operate the clamp in a PWM motor inductance and mechanical and resistive losses are
fashion when a reverse current is detected with the duty cycle neglected, as are the diode and effective auxiliary power
dependent on the magnitude of the reverse current. Another supply resistance, since these factors have little bearing on
technique is to operate the clamp based on the voltage level of the clamp resistor dimensions.
the dc bus. This technique was chosen for its robustness and The clamp resistor is sized to prevent the dc bus from rising
simpler implementation. The actual clamp activation circuit, above the clamp trip voltage threshold. The reverse current and
shown in Fig. 6, is based on a comparator that compares the dc bus voltage can be approximated by (1) and (2) respectively,
measured auxiliary bus voltage, V , to the clamp trip threshold,
Vt . The ideal response of the clamp circuit is shown in Fig. 8. J dω(t)
i(t) = − (1)
The DSP sets the trip threshold using a trim DAC to a level Kt dt
such that under normal operation, the nominal auxiliary bus
−t −t
voltage, Vnom , is below this value. The nominal bus voltage V (t) = V0 e RC + R(1 − e RC )i(t) (2)
is 560V, determined by the peak line to line voltage. When
V exceeds Vt due to an overcurrent the FPGA immediately where J is the motor inertia, Kt is the torque constant
activates the clamp switch and leaves it on for the duration of and dω/dt is the angular acceleration. The parameters for the
the overvoltage condition. When the overvoltage disappears, experimental system are C = 11µF, J = 40 × 10−4 kg.m2
the FPGA deactivates the switch after a small time delay of and Kt = 0.75 N m/A.
td to implement a form of hysteresis. The relationship between the dc bus voltage and the clamp
Using this clamp circuit, the operation of the clamp switch is resistance was determined under worst-case conditions using a
dependent on the reverse current and size of the clamp resistor. MATLAB simulation of the equivalent circuit. It was assumed
 q
800 40W
θi -30°
Constant S
700 Operation

30W
600

uP
500 θi +30°
S
Voltage (V)

20W Pulse
400 Operation uS* uS,l*
300
iSq
10W iS
200
θuS
100 θiS
0
0 0.5 1 1.5 2 2.5
Time (ms)

ΨP
Fig. 10. Relationship between clamp resistance and dc bus voltage rise for a d
reverse current flow of -20 A occurring at t = 0.5 ms. Initial voltage is 560V uSd* uSd,l* iSd
and clamp trip threshold is 600V.
Fig. 11. Modified output stage reference voltage method to avoid a negative
dc link current
that the motor was decelerated from 2000 rpm to 0 as fast
as possible by setting the reverse current limit in the torque
control loop to -20 A. Under these conditions, the time taken dependent on the filter constant and size of the step change.
to decelerate the motor is 56 ms. The results, depicted in In the final implementation of the USMC a time constant
Fig. 10, show the change in bus voltage under reverse current of 20 ms was used, the current limit was selected to be -10 A.
conditions. Initially, the bus voltage is 560 V due to the three The clamp threshold was set to 610 V and the external clamp
phase mains supply charging C. When the reverse current resistor was sized to be 60Ω with a 6 kW peak rating. A clamp
flows at t = 0.5 ms, the bus voltage rapidly increases to the resistor rated 200Ω, 2 kW peak was also mounted on board
clamp trip threshold of 600 V and the clamp activates. Fig. 10 for dissipating reverse currents of up to -3 A.
shows that the clamp resistance should be no greater than 30Ω Although a clamp resistor is necessary to provide a good
in order to prevent a rise above the clamp trip threshold. The dynamic response with regenerative loads, techniques for
required peak power rating for a 30Ω resistor is 12 kW. For minimizing or even eliminating use of the clamp are possible.
clamp resistances below 30Ω, the clamp must be operated in One simple technique which is well-suited for loads with
a PWM mode to prevent the clamp from dissipating mains low dynamic requirements such as fans is to reduce the rate
power when the bus voltage drops below 560 V. It should be of deceleration. This reduces the reverse current and in turn
also noted that for this step change in speed, the capacitance reduces the peak power rating for the clamp resistance.
has no influence over the final value of the voltage because Another technique which is presently being investigated is
the settling time of the clamp circuit, 3 · RC, is significantly to use a new modulation strategy to completely avoid negative
shorter than the time taken to implement the step change in current. Shown in Fig. 11, the proposed modulation strategy
speed. modifies the output voltage such that it remains within the
Although the power rating of the clamp resistor for this ±30◦ limit without affecting the torque-producing component
worst case operating condition is onerous, opportunities exist of the stator voltage. It is assumed that there is an angle of
for reducing the clamp resistor rating. It can be seen from θiS between the motor stator current iS and the motor back
(2) that the voltage rise is dependent on the magnitude of the EMF uP . To ensure the absence of negative dc link current,
reverse current, which in turn is dependent on the deceleration. the stator voltage must remain within the shaded area. In
One option is to limit the reverse current flow into the dc bus this example, the motor controller generates a reference stator
and another option is to limit dω/dt by filtering the speed voltage uS ∗ that is outside the shaded area. The new strategy
reference value. Using a first-order speed reference filter, the modifies the reference stator voltage so it is at the limit of the
rate of change in speed and voltage under reverse current shaded area and that the torque-producing component of the
conditions are stator voltage is unchanged. Therefore, uS ∗ is projected back
on to the q-axis and a new reference stator voltage uS,l ∗ is now
dω calculated such that it fulfils the ±30◦ criteria for no reverse
= −1/Ts (ω(t) − ω ∗ ) (3)
dt dc link current for all operating points of iS . As a result of this
restriction the d-axis reference voltage uSd,l ∗ is reduced and
−t RJ −t
V (t) = V0 e RC + (1 − e RC )(ω(t) − ω ∗ ) (4) only influences the magnetic flux in the motor. Although the
Kt T s example has shown this new method for a particular operating
where ω ∗ is the speed setpoint and Ts is the time constant point, the new method is applicable to the complete operating
of the filter. It can be seen that the rise in bus voltage is now region of the machine.
 95
u
94

93

92

91

Efficiency (%)
ia
0A 0V 90

89

88
iA
87
0A
86

85
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Power (kW)

(a) DC link voltage u, input current ia and output cur-

rent iA with a 2 kW RL load. (200 V, 10 A/division.) (a) Efficiency vs. input power

5
u

4.5

3.5

ia
0A 0V 3

THD (%)
2.5

iA 2

0A 1.5

0.5

(b) DC link voltage u, input current ia and output 0

current iA with a 2 kW PM motor load. (200 V,
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Power (kW)

10 A/division.)
(b) THD vs. input power

Fig. 13. Performance of USMC with an RL load

0 rpm

The modulation index was fixed at 0.8 to ensure consistency.

The results are portrayed in Fig. 13(a). It can be seen that the
0V
converter reaches its peak efficiency of 94.5% with an input
power of approximately 2.5 kW. The efficiency at full load
is 93%, which is 1.3% lower than the calculated value. This
0V difference can largely be attributed to the lower modulation
(c) Clamp circuit operation under regeneration condi- index used for the efficiency measurements.
tions. Graph shows motor speed (500 rpm/div), clamp The THD of the input current was measured up to the 50th
voltage (200V/div) and zoomed view of the clamp
voltage at initial activation.
harmonic and the results are shown in Fig. 13(b). It can be
seen that at low loads the THD is as high as 3.0%, but this can
Fig. 12. Experimental results be attributed due to the capacitive reactance of the EMI filter
slightly distorting the input current at low real power levels.
At full load, the THD decreases to approximately 1.0%.
V. E XPERIMENTAL R ESULTS The performance of the USMC was also evaluated with a 2
The performance of the USMC was evaluated with an kW PM motor load and the waveforms are shown in Fig. 12. It
RL and PM motor load. The dc link voltage and input and can be seen that the distortion in the input current has increased
output currents were measured with a LeCroy Waverunner slightly due to the non-ideal nature of the load.
LT548L oscilloscope and the results are shown in Fig. 12. The operation of the clamp circuit was tested by forcing the
It can be seen that the average value of the dc link voltage converter to operate under reverse power flow conditions. A
is approximately 560 V, and that its shape is typical of the motor load running at 800 rpm was connected then the speed
space vector modulation scheme used for the sparse matrix was reduced by 50% in order to achieve reverse current flow at
converter [3]. Efficiency and performance measurements were the output. The results, portrayed in Fig. 12(c) depict the actual
made, and the results are given in Fig. 13. motor speed and the voltage across the clamp switch. When
The efficiency of the converter was measured with an RL the auxiliary bus voltage reaches the clamp threshold of 610 V,
load of 20Ω, 10 mH and the onboard auxiliary supply inactive. the clamp switch becomes active, switching the 200Ω resistor
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