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SN74LVC1G79
SCES220U – APRIL 1999 – REVISED APRIL 2017

SN74LVC1G79 Single Positive-Edge-Triggered D-Type Flip-Flop

1 Features 3 Description
1• Available in the Texas Instruments The SN74LVC1G79 device is a single positive-edge-
NanoFree™ Package triggered D-type flip-flop that is designed for 1.65-V to
5.5-V VCC operation.
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output
• ESD Protection Exceeds JESD 22
on the positive-going edge of the clock pulse. Clock
– 2000-V Human-Body Model (A114-A) triggering occurs at a voltage level and is not directly
– 200-V Machine Model (A115-A) related to the rise time of the clock pulse. Following
– 1000-V Charged-Device Model (C101) the hold-time interval, data at the D input can be
changed without affecting the level at the output.
• Supports 5-V VCC Operation
NanoFree™ package technology is a major
• Inputs Accept Voltages to 5.5 V
breakthrough in IC packaging concepts, using the die
• Supports Down Translation to VCC as the package.
• Max tpd of 6 ns at 3.3 V and 50 pF load
This device is fully specified for partial-power-down
• Low Power Consumption, 10-µA Max ICC applications using Ioff. The Ioff circuitry disables the
• ±24-mA Output Drive at 3.3 V outputs when the device is powered down. This
• Ioff supports Partial-Power-Down Mode and Back- inhibits current backflow into the device which
prevents damage to the device.
Drive Protection
Device Information(1)
2 Applications PART NUMBER PACKAGE BODY SIZE
• Test and Measurement SN74LVC1G79DBV SOT-23 (5) 2.90 mm × 1.60 mm
• Enterprise Switching SN74LVC1G79DCK SC70 (5) 2.00 mm × 1.25 mm
• Telecom Infrastructure SN74LVC1G79DRL SOT (5) 1.60 mm × 1.20 mm
• Personal Electronics SN74LVC1G79YZP DSBGA (5) 1.14 mm × 0.91 mm
• White Goods (1) For all available packages, see the orderable addendum at
the end of the data sheet.

Logic Diagram (Positive Logic)

2 C
CLK C

C
4
TG Q

C C C

1
D TG TG TG

C C C
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8 Detailed Description ............................................ 11
2 Applications ........................................................... 1 8.1 Overview ................................................................. 11
3 Description ............................................................. 1 8.2 Functional Block Diagram ....................................... 11
4 Revision History..................................................... 2 8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 12
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Application and Implementation ........................ 13
9.1 Application Information............................................ 13
6.1 Absolute Maximum Ratings ...................................... 4
9.2 Typical Application ................................................. 13
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5 10 Power Supply Recommendations ..................... 14
6.4 Thermal Information .................................................. 5 11 Layout................................................................... 14
6.5 Electrical Characteristics........................................... 6 11.1 Layout Guidelines ................................................. 14
6.6 Timing Requirements: TA = –40°C to +85°C ............ 6 11.2 Layout Example .................................................... 14
6.7 Timing Requirements: TA = –40°C to +125°C .......... 6 12 Device and Documentation Support ................. 15
6.8 Switching Characteristics: CL = 15 pF, TA = –40°C to 12.1 Documentation Support ........................................ 15
+85°C ......................................................................... 7 12.2 Receiving Notification of Documentation Updates 15
6.9 Switching Characteristics: CL = 30 or 50 pF, TA = 12.3 Community Resources.......................................... 15
–40°C to +85°C.......................................................... 7 12.4 Trademarks ........................................................... 15
6.10 Switching Characteristics: CL = 30 pF or 50 pF, TA 12.5 Electrostatic Discharge Caution ............................ 15
= –40°C to +125°C..................................................... 7
12.6 Glossary ................................................................ 15
6.11 Operating Characteristics........................................ 7
13 Mechanical, Packaging, and Orderable
6.12 Typical Characteristics ............................................ 8
Information ........................................................... 15
7 Parameter Measurement Information .................. 9

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision T (December 2013) to Revision U Page

• Added Device Information table, ESD Ratings table, Thermal Information table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
• Changed thermal information to align with JEDEC standards. ............................................................................................. 5

Changes from Revision S (November 2007) to Revision T Page

• Updated document to new TI data sheet format. ................................................................................................................... 1

• Removed Ordering Information table. .................................................................................................................................... 1
• Updated Ioff in Features. ......................................................................................................................................................... 1
• Updated operating temperature range. .................................................................................................................................. 5
• Added ESD warning. ............................................................................................................................................................ 15

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5 Pin Configuration and Functions

DBV Package
5-Pin SOT-23 DRL Package
Top View 5-Pin SOT
Top View

D 1 5 VCC

CLK 2

GND 3 4 Q
YZP Package
5-Pin DSBGA
DCK Package Bottom View
5-Pin SC70 1 2
Top View
C GND Q
D 1 5 VCC

CLK 2 B CLK

GND 3 4 Q
A D VCC

See mechanical drawings for dimensions. Not to scale

Pin Functions
PIN
DBV, DCK, I/O DESCRIPTION
NAME YZP
DRL
D 1 A1 I Data input
CLK 2 B1 I Positive-Edge-Triggered Clock input
GND 3 C1 — Ground
Q 4 C2 O Non-inverted output
VCC 5 A2 — Positive Supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
(2)
VI Input voltage –0.5 6.5 V
VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage temperature –65 150 °C
TJ Junction temperature 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.

6.2 ESD Ratings

VALUE UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
Electrostatic
V(ESD) Charged device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 V
discharge
Machine Model (MM), A115-A 200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.

6.4 Thermal Information

SN74LVC1G79
THERMAL METRIC (1) DBV (SOT-23) DCK (SC70) DRL (SOT) YZP (DSBGA) UNIT
5 PINS 5 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 247.2 277.6 294.3 144.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 154.5 179.5 129.9 1.3 °C/W
RθJB Junction-to-board thermal resistance 86.8 75.9 143.4 39.9 °C/W
ψJT Junction-to-top characterization parameter 58.0 49.7 14.3 0.5 °C/W
Junction-to-board characterization
ψJB 86.4 75.1 144.0 39.7 °C/W
parameter

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = –40°C to +85°C TA = –40°C to +125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP (1) MAX MIN TYP (1) MAX
IOH = –100 µA 1.65 V to 5.5 V VCC – 0.1 VCC – 0.1
IOH = –4 mA 1.65 V 1.2 1.2
IOH = –8 mA 2.3 V 1.9 1.9
VOH V
IOH = –16 mA 2.4 2.4
3V
IOH = –24 mA 2.3 2.3
IOH = –32 mA 4.5 V 3.8 3.8
IOL = 100 µA 1.65 V to 5.5 V 0.1 0.1
IOL = 4 mA 1.65 V 0.45 0.45
IOL = 8 mA 2.3 V 0.3 0.3
VOL V
IOL = 16 mA 0.4 0.4
3V
IOL = 24 mA 0.55 0.55
IOL = 32 mA 4.5 V 0.55 0.55
II All inputs VI = 5.5 V or GND 0 to 5.5 V ±10 ±5 µA
Ioff VI or VO = 5.5 V 0 ±10 ±10 µA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 10 µA
One input at VCC – 0.6 V,
ΔICC 3 V to 5.5 V 500 500 µA
Other inputs at VCC or GND
Ci VI = VCC or GND 3.3 V 4 4 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

6.6 Timing Requirements: TA = –40°C to +85°C

over operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = –40°C to +85°C
VCC = 1.8 VCC = 2.5 VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 160 160 160 160 MHz
tw Pulse duration, CLK high or low 2.5 2.5 2.5 2.5 ns
Data high 2.2 1.4 1.3 1.2
tsu Setup time before CLK↑ ns
Data low 2.6 1.4 1.3 1.2
th Hold time, data after CLK↑ 0.3 0.4 1 0.5 ns

6.7 Timing Requirements: TA = –40°C to +125°C

over operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = –40°C to +125°C
VCC = 1.8 VCC = 2.5 VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 160 160 160 160 MHz
tw Pulse duration, CLK high or low 2.5 2.5 2.5 2.5 ns
Data high 2.2 1.4 1.3 1.2
tsu Setup time before CLK↑ ns
Data low 2.6 1.4 1.3 1.2
th Hold time, data after CLK↑ 0.3 0.4 1 0.5 ns

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6.8 Switching Characteristics: CL = 15 pF, TA = –40°C to +85°C

over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3)
TA = –40°C to +85°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 160 160 160 160 MHz
tpd CLK Q 2.5 9.1 1.2 6 1 4 0.8 3.8 ns

6.9 Switching Characteristics: CL = 30 or 50 pF, TA = –40°C to +85°C

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
TA = –40°C to +85°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 160 160 160 160 MHz
tpd CLK Q 3.9 9.9 2 7 1.7 5 1 4.5 ns

6.10 Switching Characteristics: CL = 30 pF or 50 pF, TA = –40°C to +125°C

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
TA = –40°C to +125°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 160 160 160 160 MHz
tpd CLK Q 3.9 12 2 8.5 1.7 6 1 5 ns

6.11 Operating Characteristics

TA = 25°C
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 26 26 27 30 pF

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6.12 Typical Characteristics

This plot shows the different ICC values for various voltages on the data input (D). Voltage sweep on the input is from 0 V to
6.5 V.

2 20
VCC = 1.8 V VCC = 3.3 V
1.8 VCC = 2.5 V 18 VCC = 5.0 V
1.6 16
Supply Current ICC [mA]

Supply Current ICC [mA]

1.4 14
1.2 12
1 10
0.8 8
0.6 6
0.4 4
0.2 2
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
Data (D) Input Voltage [V] ICCv
Data (D) Input Voltage [V] ICCv
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V

Figure 1. Supply Current (ICC) vs Data (D) Input Voltage Figure 2. Supply Current (ICC) vs Data (D) Input Voltage

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7 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC £2 ns VCC/2 2 × VCC 15 pF 1 MW 0.15 V
2.5 V ± 0.2 V VCC £2 ns VCC/2 2 × VCC 15 pF 1 MW 0.15 V
3.3 V ± 0.3 V 3V £2.5 ns 1.5 V 6V 15 pF 1 MW 0.3 V
5 V ± 0.5 V VCC £2.5 ns VCC/2 2 × VCC 15 pF 1 MW 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

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Parameter Measurement Information (continued)

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC £2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V
2.5 V ± 0.2 V VCC £2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V
3.3 V ± 0.3 V 3V £2.5 ns 1.5 V 6V 50 pF 500 W 0.3 V
5 V ± 0.5 V VCC £2.5 ns VCC/2 2 × VCC 50 pF 500 W 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 4. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview
The SN74LVC1G79 is a single positive-edge-triggered D-type flip-flop. Data at the input (D) is transferred to the
output (Q) on the positive-going edge of the clock pulse when the setup time requirement is met. Because the
clock triggering occurs at a voltage level, it is not directly related to the rise time of the clock pulse. This allows
for data at the input to be changed without affecting the level at the output, following the hold-time interval.

8.2 Functional Block Diagram

2 C
CLK C

C
4
TG Q

C C C

1
D TG TG TG

C C C
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Figure 5. Logic Diagram (Positive Logic)

8.3 Feature Description

8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must
be followed at all times.

8.3.2 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Recommended Operating Conditions, and the maximum input leakage current, given
in the Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive currents and oscillations. If tolerance to a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS
input.

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Feature Description (continued)

8.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.

CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.

VCC
Device

Input Logic Output

-IIK -IOK

GND

Figure 6. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.4 Partial Power Down (Ioff)

The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics.

8.3.5 Over-Voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Absolute Maximum Ratings.

8.4 Device Functional Modes

Table 1 lists the functional modes of SN74LVC1G79.

Table 1. Function Table

INPUTS OUTPUT
CLK D Y
↑ H H
↑ L L
L X Q0

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

A useful application for the SN74LVC1G79 is using it as a data latch with low-voltage data retention. This
application implements the use of a microcontroller GPIO pin to act as a clock to set the output state and a
second GPIO to provide the input data. If the SN74LVC1G79 is being powered from 1.8 V and there is concern
that a power glitch could exist as low as 1.5 V, the device will retain the state of the Q output. An example of this
data retention is shown in Figure 8 where the VCC drops to 1.5 V and the Q output maintains the HIGH output
state when VCC returns to 1.8 V. If the VCC voltage drops below 1.5 V, data retention is not guaranteed.

9.2 Typical Application

VCC > 1.65V for Operation

VCC > 1.50V for Data Retention

GPIO 1 D VCC 5
MCU SN74LVC1G79
2 CLK
CLK

3 GND Q 4

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Figure 7. Low Voltage Data Retention With SN74LVC1G79

9.2.1 Design Requirements

The SN74LVC1G79 device uses CMOS technology and has balanced output drive. Take care to avoid bus
contention because it can drive currents that would exceed maximum limits.

9.2.2 Detailed Design Procedure

1. Recommended input conditions:
– For rise time and fall time specifications, see Δt/Δv in Recommended Operating Conditions.
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
– Input voltages are recommended to not go below 0 V and not exceed 5.5 V for any VCC. See
Recommended Operating Conditions.
2. Recommended output conditions:
– Load currents should not exceed ±50 mA. See Absolute Maximum Ratings.
– Output voltages are recommended to not go below 0 V and not exceed the VCC voltage. See
Recommended Operating Conditions.

Copyright © 1999–2017, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: SN74LVC1G79
SN74LVC1G79
SCES220U – APRIL 1999 – REVISED APRIL 2017 www.ti.com

Typical Application (continued)

9.2.3 Application Curve

Positive Supply Voltage (VCC)

Non-inverted Output (Q)

Figure 8. Data Retention With VCC Glitch Down to 1.5 V

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating listed in
Recommended Operating Conditions. A 0.1-µF bypass capacitor is recommended to be connected from the VCC
terminal to GND to prevent power disturbance. To reject different frequencies of noise, use multiple bypass
capacitors in parallel. Capacitors with values of 0.1 µF and 1 µF are commonly used in parallel. The bypass
capacitor must be installed as close to the power terminal as possible for best results.

11 Layout

11.1 Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 9 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.

11.2 Layout Example

WORST BETTER BEST
2W

1W min.

Figure 9. Trace Example

14 Submit Documentation Feedback Copyright © 1999–2017, Texas Instruments Incorporated

Product Folder Links: SN74LVC1G79

 SN74LVC1G79
www.ti.com SCES220U – APRIL 1999 – REVISED APRIL 2017

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• Understanding and Interpreting Standard Logic Data Sheets, SZZA036
• Power-Up Behavior of Clocked Devices, SCHA005

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

Copyright © 1999–2017, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: SN74LVC1G79
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC1G79DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C795, C79F, C79J,
C79R)
SN74LVC1G79DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C795, C79F, C79J,
C79R)
SN74LVC1G79DBVTG4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C79F

SN74LVC1G79DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CR5, CRF, CRJ, CR
R)
SN74LVC1G79DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CR5

SN74LVC1G79DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CR5

SN74LVC1G79DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CR5, CRF, CRJ, CR
R)
SN74LVC1G79DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CR5

SN74LVC1G79DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 (CR7, CRR)

SN74LVC1G79YZPR ACTIVE DSBGA YZP 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 (CR7, CRN)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC1G79 :

• Automotive: SN74LVC1G79-Q1
• Enhanced Product: SN74LVC1G79-EP

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Sep-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G79DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G79DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74LVC1G79DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G79DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G79DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74LVC1G79DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G79DBVT SOT-23 DBV 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G79DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74LVC1G79DBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G79DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G79DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74LVC1G79DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G79DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G79DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G79DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G79DCKTG4 SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G79DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74LVC1G79YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Sep-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G79DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G79DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G79DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G79DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
SN74LVC1G79DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G79DBVT SOT-23 DBV 5 250 202.0 201.0 28.0
SN74LVC1G79DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G79DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G79DBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G79DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G79DCKR SC70 DCK 5 3000 202.0 201.0 28.0
SN74LVC1G79DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G79DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G79DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G79DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G79DCKTG4 SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G79DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0
SN74LVC1G79YZPR DSBGA YZP 5 3000 220.0 220.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/F 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/F 06/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/F 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DRL0005A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

1.7
1.5
PIN 1 A
ID AREA

1
5

2X 0.5
1.7
1.5
2X 1 NOTE 3

4
3

1.3 0.3 0.05

B 5X TYP
1.1 0.1 0.00

0.6 MAX
C

SEATING PLANE
0.18
5X 0.05 C
0.08
SYMM

SYMM

0.27
5X
0.15
0.1 C A B
0.4
5X 0.05
0.2
4220753/B 12/2020
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD-1

www.ti.com
 EXAMPLE BOARD LAYOUT
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67) SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX 0.05 MIN

AROUND AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDERMASK DETAILS

4220753/B 12/2020

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67)
SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4220753/B 12/2020

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
YZP0005 SCALE 8.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

C
0.5 MAX

SEATING PLANE
0.19
0.15 0.05 C
BALL TYP

0.5 TYP

SYMM
1
TYP
B D: Max = 1.418 mm, Min =1.358 mm
0.5
TYP E: Max = 0.918 mm, Min =0.858 mm
A

0.25
5X 1 2
0.21
0.015 C A B
SYMM

4219492/A 05/2017
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
YZP0005 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP
5X ( 0.23)
1 2

(0.5) TYP

SYMM
B

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23)

OPENING SOLDER MASK
OPENING

( 0.23)
METAL METAL UNDER
SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219492/A 05/2017

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com
 EXAMPLE STENCIL DESIGN
YZP0005 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP

5X ( 0.25)
(R0.05) TYP
1 2

(0.5)
TYP

B SYMM

METAL SYMM
TYP

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:40X

4219492/A 05/2017

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
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