Cost effective phase shifted pulse modulation soft

switching high frequency inverter for induction

heating applications
H. Kifune, Y. Hatanaka and M. Nakaoka

Abstract: A cost-effective high-efficiency high-frequency inverter with a PSM (phase-shifted pulse

modulation) scheme is proposed for medium power (5–30 kW) induction heating applications. This
inverter topology can achieve soft switching commutation in a wide range of power regulation,
without an auxiliary active resonant snubber circuit. The high-frequency PSM control scheme
presented can provide not only effective power regulation of the proposed inverter using IGBTs,
but also soft switching commutation. Theoretical equations for the soft switching operation region
are derived from the practical consideration of the gate pulse control strategy, in which the soft
switching operation is limited only by the duration of dead time. Through experimental
comparison of switching losses in the two-in-one IGBT power module, consideration is given to
how much the effect of soft switching can improve actual efficiency. In this discussion, the cost
effective high-efficiency inverter circuit topology is realised. The proposed inverter accomplishes
soft switching operation over a wide power regulation range. The actual power conversion
efficiency reached was 96.7%.

1 Introduction frequency power conversion converters with high efficiency

and performance have been developed. In addition, it has
The general characteristics of IH (induction heating) been found that switching loss can be reduced by
applications are high efficiency, rapid heating and high introducing soft switching techniques, enabling more
performance temperature control. Consequently, new compact, lighter power device cooling assemblies, and
electric heating applications using IH technology have been higher conversion efficiency [5].
studied, developed and used in consumer and business A number of high frequency soft switching inverters for
electroheat applications. In addition, it is expected that new IH applications have been proposed, and these can be
power applications using IH will be introduced, such as IH classified by the differences in inverter power, output
hot water producers, IH super-heated steam generators, IH frequency and power regulation method [6–9]. Inverters
roller drums for copy and print machines, and IH diesel developed for medium to high power applications often use
particulate filters for marine diesel main engines [1–4]. the PAM (pulse amplitude modulation) method [10].
In recent years, medium power range (5–30 kW) IH units However, the use of AC/DC active converters in the
have been introduced as the heat source for large cooking PAM scheme inevitably leads to higher cost. Inverters not
equipment in business use. High-frequency inverters using the PAM scheme, but with auxiliary resonant active
designed for large IH cooking equipment must be able to snubber circuits, are also not cost effective, as they require
regulate heating power from high temperature to low auxiliary circuit components.
temperature. When power of over 30 kW is required, two or Thus, in this paper, a cost effective high-efficiency high-
more high frequency inverters can be used in parallel. In frequency soft switching PSM (phase shift modulation)
such cases, irritating interference noise may arise if a PFM controlled full bridge inverter using IGBTs (insulated gate
(pulse frequency modulation) control scheme is adopted for bipolar transistors) is proposed for the large IH cooking
power regulation. To prevent this problem, the constant heater. It can regulate inverter power by itself and realise
frequency power regulation scheme should be introduced. soft switching with high-efficiency operation. The left-hand
With large advances of MOS gate controlled power side bridge leg of this inverter operates in the lagging current
semiconductor devices such as MOSFETs, IGBTs, and mode, and the righthand side bridge leg operates in the
CSTBTs, which are designed for high-frequency power leading current mode. This high-frequency inverter topol-
switch control and low power loss, a variety of high- ogy can maintain soft switching operation in a wide range
of power regulation activities, without an auxiliary resonant
active snubber circuit.
r IEE, 2003
IEE Proceedings online no. 20040085
2 Phase-shift modulation controlled inverter
doi:10.1049/ip-epa:20040085
Paper first received 19th March 2003 and in revised form 11th September 2003 2.1 Inverter topology
H. Kifune and Y. Hatanaka are with the Power System Engineering Chair, In general, the series load resonant high-frequency full-
Tokyo University of Marine Science and Technology, 2-1-6 Etchujima,
Koto-ku, Tokyo 135-8533, Japan bridge inverter is used as a high-frequency power supply
M. Nakaoka is with the Department of Electrical and Electronic Engineering, for IH applications in medium to high power ranges. The
Yamaguchi University, 2-16-1 Tokiwadai, Ube, Yamaguchi 755-8611, Japan operational frequency of the voltage source series resonant

IEE Proc.-Electr. Power Appl., Vol. 151, No. 1, January 2004 19

high frequency inverter is tuned a little higher or lower than vG1 Td Td
the load resonant frequency fr, in order to achieve soft
switching operation [10]. When fo4fr, for example, the
resonant current is forced to lag with respect to the inverter vG2
output voltage, realising ZVZCS (zero voltage zero current

vG3
switching) turn-on.

Td
However, the high-frequency inverter proposed here can vG4
achieve soft switching operation when fo ¼ fr by adopting a
PSM scheme (see Fig. 1). Figure 2 illustrates from top to
bottom, the waveforms of the gate pulse trains, the voltage v1
and the current of switches and the inverter output voltage
i1
and current in the steady state. The gate pulse vG4 of S4 has
a certain lag with respect to the gate pulse vG1, which delays
the turn-on timing of S4 with respect to S1. As a result, S1 i2
and S4 share the peak of the load current but cover different
zero crossing points of the load current. Hence, S1 (S2) v2
operates in current lagging mode and realises ZVZCS turn-
on. In a similar way, S3 (S4) can operate in the current
leading mode and turns off with ZVZCS. Furthermore, as i3
will be considered later, the lossless snubber capacitor Csn v3
provides voltage soft commutation of S1 and S2, realising
ZVS turn-off in these switches.
v4

iin i3 i4

S1 D1 S3 D3
v1 vab

Lload Rload Cr io
i1
Ed A B

io
S2 D2 S4 D4 mode 1 2 3 4 5 6 7 8
v2 Csn
Fig. 2 Operational waveforms of PSM converter
i4
i2

Fig. 1 Proposed PSM high-frequency inverter given between the gate pulses of the diagonal switches, as
shown in Fig. 2. The phase difference was set to 701 because
the switching losses are maximum when the instantaneous
2.2 Switching power losses analysis value of the current at switching becomes maximum when
To achieve high-efficiency operation of a high-frequency the pulse phase difference f ¼ 50–901. In this condition, the
inverter, the turn-off operation of S1 and S2 and the turn- instantaneous value of current at turn-off operation was 50
on operation of S3 and S4 need to be improved to achieve A and the inverter output power was 6.5 kW.
soft switching. It is well known that ZVS operation due As shown in Fig. 3, the turn-off loss per device is larger
to voltage soft commutation can be realised by adding a (62.4 W) than the total of the turn-on loss and the recovery
lossless snubber capacitor Csn in parallel with an active loss (28.0 W). This indicates that the tail current of the
power switch operating at current lagging mode [7, 8]. IGBT increases the turn-off loss. In addition, the current
Similarly, ZCS operation due to current soft commutation value at turn-off operation is larger than the current at turn-
can be achieved by connecting a lossless inductor snubber on operation in the PSM controlled inverter.
Lsn in series with an active power switch operating in the Because the total switching loss in S1 and S2 is 124.8 W
current leading mode. when the inverter output is 6.5 kW, it is expected that
However, adding these components for soft switching efficiency can be improved by 1.93% or less by reducing the
to the inverter increases the cost, although it reduces the turn-off losses of S1 and S2. However, the switching losses
switching losses and improves the conversion efficiency. In including the diode recovery loss in S3 and S4 is only 56.1
addition, these power components cause conduction loss, W, and efficiency improves by only 0.86% even if these
dielectric power loss and core loss. Therefore, it is necessary power losses become zero. Therefore it is reasonable to
to assess the effectiveness of soft switching. Figure 3 neglect these power losses from a practical standpoint. In
indicates the measurement values of the switching power consequence, a high-frequency inverter can realise cost
losses in the proposed PSM high-frequency inverter without effectiveness and high efficiency by improving the turn-off
Csn. Experimental conditions are: fo ¼ 23.4 kHz, Ed ¼ 270 V, of S1 and S2 to ZVS with lossless snubber capacitor Csn.
Csn ¼ 0 mF, Lload ¼ 46.5 mH, Cr ¼ 1 mF and Rload ¼ 4.5 O. A
fourth generation trench gate IGBT (CM100DU-12F) was 2.3 Lossless snubber capacitor
used as the active power switch, and it was driven under the According to Kirchhoff’s voltage law, the switch voltages v1
following conditions: the gate pulse voltage was +15 V/ and v2 across S1 and S2 are given by:
4 V and the gate resistance was 27 O. The experiment was
implemented at f ¼ 701, where f is the phase difference Ed ¼ v1 þ v2 ð1Þ

20 IEE Proc.-Electr. Power Appl., Vol. 151, No. 1, January 2004

 70
Csn output
60 terminal-A
power loss per one device, W v1 output
i1 GND E1C2 terminal-B
50
E2
40 E3C4
Ed C1
30
E4
20
200 V/div
10 50 A/div C3

0
turn-off loss cooling
a
fin
70

v4 two-in-one IGBT module

60 cooling
power loss per one device, W

C: collector terminal
fan
i4 E: emitter terminal
50

40 Fig. 4 Photo of experimental circuit

30
3 Proposed inverter characteristics
20

10 200 V/div
3.1 Switching operation modes
50 A/div Figure 5 illustrates the equivalent circuits of the proposed
0 inverter for each operation mode. It is assumed that all the
turn-on loss
b circuit components and power devices are ideal.
Mode 1: S1 and S4 are in the on state, and the power is
70
supplied to the load from the voltage source Ed.
v4 Mode 2: Turning off S1, Csn starts to discharge, and v2 is
power loss per one device, W

60
i4 changed from Ed to zero gradually. At the same time, v1
50 rises from zero to Ed gradually; S1 accordingly achieves
40 ZVS turn-off.
30

20
iin
10 200 V/div i1 i1 i3
50 A/div S1 D3
v3 S1
0 Lload R i0 Lload R i0
recovery loss Ed load Cr load Cr
c
S4
Fig. 3 Comparison of switching losses v2 vC v2 vC v4
sn sn
a Turn-off loss i4
b Turn-on loss mode 1 mode 8
c Recovery loss
IGBT type: CM100DU-12F i3
i1
D1 S3
v1 v3 i0
Lload Rloadi0 C Lload R
r load Cr

Csn S4
where Ed is a inverter input voltage, which is supplied by a v2 vC v2 vC v4
sn sn
i4
circuit including a rectifier, a chemical capacitor and a film
capacitor. It is therefore a continuous value. When S1 and mode 2 mode 7
iin
S2 operate in the current lagging mode, with Csn connected
i3
to S1 and S2, these can achieve ZVS operation because v1 S3
and v2 maintain the continuity. From (1) it can be seen that, v1 v3 v1 i
Lload R i0 Lload Rload 0 C
load Cr Ed
if either v1 or v2 becomes a continuous value, the other is r

also continuous. Hence, Csn only has to be connected in D2 S4 Csn

v2 vC v4
parallel with either S1 or S2. Considering the use of a two- i2
sn
i4
in-one package IGBT module for switching bridges, the
mode 3 mode 6
distance between the collector terminal and the emitter iin
terminal of S2 is slightly shorter than the same distance in i3
S1. Consequently, connecting Csn to S2 is advantageous: as S3
v1 v3 v1
the short lead of Csn decreases, the stray switch–Csn loop Lload Rloadi0 Lload Rloadi0 C
Cr Ed r
becomes small. Therefore, as shown in Fig. 1, we can obtain
a high-frequency full bridge inverter when Csn is added in S2 D4 S2
v4
parallel only with S2. Figure 4 is a photograph of the i2 i4 i2
compact experimental circuit. Two IGBT modules are
mode 4 mode 5
mounted on a cooling fin, and a cooling fan is installed
below them. Fig. 5 Equivalent circuits in each switching operation mode

IEE Proc.-Electr. Power Appl., Vol. 151, No. 1, January 2004 21

 Mode 3: The voltage of S2 is zero, the anti-parallel diode T/2
D2 starts current flow. In this mode, the gate pulse voltage
is input to S2.
on
Mode 4: Due to series load resonance, the load current vG1−vG4
flows in the reverse direction, and the current flows in the
loop of S2-D4-CrRloadLload. In this mode, S2 completes S1−S4
a
=0
ZVZCS turn-on and S4 completes ZVZCS turn-off. Td = 0
Mode 5: Turning on S3, the power is supplied to the load
from the voltage source Ed through S2 and S3. The inverter device current
without dead time
output power is controlled by the duration of this mode.
Mode 6: Turning off S2, Csn starts to be charged to Ed
Td /2 Td /2
from zero voltage, which enables S2 to achieve ZVS
turn-off.
on
Mode 7: The anti-parallel diode D1 becomes on-state vG1−vG4
when the charging of Csn is finished. The load current flows
in the loop D1-S3-Cr-Rload Lload. In this mode, the gate b S1−S4
pulse voltage is input to S1.
=0
Td > 0
Mode 8: Due to series resonance, the load current flows
again in the reverse direction, which brings ZVZCS turn-on device current
to S1. In addition, S3 can realise ZVZCS turn-off during
this mode. After this mode, the inverter switching operation
comes again to mode 1 by turning on S4.
Inverter operation should start from mode 6 under soft Td
switching. Before the inverter starts, there are three possible on
situations: 1 Csn has been charged to input voltage Ed vG1, vG2
before inverter start; 2 Csn is charged less than Ed; and 3 Csn S1, S2
is quite not charged. If the current flows to Csn through S3, c
=
min
Cr, Rload and Lload, the inverter’s operation becomes steady Td > 0
state straight away, as the current charges Csn gradually. If device current
Csn has already been charged to Ed before the inverter in lagging leg
starts, the current does not flow until mode 1. Then
the current flowing through S1 and S4 starts from zero in
mode 1. As a result, the charge or discharge current of Csn
does not affect the inverter’s operation. Td

3.2 Soft switching region on

vG3, vG4
The phase difference provides the soft switching operation
and the capability of power regulation for the proposed S3, S4
inverter. In this Section, the relation between the phase
=
min
d
difference f and the soft switching operation region is Td > 0
discussed. device current
Figure 6a shows the current waveforms flowing through in leading leg
each active switch when f ¼ 0 and the dead time Td ¼ 0.
Both turn-on and turn-off realise ZCS operation. However,
from a practical standpoint, the dead time is essential in the
Fig. 6 ZVZCS operation by PSM scheme
operation of a voltage source inverter to prevent a short
circuit. When a positive value of dead time Td is given to the
gate pulses, the power switches cannot achieve soft switch- complete either charging or discharging during the dead
ing operation in both turn-on and turn-off, as indicated in time when f ¼ fmax. Consequently, the largest limitation of
Fig. 6b. Then, if the gate pulses of S1 and S2 are shifted phase difference fmax can be expressed as:
with Td/2 leading, S1 and S2 operate in the current lagging fmax ¼ 180ð1  2fo Td Þ ð3Þ
mode, which brings ZVZCS turn-on of these switches (see
Fig. 6c). In addition, shifting the gate pulses of S3 and S4 by When f ¼ fmax, the inverter power becomes minimum
a lag of Td/2, S3 and S4 operate in the current leading under soft switching conditions.
mode, which brings ZVZCS turn-off to these switches (see As mentioned above, the soft switching region where
Fig. 6d). As a result, soft switching operation of all active both S1 and S2 achieve ZVZCS operation and both S3 and
switches is realised when a phase difference of Td or more is S4 achieve ZVZCS operation is defined as:
set between the gate pulses of switches in the left and right 360fo Td ofo180ð1  2fo Td Þ ð4Þ
bridges. Therefore the smallest limitation of phase difference
fmin under soft switching condition can be expressed as: From (4) it can be seen that the proposed inverter can
obtain a wide soft switching region within the power
fmin ¼ 360 fo Td ð2Þ regulation range. Note especially that the soft switching
When f ¼ fmin, the maximum inverter power is obtained operation region is limited only by the dead time.
under soft switching conditions.
When the gate pulses of the diagonal switches have no 3.3 Inverter output power
time overlap (fmax), the inverter power becomes almost Figure 7 shows the gate pulse trains and inverter output
zero. At the same time, the soft switching commutation of voltage vab. The inverter output power increases a little by
S1 and S2 is met with this condition, because Csn cannot connecting Csn, and the resonant frequency becomes slightly
22 IEE Proc.-Electr. Power Appl., Vol. 151, No. 1, January 2004
 trigger time: 03/02/04 14:39:56 number of data: 1002
vG1
t, s
Td Td
100 V/div
vG2 20 A/div
t, s
switching loss


vG3
t, s
62.3 W


vG4
t, s
d p d p
Ed current voltage
vab x, rad
−Ed

 2 (d +d)/2
0

Fig. 7 Gate pulses and inverter output voltage

higher. In this Figure, however, the waveform vab does not

reflect the influence of Csn, because the value of Csn is
designed to be somewhat smaller than that of resonant
capacitor Cr, and the increase of power is around 3%. a
200 ns/div
Moreover, the analysis would be too complicated, since the
trigger time: 03/02/05 20:28:31 number of data: 1002
current flowing through Csn is for a limited time in a cycle.
In most cases, only the fundamental wave of vab
contributes to the output power, and the harmonic waves 100 V/div
above the operation frequency can be neglected. Thus the 20 A/div

inverter output power Po can be expressed as: switching loss

Po ¼ Vi Ii cos y ð5Þ 14.0 W

where Vi, Ii, and cos y are the fundamental wave of vab, the
fundamental wave of the load current and the power factor
of the inverter, respectively. Because the proposed inverter voltage
operates at resonant frequency, we obtain: current

Vi2
Po ¼ ð6Þ
Rload
Vi is given by the Fourier transformation of vab:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
8Ed2 yp þ yd
Vi ¼ cos2 ð7Þ
p2 2
where yp (rad) is the gate pulse phase difference, and yd (rad)
is the dead time. yp and yd are expressed, using f (deg), fo
(Hz) and Td (s) as follows: b
200 ns/div

pf
yp ¼ ; yd ¼ 2pfo Td ð8Þ Fig. 8 Effect of Csn in turn-off operation
180 a Without Csn
Substituting Vi in (6) with the right-hand side of (7), we b With Csn ( ¼ 0.1 mF)
obtain:
8Ed2 yp þ yd The measured turn-off time of IGBT is 200 ns without
Po ¼ 2
cos2 ð9Þ Csn, as shown in Fig. 8a. The experimental conditions are
p Rload 2
the same as for Fig. 3. Because the switching loss is roughly
As already mentioned, soft switching operation of the proportional to dv/dt, the turn-off loss can be reduced to 1/4
inverter is limited by the dead time. Hence, (7) and (9) hold if dv/dt become 1/4. Hence, to make dv/dt equal to 1/4, to
under the following condition: obtain 800 ns voltage commutation time, Csn must provide
yd  yp  p  yd ð10Þ the voltage soft commutation time (tcom) of 600 ns
( ¼ 800200 ns). As mentioned above and as shown in
Fig. 8a, the instantaneous current value (Ioff) at turn-off
operation is about 50 A, and the inverter input voltage Ed is
4 Experimental results and discussion 270 V. Therefore, the value Csn is given by:
4.1 Design of capacitors Ed
This inverter operates at the resonant frequency of the series Csn ¼Ioff
tcom ð12Þ
load resonant circuit; the series resonant capacitance Cr is
given by: Csn ffi0:11 mF

1 In practice, Csn was set to 0.1 mF in the experiment. As a

Cr ¼ ð11Þ result, the turn-off loss per switch was reduced from 62.3 W
ð2pfo Þ2 Lload to 14.0 W (see Fig. 8b).

IEE Proc.-Electr. Power Appl., Vol. 151, No. 1, January 2004 23

4.2 Experimental results
Figure 9 shows the soft switching region obtained from (4).
v1 i1
In the Figure, the solid curve shows the theoretical inverter
output power calculated from (9). The solid circles show the
actual inverter power obtained in the experiment. The
data indicate that the actual inverter power is regulated
continuously by the PSM scheme from 10.39 kW to
0.28 kW under the condition of soft switching operation
and constant operation frequency.

12
200 V/div
10 25 A/div
5 µs/div
inverter output power Po , kW

8 soft switching region a

S1, S2: ZVZCS turn-on
S3, S4: ZVZCS turn-off
6
v4 i4
4

0
0 30 60 90 120 150 180
phase difference
, deg

Fig. 9 Soft switching region and power regulation performance

Ed ¼ 270 V, f0 ¼ 23.7 kHz,
Td ¼ 2.5 ms, Lload ¼ 46.5 mH, 200 V/div
Rload ¼ 4.5 ms, Cr ¼ 1.0 mF, 25 A/div
IGBT: CM100DV-12F 5 µs/div

Fig. 11 Observed waveforms

a Voltage and current of S1
Figure 10 shows the DC to AC power conversion b Voltage and current of S4
efficiency in this experiment. In general, the power factor for
IH load is low. Moreover, the measurement error of the
power meter becomes large when the power factor of the
object measured is low. Hence, we adopted a water-cooling Figure 11 shows the observed voltage and current
resistor and a no-core coil as an imitation IH load to waveforms when f ¼ 331. Figure 11a demonstrates that
evaluate conversion efficiency more precisely. In this Figure, S1 completed the ZVZCS turn-on. Furthermore, the turn-
to evaluate the effect of Csn, conversion efficiency was off operation was improved to ZVS condition due to the
measured both with Csn and without Csn. The turn-off voltage soft commutation effect of Csn. It seems that the
operation of S1 and S2 was improved to ZVS by Csn oscillating current included in the switch current was
increasing the efficiency from 0.6% to 9.8%. Under the derived from Csn and the stray inductor in both the DC
maximum output power condition, the actual inverter bus line and the IGBT module. However, it did not affect
efficiency reached 96.6%. the inverter operation. Figure 11b shows the voltage
and current waveforms of the switches in the current
leading mode. It can be seen that ZVZCS turn-off was
100 accomplished.

5 Conclusions
AC/DC conversion efficiency , %

95
with Csn
In this paper, a new cost-effective high-efficiency high-
90 frequency inverter with a PSM control scheme has been
proposed for induction heating applications, and experi-
mental evaluation of its switching operation has been
85 without Csn reported. This high-frequency inverter operates at the
resonant frequency of the series load resonant circuit, and
80 both soft switching operation and power regulation can be
realised by the PSM scheme in which the phase difference is
given by the gate pulses of the diagonal switches. The active
75
0 30 60 90 120 150 180
power switches in the left-hand bride leg operate in the
phase angle
, deg current lagging mode, which achieves ZVZCS turn-on. The
active power switches in the right-hand bridge leg operate in
Fig. 10 Power conversion efficiency the current leading mode, which achieves ZVZCS turn-off.
24 IEE Proc.-Electr. Power Appl., Vol. 151, No. 1, January 2004
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