Lecture 7

Multiplexers, Decoders and

Programmable Logic Devices
 Content
 Multiplexers, Decoders, and Programmable Logic
Devices
 9.1 Introduction
 9.2 Multiplexers
 9.3 Three-State Buffers
 9.4 Decoders and Encoders
 9.5 Read-Only Memories
 9.6 Programmable Logic Devices (PLD)
Programmable Logic Arrays (PLA)
Programmable Array Logic (PAL)
 9.7 CPLD
 9.8 FPGA

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 Introduction (1/2)
 The layout of a logic circuit could be very complicated if
only basic logic gates are used, especially a circuit with
multiple levels and outputs.

 An integrated circuit has been introduced to address this

problem.

3
 Introduction (2/2)
 Integrated Circuits (ICs)
 Small-scale integration (SSI)
• NAND, NOR, AND, OR, inverter, Flip-Flop
• 1-4 gates, 6 inverters, 1-2 Flip-flops
 Medium-scale integration (MSI)
• Adder, multiplexer, decoder, register, counter
• 12-100 gates
 Large-scale integration (LSI)
• Memories, microprocessors
• 100- a few thousand gates
 Very-large-scale integration (VLSI)
• Microprocessors, FPGA, Application-specific integrated
circuit (ASIC).
• Several thousand gates or more

4
 Multiplexers (1/7)
 Multiplexers (MUX, or data selector)
 A MUX has a group of data inputs and a group of
control inputs.
 The control inputs are used to select one of the data
inputs and connect it to the output terminal.

 2-to 1 MUX
 A=0, Z=I0
 A=1, Z=I1
 Z=A’I0+AI1

Control input

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 Multiplexers (2/7)

A=0, Z=I0
A=1, Z=I1

Input Output
A I0 I1 Z
1 1 1
1 0 1
0
0 1 0
0 0 0
1 1 1
1 0 0
1
0 1 1
0 0 0

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4-bits 2s-complement adder-subtractor
 Multiplexers (3/7)
 4-to-1, 8-to-1, 2n-to-1 MUX

 Logic equation for 8-to-1 MUX

Z  ABC I 0  ABCI1  ABC I 2  ABCI 3
 ABC I 4  ABCI 5  ABC I 6  ABCI 7

8
 Multiplexers (4/7)
 Logic Diagram for 8-to-1 MUX

Two level AND-OR Circuit

9
 Multiplexers (5/7)
 Logic equation for 2n-to-1 MUX

2 n 1
Z  mk I k
k 0
where mk is a minterm of the n control variables and
I k is the corresponding data input

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 Multiplexers (6/7)
 Quadruple Multiplexer – select one of the two 4-bit data.

A=0, (z0z1z2z3)=(x0x1x2x3)
A=1, (z0z1z2z3)=(y0y1y2y3)
 Bus: formed by several logic signals that
perform a common function.

 Multiplexer with bus inputs and output

A=0, Z=X
A=1, Z=Y
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 Multiplexers (7/7)
 Another type of multiplexer has an additional input called
an Enable, E.
 The E is connected to the fifth input of each AND gate.
 If E = 0 (active low), Z = 0, and if E = 1 (active high),
then the MUX functions as an ordinary 4-to-1
multiplexer.

active active
high low

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 Logic Circuits with MUXs (1/4)
 Multiplexers can be used to implement Boolean Functions.
 The control inputs can be thought as the input variables,
the data input are fixed values that are passed onto the
output according to the control inputs.

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 Logic Circuits with MUXs (2/4)
 For a -variable function, we need a MUX 2𝑛-to-1 with fixed
inputs.
 However, it is possible to use a MUX 2𝑛−1-to-1. This might
require extra NOT gates and non-fixed data inputs.

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Logic Circuits with MUXs (3/4)

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 Logic Circuits with MUXs (4/4)
 Example: Implement a MUX 4-to-1 using MUXes 2 to-1.

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 Three-State Buffers (1/9)
 A gate output can only be connected to a limited number
of device inputs without degrading the performance.

 A buffer may be used to increase the driving capability of

a gate output (high fan-out capability).

F C

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18
 Three-State Buffers (2/9)
 A logic circuit will not operate correctly if two or more
gates' outputs are directly connected.

 Three-state logic permits the outputs of two or more

gates to be connected.

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 Three-State Buffers (3/9)
 Three-state buffer (Tri-state buffer), which “tri-state”?

Buffer + switch

 Enable input B=1, output C=A.

 When B=0, C acts like an open circuit.
• C is effectively disconnected from the buffer
output, so no current can flow.
• This is referred to as a Hi-Z (high-impedance)
state
• The circuit offers a very high resistance or
impedance to the current.
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 Three-State Buffers (4/9)
 Four kinds of Three-State Buffers

B A C B A C B A C B A C
0 0 Z 0 0 Z 0 0 0 0 0 1
0 1 Z 0 1 Z 0 1 1 0 1 0
1 0 0 1 0 1 1 0 Z 1 0 Z
1 1 1 1 1 0 1 1 Z 1 1 Z

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 Three-State Buffers (5/9)
 Data Selection Using Three-State Buffers

D=B’A+BC

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 Three-State Buffers (6/9)
 Circuit with Two Three-State Buffers

S2
X 0 1 Z
S1 X X X X X
A0 0 X 0 X 0 
A1
S1  B1
1 X X 1 1 

S2 B0  Z X 0 1 Z
Outputs are conflict
D=1

Both buffers are enabled.

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 Three-State Buffers (7/9)
 Three-state bus
 A bus is driven by three-state buffers

 4-bit adder with four sources for one operand

 Use a 4-to-1 MUX to select one of several sources
 Alternatively, set up a three-state bus

1011

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 Three-State Buffers (8/9)
 Bi-directional I/O Pin

 Buffer is enabled
 The pin is driven with the output signal.

 Buffer is disabled
 An external source can drive the input pin.

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 Three-State Buffers (9/9)
 Design a 4-bit subtracter circuit with control input A in
which when A = 1, the output should be X – Y and Y – X
otherwise.

With multiplexer

With tri-state buffer

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 Decoders and Encoders (1/6)
 Decoder
 Generates all of minterms
 Exactly one of the output lines will be 1 for each
combination of the values of the input variables.
 3-to-8 decoder
a b c y0 y1 y2 y3 y4 y5 y6 y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
Binary Number

0 1 0 0 0 1 0 0 0 0 0

Minterm
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

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 Decoders and Encoders (2/6)
 4-to-10 Line Decoder with Inverted Output
BCD Input Decimal Output

A B C D 0 1 2 3 4 5 6 7 8 9

0 0 0 0 0 1 1 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 1 1 1 1
0 0 1 1 1 1 1 0 1 1 1 1 1 1
0 1 0 0 1 1 1 1 0 1 1 1 1 1
0 1 0 1 1 1 1 1 1 0 1 1 1 1
0 1 1 0 1 1 1 1 1 1 0 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
1 0 1 0 1 1 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1
1 1 0 0 1 1 1 1 1 1 1 1 1 1
1 1 0 1 1 1 1 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1

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 Decoders and Encoders (3/6)
 n-to-2n line decoder
 Generate all 2n minterms (or maxterms) of the n input
variables

 Outputs
 Noninverted
• yi=mi, i=0,1,2,…,2n-1
 Inverted
• yi=mi’=Mi, i=0,1,2,…,2n-1

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 Decoders and Encoders (5/6)
 Use a decoder and several logic gates to realize a
function
 Example: Realize the following multiple output
functions using a decoder.

f1 ( a ,b,c,d )m1 m2 m4

f 2 ( a ,b,c,d )m4 m7 m9

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 Decoders and Encoders (6/6)
 Sol (cont’d):
f1 ( a ,b,c,d )m1 m2 m4
f 2 ( a ,b,c,d )m4 m7 m9

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Decoder with ENABLE input

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 Decoder Cascading (1/2)
 Create a 3-to-8 Decoder from 2-to-4 Decoders

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 Decoder Cascading (2/2)
 Create a 4-to-16
Decoder from 3-to-8
Decoders

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 Decoders and Encoders (6/6)
 Encoder
 The inverse function of a decoder
d=0 if there is no 1.
 8-to-3 Priority Encoder
y0 y1 y2 y3 y4 y5 y6 y7 a b c d
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
X 1 0 0 0 0 0 0 0 0 1 1
X X 1 0 0 0 0 0 0 1 0 1
X X X 1 0 0 0 0 0 1 1 1
X X X X 1 0 0 0 1 0 0 1
X X X X X 1 0 0 1 0 1 1
If more than one input is 1,
X X X X X X 1 0 1 1 0 1
the highest numbered input
determines the output. X X X X X X X 1 1 1 1 1
X: don’t care
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 Combination
 Given the following circuit, what Enabled 2x4 DECoder
is the Boolean Equation for T? Input Output
E S1 S0 D0 D1 D2 D3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 X X 0 0 0 0

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 Solution
Given the following circuit, what is the Enabled 2x4 DECoder
Boolean Equation for T?
Input Output
E S1 S0 D0 D1 D2 D3
=0 1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 X X 0 0 0 0
=0 =1
T = Z.P'.Q'
Since
P = Z'.A + Z.B
Method 1: and Q = Z'.C + Z.D
we have
T = Z.( Z'.A + Z.B )'.( Z'.C + Z.D )'
= Z.( Z + A' ).( Z' + B' ).( Z + C' ).( Z' + D' )
= Z.( Z + A' ).B'.( Z + C' ).D'
= Z.B'.D'
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 Solution
Given the following circuit, what is the Enabled 2x4 DECoder
Boolean Equation for T?
Input Output
E S1 S0 D0 D1 D2 D3
=0 1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 X X 0 0 0 0
=0 =1

Method 2:
We observe that T can only be 1 if Z=1 and PQ = 00. Hence T =Z.P'.Q'.

When Z=1, P=B and Q=D,

hence T = Z.B'.D'.
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 Read-Only Memories (1/7)
 Read-Only Memory (ROM)
 Consists of semiconductor devices that are
interconnected to store binary data.
A B C F0 F1 F2 F3
0 0 0 1 0 1 0
0 0 1 1 0 1 1
0 1 0 0 1 1 1
0 1 1 0 1 0 1
1 0 0 1 1 0 0
1 0 1 0 0 0 1
1 1 0 1 1 1 1
1 1 1 0 1 0 1
3-bit address line and 23 output patterns (words).

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 Read-Only Memories (2/7)
 A 2nxm ROM can realize m functions (F1, F2,…Fm) of n
variables.
 A ROM consists of a decoder and a memory array.

Address
decoder

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 Read-Only Memories (3/7)
 Multiple-output combinational circuits can be realized
using ROMs.
 Example: Realize the following functions using ROM.

 Sol:
• If all minterms have already been generated, the
output can be realized by

41
 Read-Only Memories (4/7)
 Sol (cont’d):

Wire-OR

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 Read-Only Memories (5/7)
 Example: Design a code converter that converts a 4-bit
binary number to a hexadecimal digit and outputs the 7-
bit ASCII code.
W X Y Z Hex A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 1 1 0 0 0 0
0 0 0 1 1 0 1 1 0 0 0 1
0 0 1 0 2 0 1 1 0 0 1 0
0 0 1 1 3 0 1 1 0 0 1 1
0 1 0 0 4 0 1 1 0 1 0 0 A5=A4 and A6=A4
0 1 0 1 5 0 1 1 0 1 0 1
0 1 1 0 6 0 1 1 0 1 1 0
0 1 1 1 7 0 1 1 0 1 1 1
1 0 0 0 8 0 1 1 1 0 0 0
1 0 0 1 9 0 1 1 1 0 0 1
1 0 1 0 A 1 0 0 0 0 0 1
1 0 1 1 B 1 0 0 0 0 1 0
1 1 0 0 C 1 0 0 0 0 1 1
1 1 0 1 D 1 0 0 0 1 0 0
1 1 1 0 E 1 0 0 0 1 0 1
1 1 1 1 F 1 0 0 0 1 1 0

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 Read-Only Memories (6/7)
 Sol: Because A5=A4 and A6=A4’, the ROM needs only
five outputs. The ROM size is 16 words by 5 bits. The
decoder is a 4-to-16 decoder.

44
 Read-Only Memories (7/7)
 Types of ROMs
 Mask-programmable ROMs
 Programmable ROMs (PROMs)
 Electrically Erasable Programmable ROMs
(EEPROMs, E2PROMs)
• Apply extra high voltage for content rewritten

PROM

45
 Read-Only Memories (7/7)
 Types of ROMs
 Flash memories
• Flash memory has built-in programming and
erase capability so that data can be written to it
while it is in place in a circuit without the need for
a separate programmer.
• Similar to EEPROMS but with different charge-
storage mechanisms.

46
 Programmable Logic Devices
 Programmable Logic Device (PLD)
 A general name for a digital integrated circuit capable
of being programmed to provide various logic
functions.
 Lower cost
 Changes in design
• Changing the programming of PLD without
changing the wiring

47
 Programmable Logic Arrays (1/4)
 Programmable Logic Array (PLA)
 Perform the same basic function as a ROM
 A PLA with n inputs and m outputs can realize m
functions of n variables.
Product Terms

Two-level AND-OR circuits

48
 Programmable Logic Arrays (2/4)
 Example:
 Realize the following functions using PLA.
F0 m0,1,4,6 A'B ' AC '
F1 m2,3,4,6,7  B AC '
F2 m0,1,2,6 A'B ' BC '
F3 m2,3,4,6,7  AC  B

 Sol:

49
 Programmable Logic Arrays (3/4)
 Sol (cont’d): AND-OR equivalent circuit
Logic gate form Product
Sum terms
terms

A B C F F F F
0 1 2 3

A’B’ 0 0 – 1 0 1 0
AC’ 1 – 0 1 1 0 0
B – 1 – 0 1 0 1
BC’ – 1 0 0 0 1 0
AC 1 – 1 0 0 0 1

F0  A'B' AC '
F1  AC ' B
F2  A'B' BC '
F3  B AC

50
 Programmable Logic Arrays (4/4)
 Example: Use PLA to realize f1, f2, and f3.
 Sol: Construct the PLA table a b c d f1 f2 f3
f1 a 'bd abd ab'c' b'c a’bd 0 1 – 1 1 1 0
f 2 ca 'bd abd 1 1 – 1 1 0 1
ab’c’ 1 0 0 – 1 0 1
f 3 bcab'c' abd
b’c – 0 1 – 1 0 0
c – – 1 – 0 1 0
bc – 1 1 – 0 0 1

51
 Various type of PLA
 Types of PLAs
 Mask-programmable PLAs
 Field Programmable PLAs (FPLA)

52
 ROMs versus PLAs
 If the number of input variables is small, PROM may be
more economical than PLA.

 When the number of input variables is large, PLAs are

preferred.

53
 Programmable Array Logic (1/3)
 Programmable Array Logic (PAL)
 A special case of the PLA in which the AND array is
programmable and the OR array is fixed.
 Less expensive than the general PLA
 Easier to program
 Symbols

X means the connection to the AND gate input.

54
 Programmable Array Logic (2/3)
 Example:

55
 Programmable Array Logic (3/3)
 Example: Implement a full adder using a PAL.
 Sol:

X’Y’Cin

56
 Complex Programmable Logic Devices (CPLD) (1/3)
 CPLD includes many PALs and PLAs
 CPLD has four function blocks with 16 associated
macrocells (MC1, MC2, …).
 Each function block is a PLA.

Architecture of Xilinx XCR3064XL CPLD

57
 Complex Programmable Logic Devices (CPLD) (2/3)
 Each macrocell contains a flip-flop and MuX that routes
signals from the function block to the I/O block or the
interconnect array (IA).

 The IA selects signals from the macrocell outputs or I/O

blocks and connects them to function block inputs.

Architecture of Xilinx XCR3064XL CPLD

58
 Complex Programmable Logic Devices (CPLD) (3/3)
 The figure shows a signal generated in the PLA routed
to an I/O pin through a macrocell.

 Any 36 outputs from the IA can be connected to any

inputs of the 48 AND gates. Each OR can accept up to
48 product term inputs from the AND array.

59
 Field Programmable Gate Arrays (FPGA)
 FPGA is an IC that
contains an array of
identical logic cells
with programmable
interconnections.
CLB

 The interior of the

FPGA consists of an
array of logic cells
known as
configurable logic
blocks (CLBs).

60
 Field Programmable Gate Arrays (FPGA)
 CLB contains two function Function
Generators
Multiplexers Flip Flops

generators, 2 FFs, and

various multiplexers for
routing signals within the
CLB.

 Each function generator

has four inputs and can
implement any function of
up to four variables. Simplified CLB

 The function generators LUT = ROM with 16 1-bit words

are implemented as lookup
tables (LUTs).
61
 Field Programmable Gate Arrays (FPGA)
 The H multiplexer
selects either LUT F or Function
Multiplexers Flip Flops

Generators
LUT G depending on
the value of H1.

 The CLB has

 Two combinational
outputs (X and Y)
 Two flip-flop outputs
XQ and YQ.

Simplified CLB

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 End of Lecture 7

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