MICROPROCESSOR
G. S. Mandal’s
MITPOLYTECHNIC,ROTEGAON,VAIJAPUR
DEPARTMENT OF COMPUTER ENGINEERING
“ADDRESSING MODE”
Micro Project Report
Submitted in partial fulfillment of the requirements for the 4th
semester
Diploma in Computer Engineering
For the Academic Year
2023-24
NEHA SANJAY CHAVAN (2207770164)
RADHIKA SUNIL KOTKAR (2207770114)
ISHWARI VISHNU BORDE (2207770115)
SIDDHI BAPUSAHEB BOTHE (2207770089)
UNDER THE GUIDANCE OF
Prof. V. T. HOLE
Dept. of Computer Engg. & Technology,
MIT Polytechnic, Rotegaon
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
G. S. Mandal’s
MIT POLYTECHNIC, ROTEGAON, VAIJAPUR
DEPARTMENT OF COMPUTER ENGINEERNIG
CERTIFICATE
This is to certify that the micro project entitled “ADDRESSING MODE”
study work carried out by NEHA CHAVAN in partial fulfillment of Micro-
project of subject MICRO PROCCESOR(MIC) having course code (22415) for
the award of Diploma in Computer Engineering (CO4I) in MIT Polytechnic,
Rotegaon during year 2023-24.
Signature of Project Guide Signature.
Prof. V. T. HOLE Prof. S. RAM
Lect. Dept. of Comp. Engg. Head of Department[CO]
MIT Polytechnic, Rotegaon MIT Polytechnic, Rotegaon
Signature of Principal
Prof. K . S. Patil
MIT Polytechnic, Rotegaon
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
G. S. Mandal’s
MIT POLYTECHNIC, ROTEGAON, VAIJAPUR
DEPARTMENT OF COMPUTER ENGINEERNIG
CERTIFICATE
This is to certify that the micro project entitled “ADDRESSING MODE”
study work carried out by RADHIKA KOTKAR in partial fulfillment of
Micro-project of subject MICRO PROCCESOR(MIC) having course code
(22415) for the award of Diploma in Computer Engineering (CO4I)in MIT
Polytechnic, Rotegaon during year 2023-24.
Signature of Project Guide Signature
Prof. V. T. HOLE Prof. S. RAM
Lect. Dept. of Comp. Engg. Head of Department[CO]
MIT Polytechnic, Rotegaon MIT Polytechnic, Rotegaon
Signature of Principal
Prof. K. S. Patil
MIT Polytechnic, Rotegaon
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
G. S. Mandal’s
MIT POLYTECHNIC, ROTEGAON, VAIJAPUR
DEPARTMENT OF COMPUTER ENGINEERNIG
CERTIFICATE
This is to certify that the micro project entitled “ADDRESSING MODE”
study work carried out by ISHAWARI BORDE in partial fulfillment of
Micro- project of subject MICROPROCCESOR(MIC) having course code
(22415) for the award of Diploma in Computer Engineering (CO4I) in MIT
Polytechnic, Rotegaon during year 2023-24.
Signature of Project Guide Signature
Prof. V.T. HOLE Prof. S. RAM
Lect. Dept. Comp. of Engg. Head of Department[CO]
MIT Polytechnic, Rotegaon MIT Polytechnic, Rotegaon
Signature of Principal
Prof. K. S. Patil
MIT Polytechnic, Rotegaon
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
G. S. Mandal’s
MIT POLYTECHNIC, ROTEGAON, VAIJAPUR
DEPARTMENT OF COMPUTER ENGINEERNIG
CERTIFICATE
This is to certify that the micro project entitled “ADDRESSING MODE”
study work carried out by SIDDHI BOTHE in partial fulfillment of Micro-
project of subject MICROPROCCESOR(MIC)having course code (22415) for
the award of Diploma in Computer Engineering (CO4I) in MIT
Polytechnic, Rotegaon during year 2023-24.
Signature of Project Guide Signature
Prof. V.T. HOLE Prof. S. RAM
Lect. Dept. of Comp. Engg. HeadofDepartment[CO]
MIT Polytechnic, Rotegaon MITPolytechnic,Rotegaon
Signature of Principal
Prof. K. S. Patil
MIT Polytechnic, Rotegaon
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
INTRODUCTION
The operation field of instruction in a computer specifies the operation to be
performed. This operation must be executed on the data stored in computer
registers. The operands chosen during program execution depend on the
instruction addressing mode. The addressing mode specifies a rule for
modifying the address field of the instruction before referencing the operand.
The computers use addressing mode techniques to accommodate the following
provisions:
1. It provides programming versatility to the user by including
pointers to the memory, indexing of data, counters for loop
control, and program relocation.
2. It reduces the number of bits in the addressing field of the instruction.
3. It also provides flexibility to the assembly language programmer in
writing more efficient programs concerning the number of instructions and
execution time.
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
Types of Addressing Modes
➢ Implied/Implicit Addressing Mode:-
The operands are implicitly specified in the instruction’s definition.
Consider the example, the instruction “complement accumulator” is an implied-
mode instruction as the operand in the accumulator register is implied in the
instruction definition. All register reference the instructions that use an
accumulator are implied-mode instructions. Zero-address instructions in a stack-
organized computer are also implied-mode instructions because the operands are
implied to be on top of the stack.
➢ Immediate Addressing Mode:-
The operand is defined in the instruction itself. This mode instruction has an
operand field instead of an address field. The operand field contains the actual
operand used with the specified operation in the instruction. The immediate-
mode instructions help initialize registers to a constant value.
For example: ADD 8 will increment the values to red in the accumulator by8.
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
➢ Register Direct Addressing Mode:-
The operands that reside with in the CPU are stored in the registers. The
specific register is selected from a register field in the instruction. No reference
to the memory is required to fetch the operand. The only difference between
the Direct addressing mode and the register direct addressing mode is that the
instruction address field refers to a CPU register instead of the main memory.
Advantage: This mode provides faster memory access to the operands.
Disadvantage: It has limited address space, and using multiple registers can
help boost the performance, but it complicates the instructions.
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
➢ Register Indirect Addressing Mode:-
The instruction defines a register in the CPU that stores the effective address of
the operand in memory. Only one reference to the memory is required to fetch
the operand. The specified register contains the address of the operand instead
of the operand. The only difference between the Indirect addressing mode and
the register indirect addressing mode is that the instruction address field refers
to a CPU register.
For example: ADD R1, R2: Here, the content of R2 is added to R1.R1R2
represents registers.
Advantage: The instruction address field uses fewer bits to select a register
than required to specify a memory address directly.
➢ Auto-Increment Addressing Mode:-
This mode is a special Register Indirect Addressing Mode case. The register is
incremented/decremented after or before its value is utilized.
EA=content of the register.
The content of the register is increment automatically by step size ‘d’ after
accessing the operand, where the step size ‘d’ depends on the size of the
accessed operand. Only one reference memory is required to fetch the operand.
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
Consider an example:
Here, the Effective Address(R)=178,and the operand in AC are 7.After loading R1
is incremented by 1 and becomes 179.
➢ Auto-Decrement Addressing Mode:-
This mode is also a special Register Indirect Addressing Mode
case. EA = content of the register - step size.
The content of the register is decremented by step size ‘d’ after accessing the
operand, where the step size ‘d’ depends on the size of the accessed operand.
Only one reference memory is required to fetch the operand.
Consider an example: Here, register R1 is decremented by 1 (400-1=399) prior
to the instruction execution which implies that the operand
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
loaded to the AC is of address 1099H instead of 1088H. Hence, the Effective
Address is 1099H.
➢ Direct Addressing Mode:-
The effective address of the operand resides in the address field of the
instruction. The operand resides in the memory, and the address field of the
instruction gives its address. Only one reference to the memory is required to
fetch the operand, and no additional calculations need to be done to find the
effective address of the operand. It is also known as absolute addressing mode.
For example, ADD X will increment the value stored in the accumulator by the
value stored at X's memory.
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
➢ Indirect Addressing Mode:-
The address field of the instruction gives the address of the memory location
that contains the effective address of the operand. Two references to the
memory are required to fetch the operand: The control fetches the instruction
from memory and uses its address part to reaccess the memory that stores the
effective address. This addressing mode slows down the execution as it
requires multiple memory lookups to find the operand.
The indexed register content is added to the instruction’s address part to obtain
the effective address of the operand.
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
EA=A+(R)
Here, the address field holds two values, A: Base value R: displacement value.
Relative Addressing Mode:-
This mode is another version of the displacement address mode. The program
counter’s content is added to the instruction’s address part to obtain the
effective address.
EA=A + (PC)
Here, EA: Effective address, PC: Program counter.
The instruction’s address part is usually assigned number that can be positive
or negative. After the instruction’s address is fetched, the value of the program
counter increases immediately, irrespective of whether the fetched instruction
has been executed or not. PC: It contains the address of then ext instruction to
be executed
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
➢ Base Register Addressing Mode:-
This mode is another version of the displacement address mode. To
obtain the effective address, the base register’s content is added to the
instruction’s address.
EA=A+(R)
A: Displacement, R: Pointer to the
Base address.
➢ Stack Addressing Mode:-
The operand resides at the top of the stack. Consider an example, ADD: This
instruction will POP two items from the stack, add them, and at last, will PUSH
the result to memory references of Addressing Modes.
It helps in reducing the number of bits in the instruction's addressing
field. It facilitates pointers, indexing of data, and counters for loop
controls.
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
MICROPROCESSOR
CONCLUSION:
For the conclusion of your addressing mode project, you should summarize the
key findings, insights, and outcomes of your research or analysis. Highlight the
significance of addressing modes in computer architecture, discuss any
challenges encountered during the project, and suggest possible areas for future
exploration or improvement. Emphasize the importance of understanding
addressing modes for computer programming and system design. Finally,
conclude with a statement that reinforces there leveance and impact of
addressing modes in modern computing.
REFRENCE:
1. https://r.search.yahoo.com
2. https://www.google.co.in
ADDRESSINGMODE-NEHACHAVAN,RADHIKAKOTKAR,ISHWARIBORDE,SIDDHIBOTHE
