FPD-Link™ high speed design and channel

requirements
Aaron Heng, Applications Engineer
Bryan Kahler, Applications Engineer
Overview
• FPD-Link™ channel requirements
– Signaling topologies
– PCB elements and transmission loss characteristics
– Key channel parameters
• High speed design
– Connectors and cables
– PCB dielectrics
– Layout considerations

2
FPD-Link III signal topologies

3
FPD-Link III transmission channel
• Transmission channel refers to the transmission media that connects a
Serializer to a Deserializer integrated circuit
• It is not just the cable harness, but includes board traces, components and
board parasitic in the Serializer and Deserializer boards
• In a typical SER or DES board, channel in the SER or DES boards include
– AC coupling capacitors
– Common mode choke
– PCB traces
– PCB parasitic
• Cable harness includes connectors, cable and in-line connectors

4
Transmission channel: differential signaling
TRANSMISSION
CHANNEL

SER BOARD DES BOARD

FPD Link III CABLE ASSEMBLY
CM INTERCONNECT INTERCONNECT FPD Link III
SERIALIZER CAC_P Choke
Video, CM Choke CAC_P DESERIALIZER
STQ – Pair1 2 Control
FC HSD HSD FC
Image STQ – Pair2 2 Connector
TX Connector RX
Source
VDD2 GND
BC BC
CAC_N CAC_N TX
RX
VDC,
GND
VDC,
VDD1 GND GND

VIDEO
VIDEO VFEED
Power CONTROL Power
SOURCE Regulators Regulators
UNIT POWER DISPLAY
UNIT

• Transmission Channel for FPD-Link III refers to the interconnecting elements from a Serializer to a Deserializer
• Includes PCB differential traces, AC Coupling capacitors, common mode choke (optional), connector, and cable
• Transmission Channel = SER Board + Cable Assembly + DES Board
5
Transmission channel: single-ended signaling

• Transmission Channel for FPD-Link III refers to the interconnecting elements from a Serializer to a Deserializer
• Includes PCB trace, AC Coupling capacitor, PoC network (optional), connector, and cable
• Transmission Channel = SER Board + Cable Assembly + DES Board
6
SER-board and DES-board elements

• Channel Transmission Loss = IL (SER-Board) + IL (Cable) + IL (DES-Board)

• Transmission loss of SER-Board and DES-Board are usually small compared with that of cable
• Maintain good impedance, minimize impedance mis-match
• For PoC, choose PoC network that will not impact the board’s impedance 7
Characteristic impedance

• PCB and Cable Impedance designed to match with termination impedances of SER and DES
• Differential signaling: 100 Ω ± tolerance
• Single-end signaling: 50 Ω ± tolerance
• Excessive impedance mis-match causes reflection that degrades signal quality
8
Return loss
• Return loss measures impedance matching versus
frequency
• Indicative on how well device’s impedance matches a
reference impedance (100 Ω for differential, 50 Ω for
single-end)
• Indicative on signal reflection and echo due to
impedance mis-match

9
Insertion loss

• Channel behaves as a Low-pass-filter: higher signal attenuation at higher frequencies

• Channel Useable bandwidth depends on:
o Linear region, free of resonance
o Insertion loss within the range that a SER and DES can compensate
10
Insertion loss from PCB traces

• PCB board trace contributes a small portion of the Transmission Channel’s loss
• A 5-mil FR4 stripline has about 0.37 dB/inch at 2 GHz
• A 6-mil FR4 microstrip has about 0.31 dB/inch at 2 GHz

11
Cable aging and mechanical stress

• Insertion loss changes due to cable aging

• Return loss will also change due to bending or dynamic movement of a cable segment (eg flip-display)
• Temperature cycling and mechanical stress tests are usually done during cable qualification to assess possible impact to
link robustness
12
FPD-Link IV High Speed Design
• Connectors and cables
• PCB dielectrics
• Layout considerations
High-speed PCB design goals
• Tight impedance control (eg 100Ω ±5%)
• Minimize impedance mis-match (eg 100Ω ±10%)
• Minimize use of via and via stub
• Minimize insertion loss (typical -1.9dB)
• Minimize differential return loss (typical -12dB)
• Minimize mode conversion
– Intra-pair skew matching (50 ps of tRX HBR3)
– Inter-pair skew matching
• Minimize crosstalk

14
Planning high-speed PCB design
• Placement
• Signal speed
• Power supply
• Sensitive signals
• Component selection

15
PCB design for low EMI
• Each signal trace needs an adjacent return path (plane or trace)
• Every power trace or plane needs an adjacent return path (plane or trace)
• Return path through layers
– Ground vias
– Stitching capacitors

16
Good versus poor four-layer design
Good Poor

• Low EMI • Poor stack-up is likely in high EMI risk.

• Power return plane is closer. • Power and ground return plane are too
far apart from the ground reference and
• Both internal or external signals has
power plane ~20 – 30mils.
immediately return path.
• Signals on layer 4 are referenced to
power instead of signals return path.

17
Low EMI six-layer stackup
Good Poor

• Each signal layer has adjacent • Common stack-up

return path • Signal referenced to power
• Power immediately return path to • Power and return plane too far
ground plane separated
• Power transients couple to inner
signal layers

18
Multi-layer stack up using microstrip
Hybrid Board

• Planning for stack up

• Material selection
• Cost saving

19
Structures of microstrip and stripline

• microstrip • stripline
– Simple routing and easy to construct – More complex to fabricate
– Cheap to fabricate – Manufacturing drives the cost
– Easy for assembly – Signal path discontinuities
– Reliability – Harder for troubleshooting
– Very low impedance
– Require multiple layers
20
Examples of uniform board structures
Microstrips Coplanar
Edge Coupled Striplines

Solder mask
If GND-fill is used, it may create a co-planar structure

Broad-side Coupled Striplines

NI: TX Line:
Buried Microstrips Link to Free Download

 Estimate impedance with an Impedance Calculator

21
Eight layer stack up for stripline
• Microstrip routing from 983 to AC
coupling caps
• Split routing can be done at the AC
coupling caps
• Requires additional CMC and ESD

22
Material data rate, dielectric constant, loss tangent
Supported Data Rate
Material r Tan ()
(GHz)
Isola 370HR 1 4.17 0.016
Isola FR408HR 1 3.69 0.009
Isola I-Speed 1 3.65 0.0058
Megatron 6 1 3.71 0.002
Nelco 4800-20 2 3.70 0.007
Rogers 4350B 10 3.48 0.0037

23
Normalized material cost comparison
Material Group Vendors Specific FR4 Relative Cost Factor
High Tg Isola 370HR 1.1
High Frequency Isola FR408HR 1.8
High Frequency Isola I-Speed 3.3
High Frequency Nelco 4800-20 4.2
High Frequency Megtron 6 5
High Frequency Rogers 4350B 5.6

24
Discontinuous return path
• Common PCB problems can be traced
to discontinuous signal. When design
PCB for the FPD-Link frequencies used
for 98x family device, this is becoming
more of an issue.
• Often, the return path is disconnected
by most error
– Discontinuity such as gap or slot in the
Image Source: Sierra
return plane or power plane
– Changing reference planes

25
Differential traces

• Symmetry: Uniform Width, Uniform Gap

• Bends: 45o or Radial (smooth angle routing)
• Tightly coupled traces to minimize inter-pair crosstalk
• If only P-signal is used, loosely couple traces should be used
• Minimize impedance discontinuity: due to trace branching out
• Minimize impedance discontinuity: due to large landing pads
• Manage Intra-pair skew matching
• Manage Inter-pair skew matching 26
Impedance mis-match from landing pads

27
Controlled-impedance landing pads
VDD/GND relief layer
below landing pad
48 33

49 32

64 17

1 16

Cross Section A-A Cross Section B-B

Z diff  100 Z diff  100

28
Avoid via stub

• Via Stub introduce capacitive effect to signal, increase signal loss

• Place signal layer toward bottom side of the board -> minimize Via Stub (<15 mil)
• Top-mount through-hole component -> use bottom trace routing to avoid Via Stub
• Use back-drill to remove via stub for very high speed applications (> 10 Gbps)

29
Differential via
• Stripline method normally introduces signal via
• Two differential vias must be maintained close proximity between the
two conductor vias
• Anti-pad clearance applies to all layers
• Use back drilling method to remove unused via cylinder (copper barrel)
for all high speed routing signal path

30
Controlled impedance footprint for connectors

• Use PWR/GND VOID under landing pad • Use large anti-pad around via
• Keep landing pad impedance same as trace • Keep via impedance same as trace
• Consult connector vendor for optimize footprint • Consult connector vendor for optimize footprint

31
Minimize crosstalk
• Use coupled differential pairs
– eg. 5-5-5, 5 mil air gap w/ 5 mil trace widths
• Maximize separation between adjacent pairs (S > 5W)
– Use alternate layer routing if too many pairs on one layer
• Use staggering via or components (eg AC coupling capacitors)
to keep separation between adjacent pairs
• Use G-S-S-G to minimize via crosstalk
• No rule of thumb, layout decision based on simulation result

32
Bypass capacitor routing
example
in in
• Place bypass capacitors on same side of board as component out

being decoupled or underneath the device out

output
• Locate as close to pin as possible return
Ground
Ground output
• Keep trace width thick and short BAD!!!
return
Good

1µF Capacitor Impedance With Various ESL

Bad
5nH

Good 1nH

Better

Best

33
VDD-GND bypass - QFN

• Use low inductance path to VDD and GND planes

• Via tangent from pin to plane, no trace
• >1 VDD via if space allows
• Larger via hole size if space allows
• Use small physical size low inductance bypass capacitor, 0402 or smaller
• Bypass capacitors placed on bottom layer sharing DAP GND via array
• Bypass capacitor via straight to planes, no trace
• Use sandwiched VDD-GND layers to build a good RF bypass capacitor
• Use as small a package as possible for best decoupling performance
34
Heat transfer

• There are three methods of heat transfer: heat conduction through solids, heat convection through fluids
and gases, and heat generated by radiation.
• Heat transfer occurs when there is a temperature difference between two objects or between different
areas of an object, and its rate depends on the geometry, thickness, and material of the object.
• Heat transfers from a hotter body to a colder body until the whole system reaches final equilibrium

35
Thermal relief
• The Die-attach pad (DAP), if present, provides the most dominant thermal path between the PCB and the die.
• Packages with a DAP, such as QFN package, have a large exposed surface area through which heat can transfer quickly.
• The die and exposed pad glues with non-conductive epoxy where the heat dissipation can quickly extract from the device.
• For fast thermal relief, any unused plane can utilize this by creating equivalent DAP size. It conducts heat from the exposed
pad of the package to the PCB ground plane.

36
Example layout: DS90Ux9xx-Q1EVM

983 Molex HSAL2

DisplayPort

• Runway is kept free from any obstacles that might impede high speed signal path
• Place FPD-Link IV output signals as close as possible to the output connector

37
Example layout: DS90Ux9xx-Q1EVM

FPD-Link IV

SMA

983 HMTD

DisplayPort

38
Example layout: DS90Ux9xx-Q1EVM
To minimize crosstalk, keep the distance between two traces approximately 2 to 3 times the width of the trace.

39
Convert microstrip to stripline

• Requires additional layers

• Introduce more vias

40
FPD-Link IV output connector layout
recommendation
• Avoid through-hole connector stub
• Oval anti-pad clearance for both P and N signals

41
Summary
• FPD-Link™ channel requirements
– Signaling topologies
– PCB elements and transmission loss characteristics
– Key channel parameters
• High speed design
– Cables and connectors
– PCB dielectrics
– Layout considerations
• Please visit training.ti.com for more FPD-Link training information

42
FPD-Link™ channel training
• FPD-Link parameters & transmission channel module
– High speed serial link basics
• https://training.ti.com/high-speed-serial-link-basics
– Basic transmission parameters
• https://training.ti.com/basic-transmission-parameters
– Common connectors and cables for automotive applications
• https://training.ti.com/common-connectors-and-cables-automotive-applications
– What you need to know about the transmission channel
• https://training.ti.com/what-you-need-know-about-transmission-channel
– In-line and common mode chokes - use and effect on the transmission channel
• https://training.ti.com/line-and-common-mode-chokes-use-and-effect-transmission-
channel
– Channel specification available from FAE
43
Questions?

44
Appendix

45
Appendix A: FPD-Link Channel Specification

46
Key Channel Parameters
• Characteristic impedance
– defines the channel’s impedance matching to the termination of the SER and DES.
• Impedance mis-match
– defines the allowable impedance variations caused by connectors or PCB structures.
• Return loss
– defines the channel’s impedance matching and measures of reflections caused by
discontinuities along the full-duplex link. The return loss includes the effect of on-board
components.
• Insertion loss
– is the attenuation of signals; including that of SER-board, cable assembly and DES-
board. A longer PCB trace introduces higher insertion loss for the board. The channel’s
insertion loss should be within the range supported by the SER-DES chipset

47
Key Channel Parameters (II)
• Intra-pair skew
– Skew between P- and N- signals within the pair; excessive intra-pair skew affects
signal integrity of the DES. A common mode choke placed at the input of the DES
reduces the amount of intra-pair skew caused by an un-balanced cable assembly, but
also add small amount of insertion loss.
• Inter-pair skew/ Cross-talk
– defines the maximum allowable lane-to-lane skew for adjacent FPD-Link channels
used in a multi- link DES.
– Excessive crosstalk affects the signal integrity for the SER and DES by reducing the
signal-to-noise ratio. Cross-talk appears in a cable with more than one signal lane that
share one connector, for example, a HSD STQ cable if both pairs are used for FPD-
Link, or four coaxial cables that connect to a quad-mini-FAKRA connector.

48
Key Channel Parameters (III)
• Aging and Mechanical Stress
– Cable assembly dependent. Aging usually introduces increase in insertion loss, while
mechanical stress usually manifests as a degradation in the cable’s characteristic
impedance and return loss.
• Shielding Effectiveness
– Defines the effectiveness of the shield braid in attenuating EMI radiation or EMC pick-
up. Shielding effectiveness is dependent on the braid’s density and the connector’s
contact ground impedance. Contact cable suppliers on shielding effectiveness.

49
Appendix B: Component Considerations

50
Common Mode Choke (CMC)
• Common mode choke is a miniature component designed to attenuate common
mode signal with small effect on differential signal
• It is used in differential transmitter for EMI mitigation or in a differential receiver
for reducing intra-pair skew

51
Common Mode Choke Suitability
• Common mode choke adds small amount of insertion loss to the transmission
channel
• Choose a common mode choke with
– Smallest differential insertion loss at the Nyquist frequency of the forward channel
transmission
– Good differential return loss Footprint 0805 Footprint
DCR 0.25 ohms
– High common mode attenuation
Current Rating 400 mA
– 98xEVM used DLW21SZ900HQ2
Temp Rating -40°C to +105°C
Cutoff Frequency 10 GHz

Differential Insertion Loss Impedance Characteristic 52

Common Mode Choke (DLW21SZ900HQ2)

• Eliminate any unwanted noise interference

• Prevents the interference from affecting the
required high speed signal
• Suppress noise reduction
• Minimize the effect of any mismatch
impedance
• Designed to correct line impedance when
ESD protection diode is used

53
ESD Protection Diode Layout

• To support 13.5Gbps the capacitance of the

ESD device must be lower than 0.30pF for
optimal performance
• Both ESD devices mentioned have lower
capacitances
– TPD1E01B04
– TPD1E0B04
• ESD protection diode as close as possible to the
connector
• Create anti-pad clearance underneath the layer 54
SLYP689
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