a.
Reduce the following Boolean Expressions to minimum
number of literals.
i. x(x’+y) ii x+x’y
ii. (x+y)(x+y’) iv xy+x’z+yz
iii. (x+y)(x’+z)(y+z)
b. Show that a positive logic NAND gate is a negative logic NOR gate.
c. For the given
F(ABCD)= A’B’+ CD’+ABC+A’B’CD’+ABCD’
a. Plot K map without expanding minterms.
b. Identify PI, EPI.
c. Find SOP solution in minimal form.
d. Design AND-OR circuit for SOP expression.
e. Design Verilog Code for the simplified expression.
a. Simplify and implement using NAND gate:
F(x,y,z)=∑m(1,2,3,4,5,7)
b. Develop a Verilog code using dataflow and behavioral model
for the expression
F (A, B, C, D) = (AB’+A’B)(CB+AD’)(AB’C+AC)
c. Determine the Minimal SOP solution for the following
expressions and design using Basic Gates:
i. F=C ‘D + ABC ‘+ ABD ‘ + A ‘B ‘D
a. Differentiate between Combinational and Sequential
ii. F(wxyz) =Ʃ m(0,1,10,11,13,15) +d(2,3,12,14)
Circuits with examples.
b. Explain the structural model of Verilog Programming with an
example.
c. Implement the design of combinational circuit BCD and
Excess3 code convertor.
a. Describe the design procedure followed in design of
combinational circuits.
b. Explain the working of 3:8 Decoder with block diagram, truth
c. Explain the working of Full Adder circuit with Block
table, derive output expressions and design the logic diagram.
Diagram, truth table, Output Expression and design
logic diagram. Develop Verilog Code for Full Adder
Circuit
a. Prove that Positive OR is Negative AND logic.
b. Design Verilog HDL to describe data flow model with
a programming example.
c. Find all the prime implicants for the following Boolean
functions, and determine EPI . Also find the minimal
SOP.
(a)F (w, x, y, z) = ∑ (0, 2, 4, 5, 6, 7, 8, 10, 13,
15)
(b) F (A, B, C, D) = ∑ (0, 2, 3, 5, 7, 8, 10,
11, 14, 15)
a. Design using Multi-level NAND gates
F= W(X+Y+Z)+XY
b. For the Circuit given , develop Verilog code using
structural model
Find all the prime implicants for the following Boolean
functions and determine EPI. Also find the minimal
SOP solution.
i. F (A, B, C, D) = ∑ (1,3,4,5,10,11,12,13,14,15)
ii. F (A, B, C, D) = ∑ (0, 1,2,5,7,8,10,15)
a. Implement full adder using 3:8 decoder.
b. Differentiate between Combinational and Sequential
Circuits with examples.
c. Design a code convertor to convert BCD to Excess 3
code.
d. .Design a Full Adder with truth table and Expressions
using two Half Adders and an OR gate
e. Explain the working of 2:4 Decoder with block
diagram, truth table, derive output expressions and
design the logic diagram.
f. Explain the working of Full Subtractor circuit with
Block Diagram, truth table, Output Expression and
design logic diagram. Develop Verilog Code for Full
Adder Circuit
