BQ24800

SLUSDO8A – MARCH 2020 – REVISED JANUARY 2025

BQ24800 SMBus 1- to 4-Cell Buck Battery Charge Controller

With Peak Power, Hybrid Power Boost and Battery Only Boost Modes
1 Features 2 Applications
• Hybrid Power Boost Mode to power up system • Notebook, ultrabook, detachable, and tablet PC
from adapter and battery together • Industrial and medical equipment
– Ultra-fast transient response of 150µs to enter • System with battery backup
Hybrid Power Boost Mode • Portable equipment
• Battery Only Boost Mode to support larger system
transients and extend battery run time
3 Description
• Peak power two-level input current limit to The BQ24800 device is a high-efficiency, synchronous
maximize the power from adapter and minimize buck multi-chemistry battery charger supporting 1-, 2-,
battery discharge 3-, or 4-series Li+ cells, or other battery chemistries
• Charge 1- to 4-cell battery pack from 4.5V to 24V up to 19.2V.
adapter
Through SMBus, a host microcontroller programs
• High accuracy power and current monitoring for
charge current, charge voltage, input current limit and
CPU throttling
discharge current limit with high regulation accuracies.
– Comprehensive PROCHOT profile
Additionally, the BQ24800 supports a two level input
– ± 2% Current monitor accuracy
current limit (Peak Power mode) to fully utilize the
– ± 5% System Power Monitor Accuracy (PMON)
adapter capabilities and reduce battery discharge.
• Automatic NMOS power source selection from
The BQ24800 provides adapter current (IADP),
adapter or battery
battery discharge current (IDCHG), and system power
– ACFET Fast turn on in 100µs when exiting (PMON) signals to the host microcontroller and
learn mode from battery removal outputs the PROCHOT signal to throttle back CPU
• Programmable input current, charge voltage, speed when needed.
charge and discharge current limit
– ±0.4% Charge voltage (16mV/step) The BQ24800 supports hybrid power boost mode to
– ±2% Input current (64mA/step) boost the battery voltage to supplement the adapter
– ±2% Charge current (64mA/step) when system power demand is temporarily higher
– ±2% Discharge current (512mA/step) than the adapter is able to provide. When the adapter
• High integration is not present, the BQ24800 supports battery only
boost mode to boost the battery voltage above the
– Battery LEARN function
minimum system operating voltage, providing more
– Battery present monitor
headroom to support system transients.
– Boost Mode indicator
– Loop compensation Device Information
– BTST Diode PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• Enhanced safety features for overvoltage BQ24800 RUY (WQFN 28) 4.00mm × 4.00mm
protection, overcurrent protection, battery, inductor,
and MOSFET short-circuit protection (1) For all available packages, see Section 12
Adapter
• Switching frequency: 300kHz, 400kHz, 600kHz, 4.5 ± 24 V RAC
Enhanced Safety:
OCP, OVP, FET Short System
and 800kHz
• Realtime system control on ILIM pin to limit charge
and discharge current NFET Driver
NFET
Driver

• 0.65mA Adapter standby quiescent current for Adapter Detection

Battery
BQ24800
Energy Star RSR
Pack
1S-4S
Hybrid Power Boost Charge
SMBUS Controller with Peak Power
Mode and Battery Only
Boost Mode
Host
IADPT, PROCHOT,
IDCHG, PMON

Integration:
Loop Compensation, Soft Start,
Comparator, BTST Diode

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7 Application and Implementation.................................. 46
2 Applications..................................................................... 1 7.1 Application Information............................................. 46
3 Description.......................................................................1 7.2 Typical Applications.................................................. 46
4 Pin Configuration and Functions...................................3 8 Power Supply Recommendations................................60
5 Specifications.................................................................. 6 9 Layout.............................................................................61
5.1 Absolute Maximum Ratings........................................ 6 9.1 Layout Guidelines..................................................... 61
5.2 ESD Ratings............................................................... 6 9.2 Layout Examples...................................................... 61
5.3 Recommended Operating Conditions.........................6 10 Device and Documentation Support..........................64
5.4 Thermal Information....................................................7 10.1 Third-Party Products Disclaimer............................. 64
5.5 Electrical Characteristics.............................................7 10.2 Documentation Support.......................................... 64
5.6 Timing Requirements................................................ 13 10.3 Receiving Notification of Documentation Updates..64
5.7 Typical Characteristics.............................................. 15 10.4 Support Resources................................................. 64
6 Detailed Description......................................................16 10.5 Trademarks............................................................. 64
6.1 Overview................................................................... 16 10.6 Electrostatic Discharge Caution..............................64
6.2 Functional Block Diagram......................................... 17 10.7 Glossary..................................................................64
6.3 Feature Description...................................................18 11 Revision History.......................................................... 64
6.4 Device Functional Modes..........................................25 12 Mechanical, Packaging, and Orderable
6.5 Programming............................................................ 31 Information.................................................................... 65
6.6 Register Maps...........................................................33

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4 Pin Configuration and Functions

LODRV
PHASE

HIDRV

REGN
BTST

GND
VCC
28

27

26

25

24

23

22
ACN 1 21 ILIM

ACP 2 20 SRP

CMSRC 3 19 SRN

ACDRV 4 Thermal 18 BATDRV

Pad
ACOK 5 17 BATSRC

ACDET 6 16 BST_STAT

IADP 7 15 BATPRES

10

11

12

13

14
8

9
IDCHG

PMON

PROCHOT

SDA

SCL

CMPIN

CMPOUT
Figure 4-1. RUY Package 28-Pin WQFN Top View

Table 4-1. Pin Functions

PIN
DESCRIPTION
NAME NO.
Input current sense resistor negative input. Place an optional 0.1-µF ceramic capacitor from ACN to GND for
ACN 1
common-mode filtering. Place a 0.1-µF ceramic capacitor from ACN to ACP to provide differential mode filtering.
Input current sense resistor positive input. Place a 0.1-µF ceramic capacitor from ACP to GND for common-
ACP 2
mode filtering. Place a 0.1-µF ceramic capacitor from ACN to ACP to provide differential-mode filtering.
ACDRV charge pump source input. Place a 4-kΩ resistor from CMSRC to the common source of ACFET (Q1)
CMSRC 3
and RBFET (Q2) to limit the inrush current on CMSRC pin.
Charge pump output to drive both adapter input N-channel MOSFET (ACFET) and reverse blocking N-channel
ACDRV 4 MOSFET (RBFET). ACDRV voltage is 6 V above CMSRC when ACOK is HIGH. Place a 4-kΩ resistor from
ACDRV to the gate of ACFET and RBFET limits the inrush current on ACDRV pin.
Active HIGH AC adapter detection open drain output. It is pulled HIGH to external pull-up supply rail by external
pull-up resistor when a valid adapter is present (ACDET above 2.4 V, VCC above UVLO but below ACOV and
ACOK 5
VCC above BAT). If any of the above conditions is not valid, ACOK is pulled LOW by internal MOSFET. Connect
a 10-kΩ pull-up resistor from ACOK to the pull-up supply rail.
Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter
input to ACDET pin to GND pin. When ACDET pin is above 0.6 V and VCC is above UVLO, REGN LDO
is present, ACOK comparator, input current buffer (IADP), discharge current buffer (IDCHG), independent
ACDET 6
comparator, and power monitor buffer (PMON) can be enabled with SMBus. When ACDET is above 2.4 V, and
VCC is above SRN but below ACOV, ACOK goes HIGH. Total resistance from Adapter to ACDET to GND varies
from 100 kΩ to 1 MΩ.
Buffered adapter current output. VIADP = 20 or 40 × (VACP – VACN) The ratio of 20x and 40x is selectable with
IADP 7 SMBus. Place 100-pF (or less) ceramic decoupling capacitor from IADP pin to GND. This pin can be floating if
this output is not in use.
Buffered discharge current. VIDCHG = 8 or 16 × (VSRN – VSRP) The ratio of 8x or 16x is selectable with SMBus.
IDCHG 8 Place 100-pF (or less) ceramic decoupling capacitor from IDSCHG pin to GND. This pin can be floating if this
output is not in use.
Buffered system power output. The output current is proportional to the total power from the adapter and battery
together. The ratio is selectable through SMBus. Place a resistor from PMON pin to GND to generate PMON
PMON 9
voltage. Place a 100-pF (or less) ceramic decoupling capacitor from PMON pin to GND. The pin voltage is
clamped to a maximum of 3.3 V.

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Table 4-1. Pin Functions (continued)

PIN
DESCRIPTION
NAME NO.
Active low, open-drain output of the processor hot indicator. The charger IC monitors events like adapter current,
PROCHOT 10 battery discharge current. After any event in the PROCHOT profile is triggered, signal is asserted low. Connect
a 500-Ω pull-up resistor from PROCHOT pin to the CPU Vtt supply rail (commonly 1.05 V.)
SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. SMBus
SDA 11 communication starts when VCC is above UVLO. Connect a 10-kΩ pull-up resistor according to SMBus
specifications.
SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. SMBus
SCL 12 communication starts when VCC is above UVLO. Connect a 10-kΩ pull-up resistor according to SMBus
specifications.
Input of independent comparator. Internal reference, output polarity and deglitch time are selectable by SMBus.
CMPIN 13 Place a resistor between CMPIN and CMPOUT to program hysteresis when the polarity is HIGH. If comparator
is not in use, CMPIN is tied to ground, and CMPOUT is left floating.
Open-drain output of independent comparator. Place 10-kΩ pull-up resistor from CMPOUT to pull-up supply
CMPOUT 14 rail. Comparator reference, output polarity and deglitch time are selectable by SMBus. The comparator is active
when REGN is available. If comparator is not in use, CMPIN is tied to ground, and CMPOUT is left floating.
Active low battery present input signal. Low indicates battery present, high indicates battery absent. The device
exits the LEARN function and turns on ACFET/RBFET if BATPRES pin is pulled HIGH. Note that ACFET/
BATPRES 15 RBFET is not driven on until BATFET has been turned off in order to protect against adapter to battery short.
Upon BATPRES from LOW to HIGH, battery charging and hybrid power boost mode are disabled. The host can
enable charging and hybrid power boost mode by write to REG0x14() and REG0x15() when BATPRES is HIGH.
Active low, open-drain output for hybrid power boost mode indication. It is pulled low when the IC is operating
BST_STAT 16 in either hybrid boost mode or battery only boost mode. Otherwise, it is pulled HIGH. Connect a 10-kΩ pull-up
resistor from BST_STAT pin to the pull-up supply rail.
Connect to the source of N-channel BATFET. BATDRV voltage is 6 V above BATSRC to turn on BATFET. Place
BATSRC 17
a 10-Ω resistor from BATSRC to the source of BATFET to limit the inrush current on BATSRC pin.
Charge pump output to drive N-channel MOSFET between battery and system (BATFET). BATDRV voltage is 6
BATDRV 18 V above BATSRC to turn on BATFET and power system from battery. BATDRV is shorted to BATSRC to turn off
BATFET. Place a 4-kΩ resistor from BATDRV to the gate of BATFET to limit the inrush current on BATDRV pin.
Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN
pin with a 0.1-µF ceramic capacitor to GND for common-mode filtering. Connect a 0.1-µF ceramic capacitor
SRN 19
from SRP to SRN to provide differential mode filtering. Place a 10-Ω resistor at the SRN pin to protect against
reverse-polarity battery insertion.
Charge current sense resistor positive input. Connect SRP pin with a 0.1-µF ceramic capacitor to GND for
SRP 20 common-mode filtering. Connect a 0.1-µF ceramic capacitor from SRP to SRN to provide differential mode
filtering. Place a 10-Ω resistor at the SRP pin to protect against reverse-polarity battery insertion.
Charge current and discharge current limit. VILIM = 20 × (VSRP – VSRN) for charge current and VILIM = 5 × (VSRN
– VSRP) for discharge current. Program ILIM voltage by connecting a resistor divider from system reference
ILIM 21
3.3-V rail to ILIM pin to GND pin. The lower of ILIM voltage and 0x14() (for charge) or 0x39 (for discharge)
reference sets actual regulation limit. Charging and Hybrid Boost are disabled if ILIM is pulled below 90 mV.
IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plane through
AGND 22
pad underneath IC.
LODRV 23 Low-side power MOSFET driver output. Connect to low-side N-channel MOSFET gate.
6-V linear regulator output supplied from VCC. The LDO is active when ACDET above 0.6 V, VCC above
REGN 24 UVLO. Connect a ≥ 2.2-µF 0603 ceramic capacitor from REGN to GND. The diode between REGN and BTST is
integrated.
High-side power MOSFET driver power supply. Connect a 47-nF capacitor from BTST to PHASE. The diode
BTST 25
between REGN and BTST is integrated inside the IC.
HIDRV 26 High-side power MOSFET driver output. Connect to the high side N-channel MOSFET gate.
PHASE 27 High-side power MOSFET driver source. Connect to the source of the high-side N-channel MOSFET.
Input supply to power the IC. Use 10-Ω resistor and 1-µF capacitor to ground as a low pass filter to limit inrush
current. A diode OR is connected to VCC. It powers te charger IC from input adapter or system rail if battery
VCC 28
only boost mode is supported. The diode OR instead powers the charger IC from adapter or battery rail if battery
only boost mode is not supported. Refer to Section 7 for examples with and without battery only boost support.

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Table 4-1. Pin Functions (continued)

PIN
DESCRIPTION
NAME NO.
Exposed pad beneath the IC. Analog ground and power ground star-connected only at the thermal pad plane.
Thermal
– Always solder the thermal pad to the board and have vias on the thermal pad plane connecting to analog
Pad
ground and power ground planes. It also serves as a thermal pad to dissipate heat.

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
SRN, SRP, ACN, ACP, CMSRC, VCC, BATSRC –0.3 30 V
PHASE –2 30 V
ACDET, SDA, SCL , LODRV, REGN, IADP, IDCHG, PMON, ILIM, ACOK,
Voltage –0.3 7 V
CMPIN, CMPOUT, BATPRES, BST_STAT
PROCHOT –0.3 5.7 V
BTST, HIDRV, ACDRV, BATDRV –0.3 36 V

Differential BTST-PHASE, HIDRV-PHASE, ACDRV-CMSRC, BATDRV-BATSRC –0.3 7 V

Voltage ACP-ACN, SRP-SRN –0.5 0.5 V
LODRV (2% duty cycle) –4 7 V

Transient HIDRV (2% duty cycle) –4 36 V

Voltage PHASE (2% duty cycle) –4 30 V
REGN (5 ms) –0.3 9 V
Output Sink
ACOK, BST_STAT, PROCHOT 6 mA
Current
TJ Junction temperature –40 150 °C
Tstg Storage temperature –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

5.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
±2000
JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC
±500
specification JESD22-C101, all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SRN, SRP, ACN, ACP, CMSRC, VCC, BATSRC 0 24 V
PHASE –2 24 V
ACDET, SDA, SCL , LODRV, REGN, IADP, IDCHG, PMON,
Voltage 0 6.5 V
ILIM, ACOK, CMPIN, CMPOUT, BATPRES, BST_STAT
/PROCHOT –0.3 5 V
BTST, HIDRV, ACDRV, BATDRV 0 30 V
Differential
ACP-ACN, SRP-SRN –0.4 0.4 V
Voltage
Output Sink
ACOK, BST_STAT, PROCHOT 6 mA
Current
TJ Junction temperature –40 125 °C
TA Storage temperature –40 85 °C

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5.4 Thermal Information

BQ24800
THERMAL METRIC(1) RUY (WQFN) UNIT
28 PINS
RθJA Junction-to-ambient thermal resistance (JEDEC(1)) 33.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 29.7 °C/W
RθJB Junction-to-board thermal resistance 6.5 °C/W
ΨJT Junction-to-top characterization parameter 0.3 °C/W
ΨJB Junction-to-board characterization parameter 6.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.3 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

5.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
VBAT = 16.8V, VCC disconnected to
5 µA
battery, REG0x12[15]=1
VBAT = 16.8V, VCC connected to
25 44 µA
battery, REG0x12[15]=1
VBAT = 16.8V, VCC connect to battery,
BATFET on, REG0x12[15]=0, REGN
on, Comparator and /PROCHOT 700 800 µA
enabled, PMON and boost mode
Current with battery only (TJ=0-85C), disabled
IQ_BAT (SRP, SRN, BATSRC, PHASE, VCC,
VBAT = 16.8V, VCC connect to
ACP, ACN)
battery, BATFET on, REG0x12[15]=0,
REGN on, Comparator, /PROCHOT 1100 1200 µA
and PMON enabled, boost mode
disabled
VBAT = 13.5V, VCC connect to battery,
BATFET on, REG0x12[15]=0, REGN
on, Comparator, /PROCHOT, PMON 1.8 mA
and boost mode enabled, but not
switching.
VVCC_ULVO<VVCC<VACOVP, VACDET>
0.65 0.80 mA
2.4V, charge disabled
VVCC_ULVO<VVCC<VACOVP, VACDET
1.60 3.00 mA
IQ_VBUS Quiescent input current (VBUS) >2.4V, charge enabled, no switching
VVCC_ULVO<VVCC<VACOVP, VACDET
>2.4V, charge enabled, switching, 10 mA
MOSFET Qg 4nC
REGN LDO
VREGN_REG REGN Regulator Voltage VVCC =10V, VACDET>Vwakeup_RISE 5.7 6.0 6.3 V
VREGN = 0V, VVCC > VUVLO, in charging
80 100 mA
mode
IREGN_LIM REGN Current Limit
VREGN = 0V, VVCC > VUVLO, Not in
13 mA
charging mode
VREGN_DROPOUT REGN Output Voltage Dropout VVCC = 5V, ILOAD=20mA 4.4 4.6 4.75 V
IREGN_TSHUT REGN Output under thermal shutdown VREGN=5V 13 23 mA
CREGN REGN Output Capacitor ILOAD = 100uA to 50mA 2 µF

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5.5 Electrical Characteristics (continued)

VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC / VBAT SUPPLY
VVBUS_OP VBUS operating range 4.5 24 V
VVCC_UVLOZ_RISE Input Undervoltage Rising Threshold VVCC rising 2.4 2.6 2.8 V
VVCC_UVLOZ_FALL Input Undervoltage Falling Threshold VVCC falling 2.2 2.4 2.6 V
VVCC_UVLOZ_HYS Input Undervoltage Falling Hysteresis VVCC falling 200 mV
Sleep Falling Threshold to turnoff
VSLEEP_FALL VCC ramps down to SRN –40 25 100 mV
ACFET
Sleep Rising Threshold to turnon
VSLEEP_RISE VCC ramps up above SRN 280 400 520 mV
ACFET
VWAKEUP_RISE WAKEUP Detect Rising Threshold VVCC>VVCC_UVLOZ, ACDET ramps up 0.57 0.80 V
VVCC>VVCC_UVLOZ, ACDET ramps
VWAKEUP_FALL WAKEUP Detect Falling Threshold 0.3 0.51 V
down
VACOK_RISE ACOK Rising Threshold VVCC>VVCC_UVLOZ, ACDET ramps up 2.375 2.4 2.43 V
VVCC>VVCC_UVLOZ, ACDET ramps
VACOK_FALL ACOK Falling Threshold 2.3 2.345 2.40 V
down
VACOV_RISE VCC Overvoltage Rising Threshold VCC ramps up 24 26 28 V
VACOV_FALL VCC Overvoltage Falling Threshold VCC ramps down 22 25 27 V
ACN to BAT Falling Threshold to turn
VACNSRN_FALL ACN ramps down towards SRN 120 200 280 mV
on BATFET
ACN to BAT Rising Threshold to turn
VACNSRN_RISE ACN ramps above SRN 220 290 360 mV
off BATFET
REG0x3B[15:14]=00 56 60 64 %
Battery Depletion Falling Threshold, as REG0x3B[15:14]=01 60 65 68 %
VBATDEPL_FALL percentage of voltage regulation limit.
Exit boost mode and learn mode. REG0x3B[15:14]=10 64 68 72 %
REG0x3B[15:14]=11 68 72 78 %
REG0x3B[15:14]=00 285 370 500 mV
REG0x3B[15:14]=01 300 390 530 mV
VBATDEPL_RISE Battery Depletion Rising Hysteresis
REG0x3B[15:14]=10 320 420 565 mV
REG0x3B[15:14]=11 340 445 600 mV
VBATLOWV_FALL Battery LOWV Falling Threshold SRN ramps down 2.3 2.5 2.8 V
VBATLOWV_RISE Battery LOWV Rising Threshold SRN ramps up 2.7 V
IBATLOWV Battery LOWV charge current limit RSR = 10 mΩ 500 mA
ACFET/RBFET and BATFET DRIVERS
IACFET ACDRV Charge Pump Current Limit VACDRV-VCMSRC=5V 40 60 µA
VDRV_ACFET Gate Drive Voltage on ACFET VACDRV-VCMSRC when VVCC>VUVLO 5.5 6.1 6.8 V
RACDRV_OFF ACDRV Turnoff Resistance 5.0 6.2 7.4 kΩ
Minimum Load between gate and
RACDRV_GS 500 kΩ
source
IBATFET BATDRV Charge Pump Current Limit VBATDRV-VBATSRC=5V 40 60 µA
VBATDRV-VBATSRC when
VDRV_BATFET Gate Drive Voltage on BATFET 5.5 6.1 6.8 V
VSRN>VBAT_UVLO
RBATDRV_OFF BATDRV Turnoff Resistance 5 6.2 7.4 kΩ
Minimum Load between gate and
RBATDRV_LOAD 500 kΩ
source

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5.5 Electrical Characteristics (continued)

VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BATTERY CHARGER
Typical charge voltage regulation
VREG_RANGE 1.024 19.2 V
range
VREG_STEP Typical charge voltage step 16 mV
ChargeVoltage() = 0x41A0 16.800 V
-10C-85C –0.4 0.4 %
-40C-125C –0.5 0.5 %
ChargeVoltage() = 0x3130 12.592 V
-10C-85C –0.4 0.4 %
-40C-125C –0.5 0.5 %
VREG_ACC Charge voltage accuracy
ChargeVoltage() = 0x20D0 8.400 V
-10C-85C –0.4 0.4 %
-40C-125C –0.6 0.6 %
ChargeVoltage() = 0x1060 4.192 V
-10C-85C –0.5 0.8 %
-40C-125C –0.7 0.8 %
Typical charge current regulation
ICHG_RANGE RSR = 10 mΩ 0 8128 mA
range
ICHG_STEP Typical charge current regulation step RSR = 10 mΩ 64 mA
4096 mA
ChargeCurrent() = 0x1000
–2 2 %
2048 mA
ChargeCurrent() = 0x0800
–3 3 %
1024 mA
ChargeCurrent() = 0x0400
-5 5 %
512 mA
ChargeCurrent() = 0x0200
Charge Current Regulation Accuracy –10 10 %
ICHG_ACC
(SRN>2V, RSR = 10 mΩ)
ChargeCurrent() = 0x0100 256 mA
ChargeVoltage() = 0x20D0, 0x3031,
–16 16 %
0x41A0
ChargeVoltage() = 0x1060 –20 20 %
192 mA
ChargeCurrent() = 0x00C0
–20 20 %
128 mA
ChargeCurrent() = 0x0080
–30 30 %
ILEAK_SRP-SRN SRP and SRN Leakage Mismatch –8 8 µA
INPUT CURRENT REGULATION
ILIM1_RANGE Typical input current regulation range RAC = 10 mΩ 0 8064 mA
ILIM1_STEP Typical Input Current Regulation Step RAC = 10 mΩ 64 mA

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5.5 Electrical Characteristics (continued)

VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
4096 mA
RAC = 10 mΩ, InputCurrent() = 0x1000
–2 2 %

Input Current Regulation Accuracy 2048 mA

ILIM1_ACC RAC = 10 mΩ, InputCurrent() = 0x0800
(0-85℃) –3 3 %
1024 mA
RAC = 10 mΩ, InputCurrent() = 0x0400
–5 5 %
ILEAK_ACP-ACN ACP and ACN Leakage Mismatch –5 5 µA
PEAK POWER MODE
REG0x38[15:14]= 00 0.59 1.00 mS
REG0x38[15:14]= 01 1.3 2.0 mS
TOVLD Peak Power Overload Period
REG0x38[15:14]= 10 3.1 5.0 mS
REG0x38[15:14]= 11 7.0 10.1 mS
REG0x38[9:8]= 00 17.0 20 23.4 mS
REG0x38[9:8]= 01 34 40 46 mS
TMAX Peak Power Cycle Period
REG0x38[9:8]= 10 68 80 92 mS
REG0x38[9:8]= 11 935 1100 1265 mS

InputCurrent() = 0x1000, 6144 mA

REG0x3C[14:11]=1001 97 101 %

InputCurrent() = 0x0800, 3072 mA

REG0x3C[14:11]=1001 96 102 %
ILIM2_ACC Peak Current Limit Accuracy
InputCurrent() = 0x0400, 1536 mA
REG0x3C[14:11]=1001 99 109 %

InputCurrent() = 0x0200, 768 mA

REG0x3C[14:11]=1001 100 107 114 %
BATTERY DISCHARGE CURRENT REGULATION (HYBRID POWER BOOST MODE)
VIDCHG_RNG DIscharge Current Regulation Range RSR = 10 mΩ 0 32256 mA
IIDCHG_STEP Discahrge Current Regulation Step RSR = 10 mΩ 512 mA
8192 mA
DischargeCurrent() = 0x2000
–2 2 %
4096 mA
DischargeCurrent() = 0x1000
–3 3 %

Discharge Current Regulation 2048 mA

IDCHG_ACC DischargeCurrent() = 0x0800
Accuracy –5 5 %
1024 mA
DischargeCurrent() = 0x0400
–8 8 %
512 mA
DischargeCurrent() = 0x0200
–10 10 %
BATTERY ONLY BOOST MODE
Minimum System Voltage Range
VSYSMIN_RNG (System Voltage Regulation is 1.5 or 5.632 13.568 V
2.3V higher)
Typical System Voltage Regulation
VSYSMIN_STEP 256 mV
Step

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5.5 Electrical Characteristics (continued)

VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
9.728 V
VSYSMIN() = 0x2600
–2.2 2.8 %
VSYSMIN_ACC System Voltage Regulation Accuracy
6.656 V
VSYSMIN() = 0x1980
–2.2 2.8 %
System Voltage Falling Threshold to
VSYSMIN_ENTER As percentage of VSYSMIN 100 %
enter Battery Boost
CURRENT SENSE AMPLIFIER
VIADP IADP Output Voltage Range 0 3.3 V
IIADP IADP Output Current 1 mA
AIADP IADP Sense Amplifier Gain VIADP / (VACP- VACN), REG0x12[4]=0 20 V/V
VACP-VACN = 40mV –2 2 %
VACP-VACN = 20mV –4 4 %

Current Sense Amplifier Gain VACP-VACN = 10mV –7 7 %

VIADP_ACC
Accuracy VACP-VACN = 5mV –20 20 %
VACP-VACN = 2.5mV –30 30 %
VACP-VACN = 1.5mV –40 40 %
VIADP_CLAMP IADP Clamp Voltage 3 3.3 V
CIADP IADP Output Load Capacitance With 0 to 1mA load 100 pF
VIDCHG IDCHG Output Voltage Range 0 3.3 V
IIDCHG IDCHG Output Current 0 1 mA
AIDCHG Current Sense Amplifier Gain VIDCHG / (VSRN-VSRP), REG0x12[3]=1 20 V/V
VSRN-VSRP = 40mV –5 5 %
VSRN-VSRP = 20mV –9 9 %
VIDCHG_ACC Current Sense Output Accuracy
VSRN-VSRP = 10mV –17 17 %
VSRN-VSRP = 5mV –34 34 %
VIDCHG_CLAMP IDCHG Clamp Voltage 3 3.3 V
CIDCHG IDCHG Output Load Capacitance With 0 to 1mA load 100 pF
VPMON PMON Output Voltage Range 0 3.3 V
IPMON PMON Output Current 0 100 µA
APMON PMON System Gain IPMON / (PIN+ PBAT), REG0x3B[9]=1 1 µA/W
Adapter Only with System Power =
–4 4 %
19.5V/45W
Adapter Only with System Power =
–6 6 %
12V/24W
Adapter Only with System Power =
–10 10 %
PMON Gain Accuracy 5V/9W
VPMON_ACC
(REG0x3B[9]=1) Battery Only with System Power
–4.5 4.5 %
11V/44W
Battery Only with System Power 7.4V/
–7 7 %
29.8W
Battery Only with System Power 3.7V/
–10 10 %
14.4W
VPMON_CLAMP PMON Clamp Voltage 3 3.3 V
INPUT OVER-CURRENT PROTECTION
Rising Threshold w.r.t. ILIM2 current
VACOC REG0x37[9]=1 190 200 215 %
limit

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5.5 Electrical Characteristics (continued)

VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VACOC_CLAMP ACOC Threshold Clamp Low Value VACP-VACN 50 mV
VACOC_CLAMP ACOC Threshold Clamp High Value VACP-VACN 190 mV
BATTERY OVER-VOLTAGE PROTECTION
Overvoltage Rising Threshold as
SRN ramps up 103 104 105 %
percentage of VBAT_REG
VBAT_OVP
Overvoltage Falling Threshold as
SRN ramps down 101 102 103 %
percentage of VBAT_REG
VSRN>6V 6 mA
IBAT_OVP Discharge Resistor on SRP
VSRN=4.5V 2 mA
CONVERTER PROTECTION
ChargeCurrent()=0x0xxxH 54 60 66 mV
Cycle by cycle Over-Current Limit,
VOCP_LIMIT measured voltage between SRP and ChargeCurrent()=0x1000H-0x17C0H 80 90 100 mV
SRN.
ChargeCurrent()=0x1800H-0x1FC0H 110 120 130 mV
Cycle by cycle Under-Current Falling
VUCP_FALL SRP ramps down towards SRN 1.0 5 9.00 mV
Threshold
Light Load Falling Threshold in Buck
VLL_FALL_BUCK SRP ramps down towards SRN 1.25 mV
Mode
Light Load Rising Threshold in Buck
VLL_RISE_BUCK SRP ramps above SRN 2.5 mV
Mode
Light Load Falling Threshold in Boost
VLL_FALL_BOOST SRN ramps down towards SRP 2.5 mV
Mode
Light Load Rising Threshold in Boost
VLL_RISE_BOOST SRN ramps above SRP 5.0 mV
Mode
INDUCTOR SHORT, MOSFET SHORT PROTECTION
VIFAULT_HI_RISE ACN to PH Rising Threshold REG0x37[7] = 0 450 750 1200 mV
VIFAULT_LO_RISE PH to GND Rising Threshold REG0x37[6] = 1 180 250 340 mV
SWITCHING CONVERTER
REG0x12[9:8] = 00 510 600 690 KHz
REG0x12[9:8] = 01 680 800 920 KHz
FSW PWM switching frequency
REG0x12[9:8] = 10 255 300 345 KHz
REG0x12[9:8] = 11 340 400 460 KHz
High-side Driver (HSD) Turnon
RDS_HI_ON VBTST – VPH = 5.5 V 6 10 Ω
Resistance
RDS_HI_OFF High-side Driver Turnoff Resistance VBTST – VPH = 5.5 V 0.9 1.4 Ω
Bootstrap refresh comparator VBTST – VPH when LSFET refresh
VBTST_REFRESH 3.85 4.3 4.7 V
threshold pulse is requested, VBUS = 5V
Low-side Driver (LSD) Turnon
RDS_LO_ON 7.5 12 Ω
Resistance
RDS_LO_OFF Low-side Driver Turnoff Resistance 0.75 1.25 Ω
ISTEP Soft-start Step Size 64 mA
tSTEP Soft-start Step Time 400 us
THERMAL SHUTDOWN
TSHUT_RISE Thermal Shutdown Rising threshold Temperature Increasing 155 °C
TSHUT_FALL Thermal Shutdown Falling threshold Temperature Decreasing 135 °C

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5.5 Electrical Characteristics (continued)

VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PROCHOT COMPARATORS
REG0x3C[14:11]=1001, as percentage
VICRIT ICRIT comparator threshold 162 165 168 %
of input current limit 4096mA
as percentage of input current limit
107 110 112 %
4096mA, 0x3F()=0x1000, 0x3C [0] = 0
VINOM INOM Comparator Threshold
as percentage of input current limit
104 106 108 %
4096mA, 0x3F()=0x1000, 0x3C [0] = 1
REG0x3D[15:11]=10000, as voltage
160 163.84 167 mV
between SRN and SRP
VIDCHG IDCHG comparator threshold
REG0x3D[15:11]=00100, as voltage
38 40.96 44 mV
between SRN and SRP
REG0x3C[7:6]=00 5.71 5.75 5.95 V
REG0x3C[7:6]=01 5.88 6.00 6.12 V
VVBATT VBATT Comparator Threshold
REG0x3C[7:6]=10 6.22 6.25 6.46 V
REG0x3C[7:6]=11 6.48 6.50 6.72 V
MISC COMPARATORS
VCMP_OS Independent comparator Input Offset –4 4 mV
Independent comparator Input
VCMP_CM 0 6.5 V
Common-mode

Independent comparator Reference REG0x3B[7]=0 2.28 2.3 2.32 V

VCMP_REF
Voltage (CMPIN falling) REG0x3B[7]=1 1.18 1.2 1.22 V
Independent comparator Reference
VCMP_RISE_HYST REG0x3B[6]=0 100 mV
Hysteresis
ILIM as Converter Enable Falling
VILIM_FALL VILIM falling 60 75 90 mV
Threshold
ILIM as Converter Enable Rising
VILIM_RISE VILIM rising 90 105 120 mV
Threshold
ANALOG AND DIGITAL I/O
IAIN_ LEAK Input bias current V = 7V –1 1 µA
VIN_ LO Input high threshold (SDA, SCL) SDA and SCL pins 0.8 V
VIN_ HI Input low threshold (SDA, SCL) SDA and SCL pins 2.1 V
IDIN_ LEAK Input bias current (SDA, SCL) V = 7V, SDA and SCL pins –1 1 µA
Output Saturation Voltage (ACOK,
VOUT_LO 5 mA drain current 500 mV
SDA, CMPOUT, /BST_STAT)
Leakage Current (ACOK, SDA,
IOUT_LEAK V = 7V –1 1 uA
CMPOUT, /BST_STAT)
Output Saturation Voltage (/
VOUT_LO_PH 17mA drain current 300 mV
PROCHOT)
IOUT_LEAK_PH Leakage Current (/PROCHOT) V = 5.5V –1 1 uA

5.6 Timing Requirements

MIN NOM MAX UNIT
COMPARATOR DEGLITCH
ACOK rising deglitch to turnon ACFET, REG0x12[12]=0 100 150 200 ms
tACOK_RISE_DEG
ACOK rising deglitch to turnon ACFET, REG0x12[12]=1 0.9 1.3 1.7 s
tACOK_FALL_DEG ACOK falling deglitch to turnoff ACFET 3 µs
tACOC_DEG Deglitch time to latch off ACFET 4.5 6 7.5 ms

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5.6 Timing Requirements (continued)

MIN NOM MAX UNIT
Battery depletion falling threshold to turnoff BATFET and turnon
tBATDEPL_FALL_DEG 2 µs
ACFET in Learn mode.
PWM DRIVER TIMING
tDEADTIME_RISE Driver dead time from low-side to high-side 20 ns
tDEADTIME_FALL Driver deadtime from high-side to low-side 20 ns
SMBus TIMING CHARACTERISTICS
tR SCL/SDA rise time 300 ns
tF SCL/SDA fall time 300 ns
tW(H) SCL pulse width high 0.6 µs
tW(L) SCL pulse width low 1.3 µs
tSU(STA) Setup time for START condition 0.6 µs
tH(STA) Start condition hold time after which first clock pulse is generated 0.6 µs
tSU(DAT) Data setup time 100 ns
tH(DAT) Data hold time 0 ns
tSU(STOP) Set up time for STOP condition 0.6 µs
t(BUF) Bus free time between START and STOP conditions 1.3 µs
FS(CL) Clock frequency 10 400 kHz
HOST COMMUNICATION FAILURE
tTIMEOUT SMBus bus release timeout(1) 25 35 ms
tBOOT Deglitch for watchdog reset signal 10 ms
Watchdog timeout period, REG0x12[14:13]=01 4 5 6 s
tWDI Watchdog timeout period, REG0x12[14:13]=10 70 88 105 s
Watchdog timeout period, REG0x12[14:13]=11 140 175 210 s

Figure 5-1. SMBus Communication Timing Waveforms

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5.7 Typical Characteristics

100% 100%
VBAT = 14.8 V VBAT = 3.7 V
VBAT = 11.1 V VBAT = 7.4 V
98% VBAT = 7.4 V 98%

96% 96%

Efficiency
Efficiency

94% 94%

92% 92%

90% 90%

88% 88%
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
Charge Current (A) Charge Current (A) D002
D001

VIN = 20 V VIN = 12 V
Figure 5-2. Efficiency During Charging Figure 5-3. Efficiency During Charging
100% 100%
VBAT = 3.7 V
95%
98%
90%
96%
85%
Efficiency
Efficiency

94% 80%

75%
92%
70% VBAT = 3.7 V
90% VBAT = 7.4 V
65% VBAT = 11.1 V
VBAT = 14.8 V
88% 60%
0 1 2 3 4 5 6 7 8 0 2 4 6 8 10
Charge Current (A) D003
Discharge Current (A) D004

VIN = 5 V VIN = 20 V
Figure 5-4. Efficiency During Charging Figure 5-5. Efficiency During Hybrid Boost

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6 Detailed Description
6.1 Overview
The BQ24800 is a 1-4 cell buck battery charge controller with power selection for space-constrained, multi-
chemistry portable applications such as notebook and detachable ultrabook. It supports wide input range of input
sources from 4.5 V to 24 V, and 1-4 cell battery for a versatile solution. As a buck charger, it requires an adapter
voltage greater than the maximum battery voltage.
The BQ24800 supports automatic system power source selection with separate drivers for n-channel MOSFETS
on the adapter side and battery side.
The BQ24800 features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter over-
loading. During battery charging, as the system power increases, the charging current will reduce to maintain
total input current below adapter rating. If system power demand temporarily exceeds the adapter rating, the
BQ24800 supports hybrid power boost mode (previously called "turbo boost mode") to boost the battery voltage
through the switching regulator in order to provide supplement current.
Most adapters have the ability to maintain a current level above their nominal rating for a milliseconds or even
tens of milliseconds. The BQ24800 has two level input current DPM, also known as Peak Power mode, to allow
the user to extend the input current DPM to support a higher input current for a programmable overload time,
then allow the adapter to recover by fixing the input current limit at the nominal rating. This allows full utilization
of the adapter capabilities to reduce battery discharge.
When powering the system directly from the battery without an adapter, the battery voltage may fall below the
level required to maintain the system. BQ24800 provides the battery only boost mode to boost the system
voltage above the battery voltage, allowing the system to utilize the remaining battery power for extended battery
life.
The BQ24800 closely monitors system power (PMON), input current (IADP) and battery discharge current
(IDCHG) with highly accurate current sense amplifiers. If current is too high, adapter or battery is removed, a
PROCHOT signal is asserted to CPU so that the CPU optimizes its performance to the power available to the
system.
The SMBus controls input current, charge current and charge voltage registers with high resolution, high
accuracy regulation limits. It also sets the PROCHOT timing and threshold profile to meet system requirements.

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6.2 Functional Block Diagram

3.2V LPM EN_REGN

+ UVLO
VCC 28 ±
Qual_REGN
ACOK_DRV 5 ACOK
AC_GOOD Deglitch
ACDET 6 + Wakeup
0.6V
±
15 BATPRES
+ ADPT_PRES ACDRV
2.4V
± Charge Pump
SYS2AC
+ ACOV ACOC 4 ACDRV
26V
± AC_CMSRC
3 CMSRC
ACN
VCC*IADPT + + ACN_SRN + AC_CMSRC
PMON 9 SRN+200mV Selection 5.7V
SRN*IBATT ± ±
Logic
VSysMin+1.5V ACOK_DRV
+ BATDRV
EN_LEARN
Charge Pump
±
AC_FETOFF
SYS2BAT
EN_FET_LATCHOFF 18 BATDRV
IADP 7
Type-III Compensation 17 BATSRC
ACP 2 and Ramp Generator Watchdog
+ Timer
20x +
± +
ACN 1 ± +
±
25 BTST
±
+
+ FDPM ±
TOVLD
VREF_ILIM1 26 HIDRV
± TMAX CHG_INHIBIT
EN_PKPWR VREF_ILIM1 EN_BOOST
VREF_ILIM2 EN_BATT_BOOST 27 PHASE
FDPM EN_REGN
IDCHG 8
Tj + TSHUT
+ 155 degC REGN
± 24 REGN
SRP-SRN LDO
± + CHG_OCP
+ 120 mV
4x + ±
± 5 mV 23 LODRV
VREF_IDCHG +
± CHG_UCP
SRP 20 SRP-SRN
+ ±
16x +
1.25 mV PP PGND
± VREF_ICHG + Light_Load
SRN 19 ±
SRP-SRN
±
ACP-ACN
PWM
+
+ ACOC Driver 16 BST_STAT
ILIM 21 ± 2xILIM2 Logic
±
VREF_VREG 4.3V
+ +
Refresh
BTST-PH
± ± ACOK
SRN
+
BATOVP BATPRES
CHG_INHIBIT 104% VREF_VREG ACP-ACN PROCHOT
±
SRN Detect 10 PROCHOT
VREF_VREG 2.5 V
+ BATLOWV
VREF_ICHG IDCHG
SRN
± CMPOUT
VREF_IDCHG VCC
+
VREF_ILIM1 VCC_SRN
SCL 12 SRN + 275 mV
±
SMBUS VREF_ILIM2 VREF_CMP
SRN +
Interface EN_PKPWR + VBATT_DEPL
SDA 11 72% VREF_VREG ± 13 CMPIN
EN_BOOST ±
ILIM + CHG/
EN_BATT_BOOST DCHG_EN
120 mV ± 14 CMPOUT
FET_LATCHOFF_EN
EN_LEARN VSysMin
+ VBOOST 22 AGND
EN_SHIP ACN ±

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6.3 Feature Description

6.3.1 Device Power Up
The BQ24800 gets power from adapter or battery. A diode-OR is placed to power VCC from adapter or system
rail if battery only boost is supported. This configuration will power up the IC from a battery attach without
adapter present via the body diode of the BATFET. If battery only boost is not supported, a diode-OR is placed
to power VCC from adapter or directly from battery. After VCC is above its UVLO threshold, the device wakes up
from power-on-reset (POR) and starts communication. Refer to Section 7 for examples with and without battery
only boost support.
6.3.1.1 Battery Only
When VCC voltage is above UVLO, BQ24800 powers up to turn on BATFET and starts SMBus communication.
By default, the BQ24800 stays in low power mode (REG0x12[15] = 1) with lowest quiescent current. When
REG0x12[15] is set to 0, the device enters performance mode. User can enable IDCHG buffer, PMON,
PROCHOT, battery only boost mode or comparator through SMBus. REGN LDO is enabled (except when
only IDCHG buffer) for accurate reference during PMON, PROCHOT, battery only boost mode and comparator
operations.
6.3.1.2 Adapter Detect and ACOK Output
An external resistor divider attenuates the adapter voltage before it goes to ACDET. If the battery boost mode
is not used, the adapter detect threshold must be programmed to a value greater than the maximum battery
voltage, but lower than the minimum allowed adapter voltage. If the battery only boost mode is used, the adapter
detect threshold must instead be programmed to a value that is higher than the system regulation voltage
programmed in REG0x38[5] and REG0x3E. When ACDET is above 0.6 V, all bias circuits are enabled.
The open drain ACOK output is pulled to external rail under the following conditions:
• VUVLO < VVCC < VACOV
• VACDET > 2.4 V
• VVCC – VSRN > VSLEEP
ACOK HIGH indicates adapter is detected, or adapter present. The REG0x37[11] tracks the status of ACOK pin.
ACOK deglitch time is 150 ms at the first time adapter plug-in if REG0x37[12] has not been overwritten since
power-on reset. Once the register has been written to, and for all connections after the first connection, the value
set by REG0x37[12] (150 ms or 1.3 sec) is used. Since the POR default of this register is 1.3 sec, if it is not
overwritten, the first adapter plugin will have an ACOK deglitch time of 150 ms and all subsequent plugins will
have an ACOK deglitch time of 1.3 sec.
6.3.1.2.1 Adapter Overvoltage (ACOV)
When the VCC pin voltage is higher than 26 V, it is considered adapter over voltage. ACOK is pulled low, and
charging is disabled. ACFET/RBFET are turned off to disconnect the high voltage adapter from the system
during ACOV. BATFET is turned on if turn-on conditions are valid.
When VCC voltage falls below 24 V, it is considered a valid adapter voltage. ACOK is pulled high by an external
pull-up resistor. BATFET is turned off and ACFET and RBFET are turned on to power the system from the
adapter.
6.3.1.3 REGN LDO
REGN LDO functions as an internal reference. When the adapter is present (ACDET pin is above 0.6 V), the
REGN LDO is always enabled. When the adapter is removed (ACDET pin is less than 0.6 V), and low power
mode is enabled (REG12[15] = 1), the REGN LDO is disabled regardless of other register bits setting. When the
adapter is removed and low power mode is disabled (REG0x12[15] = 0), REGN LDO is enabled when any of the
below functions is enabled:
• Power monitor function PMON
• Processor hot function PROCHOT
• Independent comparator

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6.3.2 System Power Selection

The BQ24800 device automatically switches adapter or battery power to system. An automatic break-before-
make logic prevents shoot-through currents when the selectors switch. The system is powered across the body
diode of the BATFET during the brief period between the first selector turning off and the second turning on.
The ACDRV drives a pair of common-source (CMSRC) N-channel power MOSFETs (ACFET and RBFET)
between the adapter and ACP. The ACFET separates adapter from system and battery, and limits inrush current
when the adapter is plugged in by controlling the ACFET turn-on time. Additionally, it protects the adapter when
the system or battery is shorted. The RBFET provides negative input voltage protection and battery discharge
protection when adapter is shorted to ground, and minimizes system power dissipation with its low RDS(on)
compared to a Schottky diode.
When the voltage measured at the ACDET pin is less than 2.4 V, it is determined that a valid adapter is not
present. Under this condition, ACDRV is pulled to CMSRC to keep ACFET and RBFET off, isolating the adapter
input from the system rail. BATDRV stays at VBATSRC + 6 V to connect battery to system if all of the following
conditions are valid:
• VVCC > VUVLO
• VACN < VSRN + 200 mV
• ACFET/RBFET off
When the voltage measured at the ACDET pin is greater than 2.4 V, a valid adapter is determined to be present.
Under this condition, the ACDRV is driven above CMSRC to turn ACFET and RBFET on, and the system power
source switches from battery to adapter if all of the following conditions are valid:
• ACOK high with all conditions in Section 6.3.1.2 valid.
• Not in LEARN mode
• In LEARN mode and VSRN < battery depletion threshold
The gate drive voltage on ACFET and RBFET is VCMSRC + 6 V. If the ACFET/RBFET have been turned on for 20
ms, and the voltage across gate and source is still less than 5.7 V, ACFET and RBFET are turned off. After 1.3
sec delay, it resumes turning on ACFET and RBFET. If such a failure is detected seven times within 90 seconds,
ACFET/RBFET are latched off and an adapter removal is required to force ACDET < 0.6 V to remove the latch.
After the latch is reset, ACFET/RBFET can be turned on again.
To turn off ACFET/RBFET, one of the following conditions must be valid:
• In LEARN mode and VSRN is above battery depletion threshold;
• ACOK low
To limit the adapter inrush current during ACFET turn-on, the Cgs and Cgd external capacitor of ACFET must be
carefully selected following the guidelines below:
• Minimize total capacitance on system
• Cgs should be 40× or higher than Cgd to avoid ACFET false turn on during adapter hot plug-in
• Fully turn on ACFET within 20 ms, otherwise, charger IC will consider turn-on failure
• Check with MOSFET vendor on peak current rating
• Place 4-kΩ resistor in series with ACDRV, CMSRC, and BATDRV pin to limit inrush current
6.3.3 Current and Power Monitor
6.3.3.1 High Accuracy Current Sense Amplifier (IADP and IDCHG)
As an industry standard, a high-accuracy current sense amplifiers (CSA) are used to monitor the input current
(IADP) and the discharge current (IDCHG). IADP voltage is 20X or 40X the differential voltage across ACP and
ACN. IDCHG voltage is 8X or 16X the differential voltage across SRN and SRP. After VCC is above UVLO and
ACDET is above 0.6 V, IADP output becomes valid. To lower the voltage on current monitoring, a resistor divider
from CSA output to GND can be used and accuracy over temperature can still be achieved.
• VIADP = 20 or 40 × (VACP – VACN) IADP gain is set in REG0x12[4] with default 20x.
• VIDCHG = 8 or 16 × (VSRN – VSRP) IDCHG gain is set in REG0x12[3] with default 16x.

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A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise.
An additional RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional
response delay. The CSA output voltage is clamped at 3.3 V. To lower the voltage on current monitoring, a
resistor divider from CSA output to GND can be used and accuracy over temperature can still be achieved.
6.3.3.2 High Accuracy Power Sense Amplifier (PMON)
The BQ24800 device monitors the power used by the system by adding the power discharged from the battery
to the power pulled from the adapter. The PMON pin is a current source with output current proportional to
system power. The PMON output current is calculated in Equation 1. APMON is the ratio of PMON pin output
current to system power. It can be set in REG0x3B[9] with default 1 µA/W (REG0x3B[9] = 1) for 10-mΩ RAC and
RSR sense resistors. This gain scales with the value of the sense resistors used so that 20-mΩ RAC and RSR
instead have a gain of 2 µA/W with the same setting (REG0x3B[9] = 1).

IPMON = APMON (VIN x IIN + VBAT x IBAT) ; IBAT > 0 during discharge; IBAT < 0 during charge (1)

The BQ24800 device allows an input sense resistor that is 2x or 1/2x of charge sense resistor by setting
REG0x3B[13:12] to 01 or 10, respectively. With REG0x3B[13:12] set to 01, the current measurement across
RSR is internally doubled so that a 20-mΩ RAC and 10-mΩ RSR will have the same output at the PMON pin
as a 20-mΩ RAC and 20-mΩ RSR will have with REG0x3B[13:12] set to 00. With REG0x3B[13:12] set to 10,
the current measurement across RAC is doubled instead. APMON as a function of RAC, RSR, REG0x3B[9] and
REG0x3B[13:12] is summarized in Table 6-1. The REG0x3B[13:12] sense ratio must be set as shown in the
table for each RAC and RSR combination. The REG0x3B[9] PMON gain may be set to either 0 or 1. The resultant
APMON for each setting is shown.
Table 6-1. PMON Output Current Gain by Setting
REG0x3B[13:12] REG0x3B[9]
RAC RSR APMON
RAC and RSR Ratio PMON Gain
5 mΩ 5 mΩ 00 = RAC and RSR 1:1 0 = 0.25 µA/W for 10 mΩ 0.125 µA/W
5 mΩ 5 mΩ 00 = RAC and RSR 1:1 1 = 1 µA/W for 10 mΩ 0.5 µA/W
10 mΩ 5 mΩ 01 = RAC and RSR 2:1 0 = 0.25 µA/W for 10 mΩ 0.25 µA/W
10 mΩ 5 mΩ 01 = RAC and RSR 2:1 1 = 1 µA/W for 10 mΩ 1 µA/W
5 mΩ 10 mΩ 10 = RAC and RSR 1:2 0 = 0.25 µA/W for 10 mΩ 0.25 µA/W
5 mΩ 10 mΩ 10 = RAC and RSR 1:2 1 = 1 µA/W for 10 mΩ 1 µA/W
10 mΩ 10 mΩ 00 = RAC and RSR 1:1 0 = 0.25 µA/W for 10 mΩ 0.25 µA/W
10 mΩ 10 mΩ 00 = RAC and RSR 1:1 1 = 1 µA/W for 10 mΩ 1 µA/W
20 mΩ 10 mΩ 01 = RAC and RSR 2:1 0 = 0.25 µA/W for 10 mΩ 0.5 µA/W
20 mΩ 10 mΩ 01 = RAC and RSR 2:1 1 = 1 µA/W for 10 mΩ 2 µA/W
10 mΩ 20 mΩ 10 = RAC and RSR 1:2 0 = 0.25 µA/W for 10 mΩ 0.5 µA/W
10 mΩ 20 mΩ 10 = RAC and RSR 1:2 1 = 1 µA/W for 10 mΩ 2 µA/W
20 mΩ 20 mΩ 00 = RAC and RSR 1:1 0 = 0.25 µA/W for 10 mΩ 0.5 µA/W
20 mΩ 20 mΩ 00 = RAC and RSR 1:1 1 = 1 µA/W for 10 mΩ 2 µA/W

A resistor is connected on the PMON pin to convert output current to output voltage with desired scaling. A
maximum 100-pF capacitor to GND is recommended as close as possible to the PMON pin for decoupling
high-frequency noise. An additional RC filter is optional, if additional filtering is desired. Note that adding filtering
also adds additional response delay. The PMON output voltage is clamped to 3.3 V.
6.3.4 Processor Hot Indication for CPU Throttling
When CPU is running turbo mode, the peak power may exceed total available power from adapter and battery.
The BQ24800 provides the PROCHOT output to signal the CPU that an overload condition has occurred. When
adapter or battery discharge current exceeds the allowed threshold or system voltage drops, this indicates an
overload condition has occurred. Likewise, adapter or battery removal may result in insufficient power for the

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CPU. The processor hot function in the BQ24800 monitors these events, and optionally asserts the PROCHOT
signal when they occur.
The PROCHOT triggering events are:
• ICRIT: adapter peak current (110% of ILIM2)
• INOM: adapter average current (110% of ILIM1)
• IDCHG: battery discharge current
• VBATT: battery voltage on SRP
• ACOK: upon adapter removal (ACOK pin HIGH to LOW)
• BATPRES: upon battery removal ( BATPRES pin LOW to HIGH)
• CMPOUT: Independent comparator output (CMPOUT pin HIGH to LOW)
• Adapter insertion while battery only boost is active (triggers ICRIT event if enabled.)
The threshold of ICRIT, IDCHG or VBATT, and the deglitch time of ICRIT, INOM, IDCHG or CMPOUT are
programmable through SMBus. Each triggering event can be individually enabled in REG0x3D[6:0]. The ICRIT
threshold is 110% of the ILIM2 value as set in REG0x3C[14:11]. When ILIM2 is set to a low value, and particularly
when the ICRIT deglitch is set to one of the faster values of 10 or 100 uS, the ICRIT PROCHOTmay trip
upon adapter insertion due to inrush current. The exact values which may cause this depend on the amount of
capacitance on the system rail and the voltage difference between the adapter and battery. Larger capacitance
will lead to larger inrush current, as will larger voltage difference between the adapter and battery. This is most
likely to be a concern if the ILIM2 value is set to 512 mA or less.
ICRIT
IADP

Adjustable
Deglitch

INOM 1.05 V
IDCHG
50W
PROCHOT
Ref_DCHG 10-ms
Debounce
Ref

VSRP ≥10 ms < 0.3 V

20-ms
Deglitch

BATPRES ACOK
(One shot on rising edge) (One shot on falling edge)
CMPOUT

Figure 6-1. PROCHOT Profile

When any event in PROCHOT profile is triggered, PROCHOT is asserted low for minimum 10 ms (default
REG0x3C[4:3]=10). At the end of the 10 ms, if the PROCHOT event is still active, the pulse gets extended.

If multiple PROCHOT events occur while the PROCHOT signal remains asserted low, all of the triggering events
are saved in status register REG0x3A[6:0]. If the PROCHOT signal deasserts and then is reasserted, the status
register will be cleared upon the new high to low transition of the PROCHOT signal so that only the newly
detected event is read. Whenever the host reads REG0x3A, this will also clear all of the flagged events from that
register after they are read.
6.3.5 Input Current Dynamic Power Management
The BQ24800 employs dynamic power management to reduce charging current to maintain a maximum adapter
current ILIM1, set in REG0x3F(). If the system current requirement exceeds ILIM1, the charger will enter peak

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power mode (if enabled) as described in Section 6.3.6. If peak power mode is not enabled, the charger will
instead enter hybrid boost (if enabled and all required conditions are met) as described in Section 6.4.2.
If neither peak power mode nor hybrid boost is entered, the adapter current may exceed ILIM1, potentially
generating an INOM or ICRIT PROCHOT or ACOC event.
The BQ24800 features improved precision in both ILIM1 and the FDPM_RISE threshold used to enter
hybrid boost mode. REG0x3F() allows setting ILIM1 in increments of 64 mA, and REG0x37[5] allows setting
FDPM_RISE to either 104% or 107% of the ILIM1 value.
The improved precision of ILIM1 and FDPM_RISE allows setting the following combinations of current limit and
hybrid boost threshold. These are summarized in Table 6-2.
• REG0x3F() may be set divisible by 128 mA (bit [6] = 0) with FDPM_RISE threshold of 107% for all ILIM1
values. This is the highest precision offered by previous devices in the family.
• Additionally, REG0x3F() may be set divisible by 128 mA (bit [6] = 0) with tighter FDPM_RISE threshold of
104% for all ILIM1 values greater than 2.5 A. The first of these codes is 2560 mA.
• Alternatively, REG0x3F() may be set to a code that utilizes the new 64-mA LSB (bit [6] = 1) with FDPM_RISE
threshold of 107% for all ILIM1 values greater than 2.5 A. The first of these codes is 2560 mA.
Table 6-2. Allowed Combinations of InputCurrent() and FDPM_RISE Settings
104% FDPM_RISE 107% FDPM_RISE
InputCurrent() with 64 mA step size (REG0x3F[6] = 0) Allowed for all InputCurrent() settings Always Allowed
of 2.56 A and greater
InputCurrent() with 128 mA step size (REG0x3F[6] = 1) Not Allowed Allowed for all InputCurrent() settings
of 2.56 A and greater

6.3.5.1 Setting Input Current Limit

System current normally fluctuates as portions of the system are powered-up or put to sleep. With the input
current limit, the current draw from the AC wall adapter is limited to a set level to avoid overloading the adapter.
The total input current, from a wall adapter or other DC source, is the sum of the system current and current
required to charge the battery. When the input current exceeds the set input current limit, the BQ24800 device
decreases the charge current to provide priority to the system load. As the system current rises, the available
charge current drops to 0. If the system load increases further after charging current has been reduced to 0, the
charger goes into hybrid power boost mode and adds battery power to support the system load, maintaining the
input current limit.
During DPM regulation, the total input current is the sum of the device supply current IBIAS, the charger input
current, and the system load current ILOAD, and can be estimated as follows:

ª IBATTERY ˜ VBATTERY º
IINPUT ILOAD « » IBIAS
¬ VIN ˜ K ¼ (2)

In the above equation, η is the efficiency the switching regulator and IBATTERY is the battery charging or
discharging current (positive for charging and negative for discharging). In charging mode, the charger converter
is in buck configuration. In hybrid power boost mode, the charger converter is in boost configuration.
To set the input current limit, write a 16-bit InputCurrent() command (REG0x3F) using the data format listed in
Table 6-17. When using a 10-mΩ sense resistor, the BQ24800 device provides an input-current limit range of
64 mA to 8.128 A, with 64-mA resolution. Upon POR, default input current limit is 4096 mA on 10-mΩ current
sensing resistor (RAC). Additionally, when 0 mA or a value above 8.128A is written, the write is considered invalid
and is not written to the register.
The ACP and ACN pins are used to sense RAC with default value of 10 mΩ. However, resistors of other values
can also be used. The actual current is scaled by the ratio of 10 mΩ and RAC. For example, the input current
setting code of 4096mA on 10 mΩ becomes 2048mA if sense resistor is 20 mΩ. For a larger sense resistor,

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larger sense voltage is given, and higher regulation accuracy, but at the expense of higher conduction loss and a
more narrow current range.
6.3.6 Two-Level Adapter Current Limit (Peak Power Mode)
An adapter can usually supply current higher than its DC rating for a few milliseconds to tens of milliseconds.
The BQ24800 employs two-level input current limit, or peak power mode, to fully utilize the adapter overloading
capability and minimize battery discharge. Peak power mode is enabled in REG0x38[13]. The DC current limit,
or ILIM1, is the same as adapter DC current DPM, set in REG0x3F(). The overloading current, or ILIM2, is set in
REG0x3C[14:11], as a percentage of ILIM1.
With peak power mode enabled, adapter current greater than ILIM1 will not immediately trigger hybrid boost
supplement mode. Instead, if the adapter current remains above the ILIM1 (scaled by FDPM_RISE percentage)
threshold for 50 uS, peak power mode is entered and the adapter DPM limit is raised to ILIM2 for a period of
TOVLD as set in 0x38H [15:14]. During this period, hybrid boost may still be entered if it is enabled and adapter
current exceeds ILIM2 (scaled by FDPM_RISE percentage) for a period of FDPM_DEG as set in REG0x37[4:3].
At the end of the TOVLD period, the BQ24800 enters a recovery period where the DPM limit is set to ILIM1 for
TMAX – TOVLD. TMAX is set in REG0x38[15:14]. Once the full TMAX (overload and recovery periods) has expired,
the peak power mode exits, also forcing an exit from hybrid boost mode if it is active. Upon this exit, the
BQ24800 will immediately re-enter a new peak power mode cycle if adapter current remains above the ILIM1
(scaled by FDPM_RISE percentage) for the 50 uS qualifying period.
TOVLD TOVLD
TMAX TMAX

ILIM2
ILIM1
IADPT
0A

ISYS

DCHG
IBATT
CHG

Figure 6-2. Two-Level Adapter Current Limit Timing Diagram, REG0x37[8] = 0

Charging may optionally be disabled (REG0x37[8]=0) during TMAX in order to reduce adapter current during
overload condition. If REG0x37[8] is instead set to 1, and if all other conditions for charging are met, including
the charge inhibit bit (REG0x12[0]) being set to 0, then charging will resume during TMAX if the adapter current
falls below the active current limit, which is ILIM2 during TOVLD and ILIM1 during the subsequent relaxation period.

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During the peak power mode overload period ( TOVLD ), the INOM event will not trigger PROCHOT, even if the
event is enabled and adapter current exceeds the INOM threshold. The ICRIT event remains active during this
time. During the recovery period ( TMAX - TOVLD ), both the INOM and ICRIT events are active if enabled.
The peak power mode timing parameters (TOVLD and TMAX) are not allowed to be changed while peak power
mode is enabled. Any write to either 0x38H [15:14] (TOVLD) or 0x38H [9:8] (TMAX) while the peak power mode is
enabled (0x38 [13] = 1) will be ignored. In order to change these parameters, the user must first disable peak
power mode by writing 0x38 [13] = 0, then update TOVLD and/or TMAX, and then re-enable the peak power mode
by writing 0x38 [13] = 1.

6.3.7 EMI Switching Frequency Adjust

The charger switching frequency can be adjusted between 300 kHz, 400 kHz, 600 kHz or 800 kHz to solve
EMI issues through SMBus command REG0x12[9:8]. Lower switching frequencies provide greater efficiency and
lower EMI. Using a higher switching frequency reduces ripple, allowing smaller inductor and capacitor values.
6.3.8 Device Protections Features
6.3.8.1 Charger Timeout
The BQ24800 device includes a watchdog timer to suspend charging, hybrid power boost mode or battery only
boost mode if the charger does not receive a write ChargeVoltage() or write ChargeCurrent() command within
175 s (adjustable through REG0x12[14:13] command).

If a watchdog timeout occurs, all register values remain unchanged, but the converter is suspended. A write
to ChargeVoltage(), or ChargeCurrent(), or change of REG0x12[14:13] resets watchdog timer and resumes
converter for charging, hybrid power boost mode or battery only boost mode. The watchdog timer can be
disabled, or set to 5, 88, or 175 s through SMBus command REG0x12[14:13].
6.3.8.2 Input Overcurrent Protection (ACOC)
If no battery is present, hybrid boost mode has been disabled, or if the hybrid boost discharge current has been
reached, the BQ24800 device cannot maintain the input current level once the charge current has been reduced
to 0. When the input current exceeds 1.25x or 2x of ILIM2 set point for the 6-ms deglitch time, ACFET/RBFET
is latched off and an adapter removal is required to force ACDET < 0.6 V to remove the latch. After the latch is
removed, ACFET/RBFET can be turned on again.
The ACOC function threshold can be set to 1.25x or 2x of ICRIT (REG0x37[9]) current or disabled through
SMBus command (REG0x37[10]).
6.3.8.3 Charge Overcurrent Protection (CHG_OCP)
The BQ24800 device has cycle-by-cycle peak overcurrent protection. It monitors the voltage across SRP and
SRN, and prevents the current from exceeding the threshold based on the charge current set point. The
high-side gate drive turns off for the rest of the cycle when over current is detected, and resumes when the next
cycle starts.
The charge OCP threshold is automatically set to 6, 9, and 12 A on a 10-mΩ current sensing resistor based
on charge current register value. This prevents the threshold from being too high, which is not safe, or too
low, which can be triggered in typical operation. Select proper inductance to prevent OCP triggering in typical
operation due to high inductor current ripple.
6.3.8.4 Battery Overvoltage Protection (BATOVP)
In battery charging, the BQ24800 device does not allow the high-side and low-side MOSFET to turn-on when
the battery voltage at SRN exceeds 104% of the regulation voltage set point. If BATOVP lasts over 30 ms,
the charger is completely disabled until the battery voltage at SRN falls below 102% of the regulation voltage
set point. This allows a quick response to an overvoltage condition – such as when the load is removed or
the battery is disconnected. A 6-mA current sink from SRP to GND is only on during BATOVP and allows
discharging the stored output inductor energy that is transferred to the output capacitors.

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In battery boost mode (either battery only boost or hybrid power boost), the BQ24800 device keeps running
boost operation when BATOVP is detected, and no 6-mA sink is applied to SRP during these boost modes.
6.3.8.5 Battery Short
When battery voltage on SRN falls below 2.5 V, the converter resets for 1 ms and resumes charge if all the
enable conditions in the Enable and Disable Charging section are satisfied. This prevents overshoot current in
the inductor, which can saturate the inductor and may damage the MOSFET. The charge current is limited to 0.5
A on 10-mΩ current sensing resistor when BATLOWV condition persists and LSFET keeps off. The LSFET turns
on only for a refreshing pulse to charge BTST capacitor.
6.3.8.6 Thermal Shutdown Protection (TSHUT)
The WQFN package has low thermal impedance, which provides good thermal conduction from the silicon to
the ambient, to keep junction temperatures low. As an added level of protection, the charger converter turns
off for self-protection whenever the junction temperature exceeds the 155°C. The charger stays off until the
junction temperature falls below 135°C. During thermal shutdown, the REGN LDO current limit is reduced to
14 mA. Once the temperature falls below 135°C, charge can be resumed with soft start. During TSHUT, the
ACFET/RBFET stays on to power the system rail.
6.3.8.7 Inductor Short, MOSFET Short Protection
The BQ24800 device has a unique short circuit protection feature. Its cycle-by-cycle current monitoring feature is
achieved through monitoring the voltage drop across RDS(on) of the switching MOSFETs. In case of a MOSFET
short or inductor short circuit, the overcurrent condition is sensed by the comparator, the HSFET or LSFET is
turned off for the remainder of the switching cycle, and a counter is incremented. The high-side and low-side
MOSFETs each have an independent comparator and counter. After either counter reaches seven, the charger
is latched off and ACFET and RBFET are turned off to disconnect the adapter from the system. BATFET is
turned on to connect the battery pack to the system. The short circuit counters are reset each time that the
power stage is enabled, but once either counter reaches seven, the charger is latched off. To reset the charger
from latch-off status, the IC VCC pin must be pulled below UVLO or the ACDET pin must be pulled below 0.6
V. The low-side MOSFET Vds monitor circuit is enabled by REG0x37[7], and the threshold is 250 mV measured
between the PHASE and GND pins. The high-side MOSFET Vds monitor circuit is enabled by REG0x37[6],
and the threshold is 750 mV measured between the ACP and PHASE pins, including both the RAC sense
resistor and the HSFET. During hybrid boost and battery only boost functions, the low-side MOSFET short circuit
protection threshold is used for cycle-by-cycle current limiting, but the charger does not latch off.
Due to the blanking time of the MOSFET short protection, which blanks out the switching noise from when
the MOSFET first turns on, the cycle-by-cycle charge overcurrent protection may detect high current and turn
off MOSFET before the MOSFET short protection is triggered. In such a case, the charger's MOSFET short
protection may not be activated, so that the counter does not count to seven and then latch off. Instead the
charger may continuously keep switching with very narrow duty cycle to limit the cycle-by-cycle current peak
value. However, the charger should still be safe and does not cause failure because the duty cycle is limited to
a very short time and the MOSFET should still be inside the safety operation area. During a soft start period, it
may take a long time instead of just seven switching cycles to detect short circuit due to the same reason of the
blanking time.
6.4 Device Functional Modes
6.4.1 Battery Charging in Buck Mode
The step-down switching controller is designed to charge a series stack of batteries. The battery charging cycle
has two phases - constant current (CC) and constant voltage (CV). During the constant current phase, the
charger regulates the charging current to the limit in REG0x14(). Once the voltage on SRN reaches the limit in
REG0x15, the charger enters CV mode to regulate the battery voltage. The following conditions must be valid to
start charge:
• Charge is enabled through SMBus (REG0x12[0], default is 0, charge enabled)
• ILIM pin voltage is higher than VILIM(RISE) (120 mV nominal)
• All ChargeCurrent(), ChargeVoltage() and InputCurrent() registers have valid value programmed

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• ACOK is valid (see Device Power Up for details)

• ACFET and RBFET turn on without latchoff failure (see System Power Selection for details)
• VSRN does not exceed BATOVP threshold
• IC temperature does not exceed TSHUT threshold
• Not in ACOC condition (see Device Protections Features for details)
One of the following conditions stops on-going charging:
• Charge is inhibited through SMBus(REG0x12[0] = 1)
• ILIM pin voltage is lower than VILIM(FALL) (75 mV nominal)
• ChargeCurrent(), ChargeVoltage() or InputCurrent() is set to 0 or out of range
• ACOK is pulled low (see Device Power Up for details)
• ACFET turns off
• VSRN exceeds BATOVP threshold
• TSHUT IC temperature threshold is reached
• ACOC is detected (see Device Protections Features for details)
• Short circuit is detected (see Inductor Short, MOSFET Short Protection for details)
• Watchdog timer expires if watchdog timer is enabled (see Charger Timeout for details)
6.4.1.1 Setting the Charge Current
To set the charge current, write a 16-bit ChargeCurrent() command (REG0x14) using the data format listed in
Table 6-13. With 10-mΩ sense resistor, the BQ24800 device provides a charge current range of 128 mA to
8.128 A, with 64-mA step resolution. Upon POR, charge current is 0 A. Any conditions for ACOK low except
ACOV resets the ChargeCurrent() to 0. Sending ChargeCurrent() 0 mA terminates charge. To provide secondary
protection, the BQ24800 has an ILIM pin with which the user can program the maximum allowed charge current.
Internal charge current limit is the lower one between the voltage set by ChargeCurrent(), and the voltage on
ILIM pin. To disable this function, the user can pull ILIM above 2 V, which is the maximum charge current
regulation limit. Setting REG0x38[7] to 0 will also disable the ILIM pin charge current limiting so that only the
REG0x14 value is used. When ILIM is below 60 mV, battery charging is disabled. The preferred charge current
limit can be derived from the below equation:

VILIM
ICHG
20 u RSR (3)

The SRP and SRN pins are used to sense RSR with default value of 10 mΩ. However, resistors of other values
can also be used. The actual current is scaled by the ratio of 10 mΩ and RSR. For example, the charge current
setting code of 4096mA on 10 mΩ becomes 2048mA if sense resistor is 20 mΩ. For a larger sense resistor, a
larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher conduction loss. If
current sensing resistor value is too high, it may trigger an overcurrent protection threshold because the current
ripple voltage is too high. In such a case, either a higher inductance value or a lower current sensing resistor
value should be used to limit the current ripple voltage level. A current sensing resistor value no more than 20
mΩ is suggested.
6.4.1.2 Setting the Charge Voltage
To set the output charge regulation voltage, write a 16-bit ChargeVoltage() command (REG0x15) using the data
format listed in Table 6-14. The BQ24800 device provides charge voltage range from 1.024 to 19.200 V, with
16-mV step resolution. Upon POR, charge voltage limit is 0 V. Sending ChargeVoltage() 0 mV disables battery
charging.
The SRN pin is used to sense the battery voltage for voltage regulation and should be connected as close to the
battery as possible. Place a decoupling capacitor (0.1 µF recommended) as close to IC as possible to decouple
high frequency noise.
6.4.1.3 Automatic Internal Soft-Start Charger Current
Every time the charge is enabled, the charger automatically applies soft-start on charge current to avoid any
overshoot or stress on the output capacitors or the power converter. The charge current starts at 128 mA, and

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the step size is 64 mA in CCM mode for a 10-mΩ current sensing resistor. Each step lasts around 400 μs in
CCM mode, till it reaches the programmed charge current limit. No external components are needed for this
function.
During DCM mode, the soft start up current step size is larger and each step lasts for longer time period due to
the intrinsic slow response of DCM mode.
6.4.2 Hybrid Power Boost Mode
The BQ24800 device supports the hybrid power boost mode to boost battery voltage to adapter level and
supplement adapter power when system power demand is temporarily higher than adapter maximum level. Ultra
fast 150 µs response time (requires REG0x37[4:3] = 10b) keeps the adapter from crashing. After device powers
up, the REG0x37[2] is 0 to disable hybrid power boost mode. To enable hybrid power boost mode, host writes 1
to REG0x37[2]. The BST_STAT pin and REG0x37[1] indicate if the device is in hybrid power boost mode when
0x37[11] = 1.
To support hybrid power boost mode, input current must be set higher than 1536 mA for 10-mΩ input current
sensing resistor. The threshold to enter hybrid power boost mode (FDPM_RISE in REG0x37[5]) is set as
percentage to the input current limit. When peak power is not enabled, the input current limit is always ILIM1,
set in REG0x3F(). For discussion of hybrid boost behavior when peak power is enabled, refer to Section
6.3.6. When input current is higher than 104/107% of input current limit, the BQ24800 converter changes
from buck charging converter to hybrid power boost converter. During hybrid power boost mode the adapter
current is regulated at input current limit level so that adapter will not crash. If the watchdog timer is enabled
(REG0x12[14:13]) and it expires, it will halt the hybrid boost mode converter. Writing to REG0x12[14:13],
REG0x14 or REG0x15 will restart the watchdog timer and allow hybrid boost mode to be reentered.
One of the following conditions stops on-going hybrid power boost mode:
• Adapter current falls below FDPM_FALL (REG0x37[0]) threshold
• Hybrid power boost mode is disabled (REG0x37[2] = 0)
• Adapter is removed
• Battery voltage is below depletion threshold in REG0x3B[15:14]
• ACFET turns off
• TSHUT IC temperature threshold is reached
• Short circuit is detected (see Inductor Short, MOSFET Short Protection for details)
• Watchdog timer expires if watchdog timer is enabled (see Charger Timeout for details)
6.4.3 Battery Only Boost Mode
When the system is powered from the battery with no adapter attached, a large system load will drop the system
voltage significantly due to the battery's impedance. In order to provide the ability to handle large transients
over the full operating range of the battery, the BQ24800 provides battery only boost mode. This mode uses the
switching converter to boost the battery voltage to a regulated system output, providing additional headroom for
system transients.
Unlike the hybrid power boost mode, which is expected to enter and exit frequently as supplemental current
is required, battery only boost mode is entered once and maintained until either the adapter is plugged in, the
battery reaches the BAT_DEPL_VTH (REG0x3B[15:14]) battery depletion threshold, or the mode is manually
exited with the EN_BATT_BOOST (REG0x38[6]) bit. Entry into the mode may either be handled automatically,
using the VSYSMIN threshold as set in VSysMin() (REG0x3E) register, or manually using the EN_BATT_BOOST
bit. In order to use automatic entry, EN_BATT_BOOST is set to 1 while system voltage is above VSYSMIN. When
the system voltage falls below VSYSMIN, the converter will enter battery only boost mode, regulating the system
voltage to either 1.5V or 2.3V above VSYSMIN as set by the VBOOST (REG0x38[5]) bit.
All of the following conditions must be met in order to enter battery only boost mode:
• Battery only boost mode is enabled (REG0x38[6] = 1)
• Battery low power mode is disabled (REG0x12[15] = 0)
• System voltage (VACN) is below VSYSMIN

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• ACOK is LOW
• Battery voltage (VSRN) is above depletion threshold in REG0x3B[15:14]
The time required to transition from direct-battery to regulated boost output is dependent on system conditions
and generally requires between 1-5 msec. During this time, the battery via the body diode of the battery
MOSFET holds up the system rail, resulting in a temporary voltage drop between the battery and system
according to the forward voltage of the body diode. The VSysMin() entry should be set to a high enough
threshold that the battery can support the transition under the worst case loading condition. A method for
calculating this threshold is provided in Equation 4

VSysMin() = VOP_MIN + ( ISYS_MAX X RBATT ) + VBATFET_FD (4)

VOP_MIN is the minimum operational voltage that will support the system. RBATT includes both the internal
impedance of the battery as well as any resistance in the power path between the battery and the system.
VBATFET_FD is the forward voltage drop of the BATFET body diode.

VSYS 1.5 or 2.3V

VSYSMIN Body Diode

Forward Voltage

1-5 mSec
Figure 6-3. Entry Into Battery Only Boost Mode

For systems where finer control is desired, entry into battery-only boost mode may be executed manually. For
manual control, an external microcontroller is used to monitor the battery charge using a battery gas gauge IC or
other method, and this information is used to determine the optimal point for entry into battery only boost mode.
In order to manually enter battery only boost, VSYSMIN must be set below the current system voltage and then
the REG0x38[6] enable bit set to 1. VSYSMIN may be adjusted after battery only boost is active in order to adjust
the system regulation voltage. There is a delay of approximately 50 mSec (typical) between completion of the
SMBUS command to enable battery only boost and entry into the mode.
One of the following conditions stops on-going battery only boost mode:
• Battery only boost mode is disabled (REG0x38[6] = 0)
• Battery low power mode is enabled (REG0x12[15] = 1)
• Adapter plugs in and ACOK goes HIGH
• Battery voltage (VSRN) is below depletion threshold in REG0x3B[15:14]
• Battery voltage (VSRN) rises to within 200 mV of system regulation voltage (measured at VACN)
• TSHUT IC temperature threshold is reached
• Short circuit is detected (see Inductor Short, MOSFET Short Protection for details)
• Watchdog timer expires if watchdog timer is enabled (see Charger Timeout for details)
In battery-only boost mode, the BQ24800 will regulate system voltage to either ( VSYSMIN + 1.5V ) or ( VSYSMIN +
2.3 V ) as set in REG0x38[5]. In order to properly transition during adapter insertion and removal, it is required
that the minimum ACOK falling threshold for ACDET (2.30 V scaled by ACDET resistor divider) is above this
regulation point. Once the device is in boost mode, status bit REG0x37[1] is set to 1 and BST_STAT pin goes
LOW.
If the adapter is inserted while battery only boost mode is active, the system voltage will transition from
the battery only boost regulation voltage to the adapter voltage, maintaining battery only boost mode until
the ACFET has completely turned on. Additionally, the ICRIT PROCHOT signal, if enabled, is automatically

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asserted, even if the adapter current never exceeds the ICRIT threshold. This may be used to preemptively slow
the CPU during the transition.
6.4.3.1 Setting Minimum System Voltage in Battery Only Boost Mode
To set the VSYSMIN minimum system voltage during battery only boost mode, write a 16-bit VSysMin() command
(REG0x3E) using the data format listed in Table 6-16. The BQ24800 device provides minimum system voltage
range from 5.632-13.568 V (0x1600 - 0x3500), with 256-mV step resolution. Upon POR, minimum system
voltage limit is 8.96 V (0x2300). The regulation voltage during battery only boost mode is either 1.5V or 2.3V
above VSYSMIN as set in REG0x38[5].
The ACN pin is used to sense the system voltage for converter regulation. Place a decoupling capacitor (0.1 µF
recommended) as close to IC as possible to decouple high frequency noise.
6.4.4 Battery Discharge Current Regulation in Hybrid Boost Mode and Battery Only Boost Mode
To keep the discharge current below battery OCP rating during hybrid boost mode or battery only boost mode,
the BQ24800 device supports discharge current regulation. After device powers up, the REG0x37[15] is 0 to
disable discharge current regulation. To enable discharge current regulation, host writes 1 to REG0x37[15].
REG0x37[15]=1 enables battery discharge current regulation during the hybrid power boost mode and battery
only boost mode if the conditions to start either boost mode are valid.
Once the battery discharge current is limited, the input current goes up to meet the system current requirement.
The user can assert PROCHOT to detect input current increase (ICRIT or INOM), and request CPU throttling to
lower the system power.
To set the discharging current limit, write a 16-bit DischargeCurrent() command (REG0x39) using the data format
listed in Table 6-15. When using a 10-mΩ sense resistor, the BQ24800 device provides a discharge current limit
range of 512 mA to 32.256 A, with 512-mA resolution. Upon POR, default discharge current limit is 6.144 A on
10-mΩ current sensing resistor (RSR).
To provide secondary protection during battery discharge, the BQ24800 has an ILIM pin with which the user
can program the maximum discharge current. Typically, the user sets the limit below battery pack over current
protection (OCP) threshold for maximum battery discharge capacity. Refer to battery specification for OCP
information. Internal discharge current limit is the lower one between the voltage set by DischargeCurrent(), and
the voltage on ILIM pin. To disable this function, the user can pull ILIM pin above 1.6V, which is the maximum
discharge current regulation limit. Setting REG0x38[7] to 0 will also disable the ILIM pin discharge current
limiting so that only the REG0x39 value is used. When ILIM is below 60mV, hybrid boost and battery only boost
are disabled. The set discharge current limit can be derived from Equation 5.

VILIM
IDCHG
5 u RSR (5)

The SRP and SRN pins are used to sense RSR with default value of 10 mΩ. However, resistors of other values
can also be used. The actual current is scaled by the ratio of 10 mΩ and RSR. For example, the discharge
current setting code of 4096mA on 10 mΩ becomes 2048mA if sense resistor is 20 mΩ. For a larger sense
resistor, a larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher
conduction loss. If current sensing resistor value is too high, it may trigger an overcurrent protection threshold
because the current ripple voltage is too high. In such a case, either a higher inductance value or a lower current
sensing resistor value should be used to limit the current ripple voltage level. A current sensing resistor value no
more than 20 mΩ is suggested.
When operating in battery only boost mode, the battery is the only power source in the system. Limiting the
battery discharge current will cause system voltage to drop if the system load is greater than the amount that
may be supplied by the battery with the discharge limit set. When boosting the battery to a higher voltage,
the battery discharge current will be larger than the system current according to the ratio of system to battery
voltage. It is common for the battery current to be double that of the system current. The discharge limit should
be set to the largest current that the battery and switching components can support without damage and should

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be used only as a protection against high-current damage as might occur from a short circuit. Limiting current in
battery boost mode will cause the system voltage to fall below the regulation set point.
6.4.5 Battery LEARN Cycle
A battery LEARN cycle can be activated through the REG0x12[5]. When LEARN is enabled, the system draws
power from the battery instead of the adapter by turning off ACFET/RBFET and turning on BATFET. The LEARN
function allows the battery to discharge in order to calibrate the battery gas gauge over a complete discharge
and charge cycle. The controller automatically exits the LEARN cycle when the battery voltage is below the
battery depletion threshold as set in REG0x3B[15:14]. The system switches back to adapter input by turning off
BATFET and turning on ACFET/RBFET. After the LEARN cycle, REG0x12[5] is automatically reset to 0.

When adapter is removed during LEARN mode, the charger exits LEARN mode by setting REG0x12[5] to 0. The
battery FET keeps powering the system without any glitches. Later when adapter plugs in again, host has to set
REG0x12[5] to 1 to enable LEARN mode again.
When the battery is removed during LEARN mode, BATPRES rises from low to high and the device exits LEARN
mode. ACFET/RBFET quickly turns on in 100 µs to prevent the system from crashing. The turn-on triggered by
BATPRES is faster than that triggered by battery depletion comparator.
6.4.6 Converter Operational Modes
6.4.6.1 Continuous Conduction Mode (CCM)
With sufficient charge current, the inductor current does not cross 0, which is defined as CCM. The controller
compares SRP-SRN (CC charging) or SRN (CV charging) to a reference value as set in ChargeCurrent()
REG0x14 and ChargeVoltage() REG0x15. This error is integrated in the error amplifier and the error amplifier
output (EAO) is compared to a ramp voltage. As long as EAO voltage is above the ramp voltage, the high-side
MOSFET (HSFET) stays on. When the ramp voltage exceeds EAO voltage, HSFET turns off and low-side
MOSFET (LSFET) turns on. At the end of the cycle, ramp gets reset and LSFET turns off, ready for the next
cycle. There is always break-before-make logic during transition to prevent cross-conduction and shoot-through.
During the dead time when both MOSFETs are off, the body-diode of the low-side power MOSFET conducts the
inductor current.
During CCM, the inductor current always flows and creates a fixed two-pole system. Having the LSFET turn-on
keeps the power dissipation low and allows safe charging at high currents.
6.4.6.2 Discontinuous Conduction Mode (DCM)
During the HSFET off time when LSFET is on, the inductor current decreases. If the current goes to 0, the
converter enters DCM. Each cycle, if the voltage across SRP-SRN falls below 5 mV (0.5 A on 10 mΩ RSR
flowing into the battery for charging or out of the battery for hybrid boost), the undercurrent comparator (UCP)
turns off LSFET (if charging) or HSFET (if hybrid boosting) to block negative inductor current.
During DCM the loop response automatically changes. It changes to a single-pole system and the pole is
proportional to the load current.
6.4.6.3 Non-Sync Mode and Light Load Comparator
When charging, if the average charge current falls below 125 mA (on 10-mΩ sense resistor) the light load
comparator keeps LSFET off to block reverse current in the inductor. When average current rises above 250 mA,
the LSFET turns on again. Similarly, in boost mode, when the discharge current is below 250 mA (on 10-mΩ
sense resistor), the light load comparator keeps HSFET off. When average current rises above 500 mA, the
HSFET turns on again.

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6.5 Programming
6.5.1 SMBus Interface
The BQ24800 device operates as a slave, receiving control inputs from the embedded controller host
through the SMBus interface. This devices uses a simplified subset of the commands documented in System
Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The BQ24800 may use
the SMBus read-word and write-word protocols (shown in Table 6-3 and Table 6-4) to receive commands from
a smart battery. The BQ24800 device performs only as a SMBus slave device with address 0x12. Note that this
SMBUS address is written in 8-bit format, which is the 7-bit SMBus address with a "0" bit appended to represent
the R/W bit. The corresponding 7-bit address is 0x09. The BQ24800 does not initiate communication on the bus.
The BQ24800 has two identification registers, a 16-bit device ID register (0xFF) and a 16-bit manufacturer ID
register (0xFE). The BQ24800 has manufacturer ID of 0x40 and device ID of 0x38.
SMBus communication starts when VCC is above UVLO.
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose
pull-up resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.
Communication starts when the master signals a start condition, which is a high-to-low transition on SDA,
while SCL is high. When the master has finished communicating, the master issues a stop condition, which is a
low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 6-4 and
Figure 6-5 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and
data bytes are transmitted between the start and stop conditions. The SDA state changes only while SCL is low,
except for the start and stop conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of
SCL. Nine clock cycles are required to transfer each byte in or out of the device because either the master or
the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The BQ24800 supports the
charger commands listed in Table 6-3.
6.5.1.1 SMBus Write-Word and Read-Word Protocols
Table 6-3. Write-Word Format
S SLAVE W ACK COMMAND ACK LOW DATA ACK HIGH DATA ACK P
(1) (3) ADDRESS(1) (1) (6) (2) (5) BYTE(1) (2) (5) BYTE(1) (2) (5) BYTE(1) (2) (5) (1) (4)

7 bits 1b 1b 8 bits 1b 8 bits 1b 8 bits 1b

MSB LSB 0 0 MSB LSB 0 MSB LSB 0 MSB LSB 0

(1) Master to slave

(2) Slave to master (shaded gray)
(3) S = Start condition or repeated start condition
(4) P = Stop condition
(5) ACK = Acknowledge (logic-low)
(6) W = Write bit (logic-low)
Table 6-4. Read-Word Format
S(1) SLAVE W ACK COMMAND ACK S(1) SLAVE R(1) ACK LOW DATA ACK HIGH DATA NACK P
(3) ADDRESS(1) (1) (7) (2) (5) BYTE(1) (2) (5) (3) ADDRESS(1) (8) (2) (5) BYTE(2) (1) (5) BYTE(2) (1) (6) (1) (4)

7 bits 1b 1b 8 bits 1b 7 bits 1b 1b 8 bits 1b 8 bits 1b

MSB LSB 0 0 MSB LSB 0 MSB LSB 1 0 MSB LSB 0 MSB LSB 1

(1) Master to slave

(2) Slave to master (shaded gray)
(3) S = Start condition or repeated start condition
(4) P = Stop condition
(5) ACK = Acknowledge (logic-low)
(6) NACK = Not acknowledge (logic-high)
(7) W = Write bit (logic-low)
(8) R = Read bit (logic-high)

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6.5.1.2 Timing Diagrams

A B C D E F G H I J K L M
tLOW tHIGH

SMBCLK

SMBDATA

tSU:STA tHD:STA tSU:DAT tHD:DAT tHD:DAT tSU:STO tBUF

A = Start condition H = LSB of data clocked into slave

B = MSB of address clocked into slave I = Slave pulls SMBDATA line low

C = LSB of address clocked into slave J = Acknowledge clocked into master

D = R/W bit clocked into slave K = Acknowledge clock pulse

E = Slave pulls SMBDATA line low L = Stop condition, data executed by slave

F = ACKNOWLEDGE bit clocked into master M = New start condition

G = MSB of data clocked into slave

Figure 6-4. SMBus Write Timing

A B C D E F G H I J K
tLOW tHIGH

SMBCLK

SMBDATA

tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:DAT tSU:STO tBUF

A = START CONDITION E = SLAVE PULLS SMBDATA LINE LOW I = ACKNOWLEDGE CLOCK PULSE

A = Start condition G = MSB of data clocked into master

B = MSB of address clocked into slave H = LSB of data clocked into master

C = LSB of address clocked into slave I = Acknowledge clock pulse

D = R/W bit clocked into slave J = Stop condition

E = Slave pulls SMBDATA line low K = New start condition

F = ACKNOWLEDGE bit clocked into master

Figure 6-5. SMBus Read Timing

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6.6 Register Maps

6.6.1 Battery-Charger Commands
The BQ24800 supports fourteen battery-charger commands that use either Write-Word or Read-Word protocols,
as summarized in Table 6-5. ManufacturerID() and DeviceID() can be used to identify the BQ24800. The
ManufacturerID() command always returns 0x0040 and the DeviceID() command always returns 0x0038.
Table 6-5. Battery Charger Command Summary
REGISTER ADDRESS REGISTER NAME READ OR WRITE DESCRIPTION POR STATE
0x12 ChargeOption0() Table 6-6 Read or Write Charge Options Control 0 0xE108
0x3B ChargeOption1() Table 6-7 Read or Write Charge Options Control 1 0xC220
0x38 ChargeOption2()Table 6-8 Read or Write Charge Options Control 2 0x0384
0x37 ChargeOption3()Table 6-9 Read or Write Charge Options Control 3 0x1A40
0x3C ProchotOption0()Table 6-10 Read or Write PROCHOT Options Control 0 0x4A54
0x3D ProchotOption1() Table 6-11 Read or Write PROCHOT Options Control 1 0x8120
0x3A ProchotStatus() Table 6-12 Read Only PROCHOT status 0x0000
0x14 ChargeCurrent() Table 6-13 Read or Write 7-bit Charge Current Setting 0x0000
0x15 ChargeVoltage() Table 6-14 Read or Write 11-bit Charge Voltage Setting 0x0000
0x39 DischargeCurrent() Table Read or Write 6-bit Discharge Current Setting 0x1800, or 6144mA
6-15
0x3E VsysMin() Table 6-16 Read or Write 7-bit Minimum System Voltage 0x2300, or 8960 mV
Setting
0x3F InputCurrent() Table 6-17 Read or Write 7-bit Input Current Setting 0x1000, or 4096mA
0xFE ManufacturerID() Read Only Manufacturer ID 0x0040
0xFF DeviceID() Read Only Device ID 0x0038

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6.6.2 Setting Charger Options

6.6.2.1 ChargeOption0 Register
Figure 6-6. ChargeOption0 Register (0x12)
15 14 13 12 11 10 9 8
EN_LWPWR WDTMR_ADJ Reserved PWM_FREQ
R/W R/W R R/W

7 6 5 4 3 2 1 0
Reserved EN_LEARN IADP_GAIN IDCHG_GAIN Reserved CHRG_INHIBIT
R R/W R/W R/W R R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-6. ChargeOption0 Register (0x12H)

BIT BIT NAME DESCRIPTION
0: IC in performance mode with battery only. The PROCHOT, current/power monitor buffer, battery only boost
mode, and independent comparator follow register setting.
Low Power Mode Enable
[15] 1: IC in low power mode with battery only. IC is in the lowest quiescent current when this bit is 1. PROCHOT,
(EN_LWPWR)
discharge current monitor buffer, power monitor buffer, battery only boostmode and independent comparator
are disabled. (default at POR)
Set maximum delay between consecutive SMBus write charge voltage or charge current command.
If IC does not receive write on REG0x14() or REG0x15() within the watchdog time period, the charger converter
stops to disable charge and boost mode operations.
After expiration, the timer will resume upon the write of REG0x14() or REG0x15(). The charge or boost
WATCHDOG Timer Adjust
[14:13] operations will resume if all the other conditions are valid.
(WDTMR_ADJ)
00: Disable watchdog timer
01: Enabled, 5 sec
10: Enabled, 88 sec
11: Enable watchdog timer (175 s) (default at POR)
[12:10] Reserved 0 - Reserved
Converter switching frequency.
00: 600 kHz
Switching Frequency
[9:8] 01: 800 kHz (default at POR)
(PWM_FREQ)
10: 300 kHz
11: 400 kHz
[7:6] Reserved 0 - Reserved
Battery LEARN mode enable. In LEARN mode, ACFET and RBFET turn off and BATFET turns on. When
BATPRES is HIGH, IC exits LEARN mode and this bit is set back to 0. When the battery is depleted, the
LEARN Mode Enable
[5] charger cannot enable LEARN mode
(EN_LEARN)
0: Disable LEARN mode (default at POR)
1: Enable LEARN mode
IADP Amplifier Gain for Primary Ratio of IADP pin voltage over the voltage across ACP and ACN.
[4] Input 0: 20X (default at POR)
(IADP_GAIN) 1: 40X
Ratio of IDCHG pin voltage over the voltage across SRN and SRP.
IDCHG Amplifier Gain
[3] 0: 8x with discharge current range 0-32A for 10 mΩ RSR.
(IDCHG_GAIN)
1: 16x with discharge current range 0-16A for 10 mΩ RSR (default at POR)
[2:1] Reserved 0 - Reserved
Charge inhibit. When this bit is 0, battery charging is enabled with valid value in REG0x14() and REG0x15()
Charge Inhibit
[0] 0: Enable charge (default at POR)
(CHRG_INHIBIT)
1: Inhibit charge

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6.6.3 ChargeOption1 Register

Figure 6-7. ChargeOption1 Register (0x3B)
15 14 13 12 11 10 9 8
BAT_DEPL_VTH RSNS_RATIO EN_IDCHG EN_PMON PMON_RATIO Reserved
R/W R/W R/W R/W R/W R

7 6 5 4 3 2 1 0
CMP_REF CMP_POL CMP_DEG EN_FET_LATCHOFF Reserved EN_SHIP_DCHG Reserved
R/W R/W R/W R/W R R/W R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-7. ChargeOption1 Register (0x3B)

BIT BIT NAME DESCRIPTION
Battery over-discharge threshold. During LEARN cycle, when battery voltage is below the depletion threshold,
the IC exits LEARN mode. During boost mode, when battery voltage is below the depletion threshold, the IC
exits boost mode.
Battery Depletion Threshold
[15:14] 00: Falling threshold = 60% of ChargeVoltage() register setting
(BAT_DEPL_VTH)
01: Falling threshold = 64% of ChargeVoltage() register setting
10: Falling threshold = 68% of ChargeVoltage() register setting
11: Falling threshold = 72% of ChargeVoltage() register setting (default at POR)
Adjust the PMON calculation for different input sense resistor RAC and charge sense resistor RSR ratio.
Reference Table 6-1 for further detail..
RAC and RSR Ratio 00: RAC and RSR 1:1 (default at POR)
[13:12]
(RSNS_RATIO) 01: RAC and RSR 2:1
10: RAC and RSR 1:2
11: Reserved
IDCHG pin output enable.
IDCHG Buffer Enable
[11] 0: Disable IDCHG output to minimize Iq (default at POR)
(EN_IDCHG)
1: Enable IDCHG output
PMON pin output enable.
PMON Buffer Enable
[10] 0: Disable PMON output to minimize Iq (default at POR)
(EN_PMON)
1: Enable PMON output
Ratio of PMON output current vs total input and battery power. Reference Table 6-1 for further detail.
PMON Gain
[9] 0: 0.25 µA/W for 10 mΩ sense resistors
(PMON_RATIO)
1: 1 µA/W for 10 mΩ sense resistors (default at POR)
[8] Reserved 0 - Reserved
Independent comparator internal reference.
Independent Comparator
[7] 0: 2.3 V (default at POR)
Reference (CMP_REF)
1: 1.2 V
Independent comparator output polarity.
With comparator polarity bit set as 1, the hysteresis is set by placing a resistor from CMPIN to CMPOUT. With
Independent Comparator Polarity
[6] comparator polarity bit set as 0, the hysteresis is internally set as 100mV.
(CMP_POL)
0: When CMPIN is above internal threshold, CMPOUT is LOW (default at POR)
1: When CMPIN is above internal threshold, CMPOUT is HIGH
Independent comparator deglitch time, applied on the edge where CMPOUT goes LOW. No deglitch time is
applied on the rising edge of CMPOUT. If the value in REG0x3B[7:3] is changed by host, deglitch time will get
reset.
Independent Comparator Deglitch 00: Independent comparator is disabled
[5:4]
Time (CMP_DEG) 01: Independent comparator is enabled with output deglitch time 1 µs
Note: 1 µs deglitch should not be used when low-power mode bit is enabled.
10: Independent comparator is enabled with output deglitch time 2 ms (default at POR)
11: Independent comparator is enabled with output deglitch time 5 sec
When independent comparator is triggered, both ACFET/RBFET turn off. The latch off is cleared by either POR
Power Path Latch-off Enable or write this bit to zero. This function is available with CMP_DEG setting of 2 ms (10) or 5 sec (11).
[3]
(EN_FET_LATCHOFF ) 0: When independent comparator is triggered, no power path latch off (default at POR)
1: When independent comparator is triggered, power path latches off.
[2] Reserved 0 - Reserved
Discharge SRN pin for 140 ms with minimum 5-mA current.
Discharge SRN for Shipping
[1] 0: Disable discharge mode (default at POR)
Mode (EN_SHIP_DCHG)
1: Enable discharge mode
[0] Reserved 0 - Reserved

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6.6.4 ChargeOption2 Register

Figure 6-8. ChargeOption2 Register (0x38)
15 14 13 12 11 10 9 8
PKPWR_TOVLD EN_PKPWR Reserved PKPWR_TMAX
R/W R/W R R/W

7 6 5 4 3 2 1 0
EN_EXTILIM EN_BATT_BOOST VBOOST Reserved
R/W R/W R/W R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-8. ChargeOption2 Register (0x38)

BIT BIT NAME DESCRIPTION
Input source maximum over-load time TOVLD in peak power mode.
Peak Power Mode Over-load 00: 1 ms (default @ POR)
[15:14] Time 01: 2 ms
(PKPWR_TOVLD) 10: 5 ms
11: 10 ms
Peak power mode enable.
Peak Power Mode Enable
[13] 0: Disable peak power mode (default @ POR)
(EN_PKPWR)
1: Enable peak power mode
[12:10] Reserved 0 - Reserved
Peak power mode cycle time TMAX. Relax time is TMAX - TOVLD.
00: 20 ms (default @ POR)
Peak Power Mode Cycle Time
[9:8] 01: 40 ms
(PKPWR_TMAX)
10: 80 ms
11: 1 sec
External ILIM pin enable to set the charge and discharge current.
External Current Limit Enable
[7] 0: Charge/discharge current limit is set by REG0x14() and 0x39().
(EN_EXTILIM)
1: Charge/discharge current limit is set by the lower value of ILIM pin and registers. (default at POR)
Battery only boost mode enable. When charger exits battery boost due to higher battery voltage or fault, this
Battery Only Boost Mode Enable enable bit does not automatically go to zero.
[6]
(EN_BATT_BOOST) 0: Disable battery only boost mode (default at POR)
1: Enable battery only boost mode.
System Regulation Voltage in System regulation voltage in battery only boost mode.
[5] Battery Only Boost Mode 0: 1.5V + VsysMin() (default at POR)
(VBOOST) 1: 2.3V + VSysMin()
[4:0] Reserved 0 - Reserved

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6.6.5 ChargeOption3 Register

Figure 6-9. ChargeOption3 Register (0x37)
15 14 13 12 11 10 9 8
EN_IDCHG_REG Reserved ACDRV_OFF ACOK_DEG ACOK_STAT EN_ACOC ACOC_VTH PKPWR_ENCHRG
R/W R R/W R/W R R/W R/W R

7 6 5 4 3 2 1 0
IFAULT_HI IFAULT_LO FDPDM_RISE FDPM_DEG EN_HYBRID_BOOST BOOST_STAT FPDM_FALL
R/W R/W R/W R/W R/W R R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-9. ChargeOption3 Register (0x37)

BIT BIT NAME DESCRIPTION
Discharge Current Regulation Battery discharge current regulation enable.
[15] Enable 0: Disable discharge current regulation (default at POR)
(EN_IDCHG_REG) 1: Enable discharge current regulation
[14] Reserved 0 - Reserved
Force ACFET/RBFET to turn off, even with good adapter present.
[13] ACDRV Disable (ACDRV_OFF) 0: ACFET/RBFET control based on "System Power Selection". (default at POR)
1: Turn off ACFET/RBFET.
Adjust ACOK rising edge deglitch time.
ACOK Deglitch Time for Primary After POR, the first time adapter plugs in, deglitch time is always 150 ms if this register has not been written by
[12] Input the host. Starting from the 2nd time adapter plugs in, the deglitch time follows the bit setting.
(ACOK_DEG ) 0: ACOK rising edge deglitch time 150ms
1: ACOK rising edge deglitch time 1.3 sec (default at POR)
Input present indication bit. This bit is set to 1 when ACOK pin goes HIGH. Refer to for conditions to transition
Adapter Present Indicator ACOK.
[11]
(ACOK_STAT ) 0: AC adapter is not present
1: AC adapter is present
ACOC protection threshold by monitoring ACP_ACN voltage.
ACOC Enable
[10] 0: Disable ACOC (default at POR)
(EN_ACOC)
1: Enable ACOC
ACOC protection threshold by monitoring ACP_ACN voltage.
ACOC Limit
[9] 0: 125% of ILIM2
(ACOC_VTH)
1: 200% of ILIM2 (default at POR)
Allow battery charging during peak power TMAX cycle.
0: Battery charging is NOT allowed during TMAX. The adapter only supports system load. This reduces the
[8] PKPWR_ENCHRG
chance of overloading the adapter. (default at POR)
1: Battery charging is allowed during TMAX. The adapter current capability of ILIM1 and ILIM2 is fully utilized.
MOSFET/inductor short protection by monitoring ACN to PHASE voltage
HSFET VDS Threshold
[7] 0: Disable (default at POR)
(IFAULT_HI)
1: 750 mV
MOSFET/inductor short protection by monitoring PHASE to GND voltage (LSFET drain-source voltage.) Also
LSFET VDS Threshold provides cycle-by-cycle current limit protection during hybrid boost and battery only boost functions.
[6]
(IFAULT_LO) 0: Disable
1: 250 mV (default at POR)
Fast DPM comparator threshold to enter hybrid power boost mode. (Minimum REG0x3F DPM setting for boost
mode: 1536 mA). The threshold is set as percentage to the input current limit. When peak power is not enabled,
the input current limit is ILIM1, set in REG0x3F(). When the device is in TOVLD of peak power mode cycle, input
Hybrid Power Boost Mode Entry
current limit is ILIM2, and the threshold is 107% of ILIM2. For the rest of peak power mode cycle, input current
[5] Threshold
limit is ILIM1.
(FDPM_RISE)
0: 107%
1: 104%
Refer to Table 6-2 for allowed conditions to set this bit to 1.
Response time from system current exceeding Fast DPM Threshold to battery discharge in boost mode.
Fast DPM Deglitch 00: Response time 150 µs (default at POR)
[4:3]
Time (FDPM_DEG) 01: Response time 250 µs
1X: Response time 50 µs
Hybrid power boost mode enable bit. When BATPRES goes from LOW to HIGH (battery removal), this bit will
be reset to zero to disable boost mode. When the charger exits hybrid power boost due to smaller load or fault,
Hybrid Power Boost Mode
[2] this enable bit doesn't automatically go to zero.
Enable(EN_HYBRID_BOOST)
0: Disable hybrid power boost mode (default at POR)
1: Enable hybrid power boost mode

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Table 6-9. ChargeOption3 Register (0x37) (continued)

BIT BIT NAME DESCRIPTION
Active-high boost mode indicator. This bit is read only.
Boost Mode Indication 0: Charger is not in hybrid power boost mode or battery only boost mode (default at POR)
[1]
(BOOST_STAT) 1: Charger is in hybrid power boost mode or battery only boost mode (Note that the BST_STAT pin is active-low
and is low when the BOOST_STAT register bit is set to 1.)
Hybrid Power Boost Mode Exit Fast DPM comparator threshold to exit hybrid power boost mode.
[0] Threshold 0: 93% (default at POR)
(FDPM_FALL) 1: 96%

6.6.6 ProchotOption0 Register

Figure 6-10. ProchotOption0 Register (0x3C)
15 14 13 12 11 10 9 8
Reserved ILIM2_VTH[3:0] ICRIT_DEG Reserved
R R/W R/W R

7 6 5 4 3 2 1 0
VBATT_VTH[1:0] EN_PROCHOT_EX PROCHOT_WIDTH[1:0] PROCHOT_CLEAR INOM_DEG INOM_VTH
T
R/W R/W R/W R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-10. ProchotOption0 Register (0x3C)

BIT BIT NAME DESCRIPTION
[15] Reserved 0 - Reserved
ILIM2 threshold as percentage of DPM in REG0x3F(). At 250% setting, when IDPM is over 3.648A, clamp ILIM2
to 230% of IDPM.
Peak Adapter Current Limit The current is measured on the RAC between ACP and ACN. ICRIT is set as 110% of ILIM2.
[14:11]
(ILIM2_VTH) 0001 - 1001: 110% - 150%, step 5%
1001: 150%, 1010: 160%, 1011: 170%, 1100: 180%, 1101: 200%, 1110: 220%; 1111: 250%
Default 150% (1001)
Typical ICRIT deglitch time.
00: 10 µs
ICRIT Deglitch Time
[10:9] 01: 100 µs (default at POR)
(ICRIT_DEG)
10: 400 µs
11: 800 µs
[8] Reserved 0 - Reserved
Battery voltage threshold to trigger PROCHOT.
Measure on SRN with fixed 20-µs deglitch time. Trigger when SRN voltage is below the threshold.
If REG0x15() is programmed below VBATT threshold, it is recommended to not enable VBATT in PROCHOT
Battery Voltage Threshold profile.
[7:6]
(VBATT_VTH) 00: 5.75 V
01: 6.00 V (default at POR)
10: 6.25 V
11: 6.50 V
PROCHOT Pulse Extension When pulse extension is enabled, keep PROCHOT pin voltage low until host write 0x3C[2] = 0.
[5] Enable 0: Disable pulse extension (default at POR)
(EN_PROCHOT_EXT) 1: Enable pulse extension
Minimum PROCHOT pulse width when REG0x3C[5]=0
00: 100 µs
PROCHOT Pulse Width
[4:3] 01: 1 ms
(PROCHOT_WIDTH[1:0])
10: 10 ms (default at POR)
11: 5 ms
Clear PROCHOT pulse when (0x3C[5] = 1).
PROCHOT Pulse Clear
[2] 0: Clear PROCHOT pulse and drive PROCHOT pin HIGH
(PROCHOT_CLEAR)
1: Idle (default at POR)
Maximum INOM deglitch time. INOM threshold is 110% of DPM in REG0x3F(). Measure current between ACP
INOM Deglitch Time and ACN. Trigger when the current is above this threshold.
[1]
(INOM_DEG) 0: 1 ms (max) (default at POR)
1: 15 ms (max)
INOM current threshold as percentage of DPM in REG0x3F().
INOM Threshold
[0] 0: 110% (default at POR)
(INOM_VTH)
1: 106%

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6.6.7 ProchotOption1 Register

Figure 6-11. ProchotOption1 Register (0x3D)
15 14 13 12 11 10 9 8
IDCHG_VTH IDCHG_DEG
R/W R/W

7 6 5 4 3 2 1 0
Reserved PROCHOT_PROFILE
R R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-11. ProchotOption1 Register (0x3D)

BIT BIT NAME DESCRIPTION
6 bit, range, range 0 A to 32256 mA, step 512 mA. Measure current between SRN and SRP. Trigger when the
IDCHG Threshold
[15:10] discharge current is above the threshold.
(IDCHG_VTH)
Default: 16384 mA (100000)
Typical IDCHG deglitch time.
00: 1.6 ms
IDCHG Deglitch Time
[9:8] 01: 100 µs (default at POR)
(IDCHG_DEG)
10: 6 ms
11: 12 ms
[7] Reserved 0 - Reserved
When adapter is present, the PROCHOT function is enabled by the below bits.
When adapter is removed, ICRIT, INOM, BATPRES, and ACOK functions are automatically disabled in the
PROCHOT profile. Comparator, IDCHG, and VBATT function settings are preserved. When all the bits are 0,
PROCHOT function is disabled.
Bit 6: Independent comparator, 0: disable (default at POR); 1: enable
PROCHOT Profile Enable
[6:0] Bit 5: ICRIT, 0: disable; 1: enable (default at POR)
(PROCHOT_PROFILE)
Bit 4: INOM, 0: disable (default at POR); 1: enable
Bit 3: IDCHG, 0: disable (default at POR); 1: enable
Bit 2: VBATT, 0: disable (default at POR); 1: enable
Bit 1: BATPRES, 0: disable (default at POR) ; 1: enable (one-shot rising edge triggered)
Bit 0: ACOK, 0: disable (default at POR) ; 1: enable (one-shot falling edge triggered)

6.6.8 ProchotStatus Register

Figure 6-12. ProchotStatus Register (0x3A)
15 14 13 12 11 10 9 8
Reserved
R

7 6 5 4 3 2 1 0
Reserved PROCHOT_STAT[6:0]
R R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-12. ProchotStatus Register (0x3A)

BIT BIT NAME DESCRIPTION
[15:7] Reserved 0 - Reserved
The status of all events triggered during the same PROCHOT pulse are set to 1. The register resets when either
of below two conditions occurs.
• Host first read after PROCHOT goes high
• PROCHOT goes low to start another pulse.
PROCHOT status Bit 6: Independent comparator, 0: Not triggered; 1: Triggered
[6:0]
(PROCHOT_STAT) Bit 5: ICRIT, 0: Not triggered; 1: Triggered
Bit 4: INOM, 0: Not triggered; 1: Triggered
Bit 3: IDCHG, 0: Not triggered; 1: Triggered
Bit 2: VBATT, 0: Not triggered; 1: Triggered
Bit 1: BATPRES, 0: Not triggered ; 1: Triggered
Bit 0: ACOK, 0: Not triggered ; 1: Triggered

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6.6.9 Charge Current Register

Figure 6-13. Charge Current Register (0x14)
15 14 13 12 11 10 9 8
Reserved DACICHG[6:2]
R R/W

7 6 5 4 3 2 1 0
DACICHG[1:0] Reserved
R/W R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-13. Charge Current Register (0x14), Using 10-mΩ Sense Resistor
BIT BIT NAME DESCRIPTION
15 Not used; 1 = invalid write
14 Not used; 1 = invalid write
13 Not used; 1 = invalid write
0 = Adds 0 mA of charger current
12 Charge Current, DACICHG 6
1 = Adds 4096 mA of charger current
0 = Adds 0 mA of charger current
11 Charge Current, DACICHG 5
1 = Adds 2048 mA of charger current
0 = Adds 0 mA of charger current
10 Charge Current, DACICHG 4
1 = Adds 1024 mA of charger current
0 = Adds 0 mA of charger current
9 Charge Current, DACICHG 3
1 = Adds 512 mA of charger current
0 = Adds 0 mA of charger current
8 Charge Current, DACICHG 2
1 = Adds 256 mA of charger current
0 = Adds 0 mA of charger current
7 Charge Current, DACICHG 1
1 = Adds 128 mA of charger current
0 = Adds 0 mA of charger current
6 Charge Current, DACICHG 0
1 = Adds 64 mA of charger current
5 Not used; value ignored
4 Not used; value ignored
3 Not used; value ignored
2 Not used; value ignored
1 Not used; value ignored
0 Not used; value ignored

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6.6.10 Charge Voltage Register

Figure 6-14. Charge Voltage Register (0x15)
15 14 13 12 11 10 9 8
Reserved DACV[10:4]
R R/W

7 6 5 4 3 2 1 0
DACV[3:0] Reserved
R/W R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-14. Charge Voltage Register (0x15)

BIT BIT NAME DESCRIPTION
15 Not used; 1 = invalid write
0 = Adds 0 mV of charger voltage
14 Charge voltage, DACV 10
1 = Adds 16384 mV of charger voltage
0 = Adds 0 mV of charger voltage
13 Charge voltage, DACV 9
1 = Adds 8192 mV of charger voltage
0 = Adds 0 mV of charger voltage
12 Charge voltage, DACV 8
1 = Adds 4096 mV of charger voltage
0 = Adds 0 mV of charger voltage
11 Charge voltage, DACV 7
1 = Adds 2048 mV of charger voltage
0 = Adds 0 mV of charger voltage
10 Charge voltage, DACV 6
1 = Adds 1024 mV of charger voltage
0 = Adds 0 mV of charger voltage
9 Charge voltage, DACV 5
1 = Adds 512 mV of charger voltage
0 = Adds 0 mV of charger voltage
8 Charge voltage, DACV 4
1 = Adds 256 mV of charger voltage
0 = Adds 0 mV of charger voltage
7 Charge voltage, DACV 3
1 = Adds 128 mV of charger voltage
0 = Adds 0 mV of charger voltage
6 Charge voltage, DACV 2
1 = Adds 64 mV of charger voltage
0 = Adds 0 mV of charger voltage
5 Charge voltage, DACV 1
1 = Adds 32 mV of charger voltage
0 = Adds 0 mV of charger voltage
4 Charge voltage, DACV 0
1 = Adds 16 mV of charger voltage
3 Not used; value ignored
2 Not used; value ignored
1 Not used; value ignored
0 Not used; value ignored

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6.6.11 Discharge Current Register

Figure 6-15. Discharge Current Register (0x39)
15 14 13 12 11 10 9 8
Reserved DACIDCHG Reserved
R R/W R

7 6 5 4 3 2 1 0
Reserved
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-15. Discharge Current Register (0x39), Using 10-mΩ Sense Resistor
BIT BIT NAME DESCRIPTION
15 Not used; 1 = invalid write
0 = Adds 0 mA of discharge current
14 Discharge current, DACIDCHG 5
1 = Adds 16384 mA of discharge current
0 = Adds 0 mA of discharge current
13 Discharge current, DACIDCHG 4
1 = Adds 8192 mA of discharge current
0 = Adds 0 mA of discharge current
12 Discharge current, DACIDCHG 3
1 = Adds 4096 mA of discharge current
0 = Adds 0 mA of discharge current
11 Discharge current, DACIDCHG 2
1 = Adds 2048 mA of discharge current
0 = Adds 0 mA of discharge current
10 Discharge current, DACIDCHG 1
1 = Adds 1024 mA of discharge current
0 = Adds 0 mA of discharge current
9 Discharge current, DACIDCHG 0
1 = Adds 512 mA of discharge current
8 Not used; value ignored
7 Not used; value ignored
6 Not used; value ignored
5 Not used; value ignored
4 Not used; value ignored
3 Not used; value ignored
2 Not used; value ignored
1 Not used; value ignored
0 Not used; value ignored

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6.6.12 Minimum System Voltage Register

Figure 6-16. Minimum System Voltage Register (0x3E)
15 14 13 12 11 10 9 8
Reserved DACVS
R R/W

7 6 5 4 3 2 1 0
Reserved
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-16. Minimum System Voltage Register (0x3E)

BIT BIT NAME DESCRIPTION
15 Not used; 1 = invalid write
14 Not used; 1 = invalid write
0 = Adds 0 mV of charger voltage
13 Minimum system voltage, DACVS5
1 = Adds 8192 mV of charger voltage
0 = Adds 0 mV of charger voltage
12 Minimum system voltage, DACVS4
1 = Adds 4096 mV of charger voltage
0 = Adds 0 mV of charger voltage
11 Minimum system voltage, DACVS3
1 = Adds 2048 mV of charger voltage
0 = Adds 0 mV of charger voltage
10 Minimum system voltage, DACVS2
1 = Adds 1024 mV of charger voltage
0 = Adds 0 mV of charger voltage
9 Minimum system voltage, DACVS1
1 = Adds 512 mV of charger voltage
0 = Adds 0 mV of charger voltage
8 Minimum system voltage, DACVS0
1 = Adds 256 mV of charger voltage
7 Not used; value ignored
6 Not used; value ignored
5 Not used; value ignored
4 Not used; value ignored
3 Not used; value ignored
2 Not used; value ignored
1 Not used; value ignored
0 Not used; value ignored

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6.6.13 Input Current Register

Figure 6-17. Input Current Register (0x3F)
15 14 13 12 11 10 9 8
Reserved DACIIN[6:2]
R R/W

7 6 5 4 3 2 1 0
DACIIN[1:0] Reserved
R/W R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-17. Input Current Register (0x3F), Using 10-mΩ Sense Resistor
BIT BIT NAME DESCRIPTION
15 Not used; 1 = invalid write
14 Not used; 1 = invalid write
13 Not used; 1 = invalid write
0 = Adds 0 mA of input current
12 Input current, DACIIN 6
1 = Adds 4096 mA of input current
0 = Adds 0 mA of input current
11 Input current, DACIIN 5
1 = Adds 2048 mA of input current
0 = Adds 0 mA of input current
10 Input current, DACIIN 4
1 = Adds 1024 mA of input current
0 = Adds 0 mA of input current
9 Input current, DACIIN 3
1 = Adds 512 mA of input current
0 = Adds 0 mA of input current
8 Input current, DACIIN 2
1 = Adds 256 mA of input current
0 = Adds 0 mA of input current
7 Input current, DACIIN 1
1 = Adds 128 mA of input current
0 = Adds 0 mA of input current
6 Input current, DACIIN 0 1 = Adds 64 mA of input current
Refer to Table 6-2 for allowed conditions to set this bit to 1.
5 Not used; value ignored
4 Not used; value ignored
3 Not used; value ignored
2 Not used; value ignored
1 Not used; value ignored
0 Not used; value ignored

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6.6.14 Register Exceptions

Certain system events, such as adapter or battery removal, introduce a response within the register set, such
as to reset one or more fields to their POR value. Table Table 6-18 provides a list of register fields and their
response to such system events.
Table 6-18. Register Exceptions
REGISTER ACDET < BATPRES EN_PKPWR=
FIELD NAME BATDEPL UNDERVALUE OVERVALUE
FIELD 2.4V High 1
0x12H [5] LEARN_EN POR Value, POR Value, POR Value,
Write Ignored Write Ignored Write Ignored
0x38H [6] EN_BATT_BOOST POR Value if
Boost Active
0x37H [2] EN_HYBRID_BOOST POR Value
0x38H [15:14] PKPWR_TOVLD Write ignored
0x38H [9:8] PKPWR_TMAX Write ignored
0x14H ICHG POR Value POR Value 64 mA treated Write ignored
as 0
0x15H VCHG POR Value Write ignored Write ignored
0x39H IDCHG Write ignored Write ignored
0x3EH VSysMin Write ignored Write ignored
0x3FH IDPM Write ignored Write ignored

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Application Information

The BQ24800EVM evaluation module (EVM) is a complete charger module for evaluating the BQ24800. The
application curves were taken using the BQ24800EVM. Refer to the BQ24800 EVM User's Guide for EVM
information.
7.2 Typical Applications
Two typical applications are provided in this section. The first is a battery charging system that supports
Battery-only Boost, see Figure 7-1. The second is a battery charging system that does not support battery-only
boost, see Figure 7-22. For details on the operation of battery-only boost mode, refer to Section 6.4.3.
7.2.1 Typical System Schematic
Applications that use the battery-only boost function require that VCC be powered by a diode selector between
the adapter input and the system rail as shown with the D1 and D2 components in Figure 7-1. It is important that
VCC be powered from the system rail instead of directly from the battery in systems that support battery-only
boost mode. During heavy load conditions while operating in battery-only boost mode, the current draw from
the battery may cause the voltage as measured at the SRN pin to drop below the level required to support
the switching regulator. By powering VCC instead from the system rail, it provides a sufficient voltage to the
converter in this condition. Note that, in this configuration, initial power-up of the device from battery insert
without an adapter incurs a voltage drop across the body diode of the Q3 switch in addition to the voltage drop
across the D2 Schottky diode. For a partially-charged 1-S lithium-ion battery, this additional voltage drop across
the Q3 backgate diode may drop the voltage at VCC below the under-voltage lockout. For this reason, this
configuration should not be used with a 1-S lithium-ion battery.

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Adapter RAC System

Q1 Q2 10 m

C3A
C1 C2 0.1 …F D1 D2
R1 1 nF 47 nF (optional)
2 C4 C5
C3 0.1 …F 0.1 …F C6 CIN
R6 CSYS
C1 0.1 …F 1 …F 20 …F
10 80 …F
2.2 …F

VCC
R4 R5 ACN Q3
4.02 k 4.02 k
ACP R7: 4.02 k
BATDRV
R8: 10
CMSRC BATSRC
R2 ACDRV Q4
866 k HIDRV
ACDET 2-4S
3.3V BTST C7 L1 RSR Battery
R3 1.05V 47 nF 3.3 …+ 10 m
133 k
R10: 10 k

R11: 10 k

R12: 10 k

R13: 10 k
BQ24800
R9: 500

PHASE
C8 C9 C10
Q5 0.1 …F 0.1 …F 0.1 …F
LODRV CBATT
SDA
20 …F
SMBus PGND
SCL
R14: 10
ACOK
SRP
Dig I/O BST_STAT
SRN
R15: 10
PROCHOT From battery
BATPRES
IADPT connector
REGN
A/D IDCHG C13 3V3
2.2 uF
PMON R17
CMPOUT
CMPIN

316 k
Host R16 C11 C12 ILIM
30.1 k 100 pF 100 pF R18
100 k

Figure 7-1. Typical System Schematic

7.2.1.1 Design Requirements

Table 7-1. Design Requirements
DESIGN PARAMETER EXAMPLE VALUE
Input Voltage(2) 17.7 V < Adapter Voltage < 24 V
Input Current Limit(2) 3.2 A for 65-W adapter
Battery Charge Voltage(1) 12592 mV for 3-s battery
Battery Charge Current(1) 4096 mA for 3-s battery
Battery Discharge Current(1) 10240 mA for 3-s battery supporting battery only boost mode

(1) Refer to battery specification for settings.

(2) Refer to adapter specification for settings for Input Voltage and Input Current Limit.
7.2.1.2 Detailed Design Procedure
The parameters are configurable using the evaluation software.
The simplified application circuits (see Figure 7-1 and Figure 7-22) show the minimum capacitance requirements
for each pin. Inductor, capacitor, and MOSFET selection and are explained in the rest of this section. Refer to the
BQ24800 EVM User's Guide for the full application schematic.
7.2.1.2.1 Adapter Current Sense Filter
To improve common-mode and differential-mode noise rejection for the adapter current sensing across the
RAC sense resistor, 0.1 µF C3, C4 and C5 capacitors are placed at ACP and ACN. For 2S lithium-ion battery
applications, an additional 0.1 µF capacitor may be placed at C3A location in parallel with C3 for improved
filtering. The C3A capacitor is not recommended for 3S or 4S battery applications.

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7.2.1.2.2 Negative Output Voltage Protection

Reversely inserting the battery pack into the charger output during production or hard shorts on battery to ground
will generate negative voltage on SRP, SRN, and BATSRC pins. IC internal electrostatic-discharge (ESD) diodes
from GND pin to SRP or SRN pins and two anti-parallel (AP) diodes between SRP and SRN pins can be forward
biased and negative current can pass through the ESD diodes and AP diodes when output has negative voltage,
potentially damaging the IC. Small resistors for SRP, SRN and BATSRC (R12-R14) limit the negative current into
these pins. The suggested resistor value is 10 Ω for the SRP, SRN, and BATSRC pins.
7.2.1.2.3 Reverse Input Voltage Protection
Q6, R12, and R13 in Figure 7-2 give system and IC protection from reversed adapter voltage. In normal
operation, Q6 is turned off by negative Vgs. When adapter voltage is reversed, Q6 Vgs is positive. As a result,
Q6 turns on to short gate and source of Q2 so that Q2 is off. Q2 body diode blocks negative voltage to system.
However, CMSRC and ACDRV pins need R3 and R4 to limit the current due to the ESD diode of these pins
when turned on. Q6 must have low Vgs threshold voltage and low Qgs gate charge so that it turns on before
Q2. R3 and R4 must have sufficient power rating for the power dissipation when the ESD diode is on. If Q1 is
replaced by Schottky diode for reverse adapter voltage protection, Q2, R3 and R4 are not needed.

Reverse Q6
Input R12 BSS138W
Protection 1M R13
3.01M

Q1 (ACFET) Q2 (RBFET) RAC 10mW

Adapter +
Ri C1 C2
2W 1nF 47nF
C3 C5
Ci
Adapter - 0.1mF 0.1mF
2.2mF

C4 ACN
0.1mF
R3 R4 U1
4.02k 4.02k ACP BQ24800

CMSRC

ACDRV
R1
430k
ACDET
R2
66.5k

Figure 7-2. Reverse Input Voltage Protection Circuit

7.2.1.2.4 Reduce Battery Quiescent Current

When the adapter is not present, if VCC is powered with voltage higher than UVLO directly or indirectly (such
as through a LDO or switching converter) from battery, the internal BATFET charge pump gives the BATFET
pin 6-V higher voltage than the SRN pin to drive the n-channel BATFET. As a result, the battery has higher
quiescent current. This is only necessary when the battery powers the system due to a high system current
that goes through the MOSFET channel instead of the body diode to reduce conduction loss and extend the
battery working life. When the system is totally shutdown, it is not necessary to let the internal BATFET charge
pump work. The host controller can turn off the switches in the battery pack to disconnect the battery from the
system. Some packs may wake up again if the voltage on SRN pin stays above pack UVLO too long. By setting
ChargeOption1() bit[1] to 1, host can enable current source inside charger IC to discharge the SRN pin quickly.
As a result, the system is discharged down to zero to minimize the quiescent current.
7.2.1.2.5 CIN Capacitance
CIN provides input capacitance when the converter is operating in forward buck charging mode. This should
have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is

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half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then
the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and can be estimated by
Equation 6:

ICIN = ICHG ´ D × (1 - D)
(6)

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed as close as possible to the drain of the high side switching MOSFET (HIFET). The voltage rating of the
capacitor must be higher than normal input voltage level. 25-V rating or higher capacitor is preferred for 19- V to
20-V input voltage. 10- to 20-μF capacitance is suggested for typical of 3- to 4-A charging current.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage
is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's data
sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to get the required value at the operating point.
7.2.1.2.6 L1 Inductor Selection
The BQ24800 has four selectable fixed switching frequencies. Higher switching frequency allows the use of
smaller inductor and capacitor values but decreases efficiency and increases EMI. Inductor saturation current
should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):

ISAT ³ ICHG + (1/2) IRIPPLE (7)

The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fS)
and inductance (L):

VIN ´ D ´ (1 - D)
IRIPPLE =
fS ´ L (8)

The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging
voltage range is from 9V to 12.6V for 3-cell battery pack. For 20-V adapter voltage, 10-V battery voltage gives
the maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12-V to
16.8-V, and 12-V battery voltage gives the maximum inductor ripple current.
Usually inductor ripple is designed in the range of (20-40%) maximum charging current as a trade-off between
inductor size and efficiency for a practical design. Refer to the Section 7.2.1.2.8 section for recommended
inductor value by charging current and switching frequency.
7.2.1.2.7 CBATT Capacitance
CBATT is the output capacitor for buck charging mode and should have enough ripple current rating to absorb
output switching ripple current. The output capacitor RMS current is given:

IRIPPLE
ICOUT = » 0.29 ´ IRIPPLE
2 ´ 3 (9)

The BQ24800 has internal loop compensator. To get good loop stability, the resonant frequency of the inductor
and CBATT should be designed between 10 kHz and 20 kHz. The preferred ceramic capacitor is 25V X7R or X5R
for capacitor. Refer to the Section 7.2.1.2.8 section for recommended CBATT capacitor value by charge current
and switching frequency. Place the capacitors after charging current sensing resistor to get the best charge
current regulation accuracy.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias
voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead

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to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the
manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose
a higher voltage rating or nominal capacitance value in order to get the required value at the operating point.
7.2.1.2.8 Buck Charging Internal Compensation
The synchronous buck PWM converter uses a fixed frequency voltage control scheme and internal type III
compensation network. The LC output filter gives a characteristic resonant frequency:

(10)

The resonant frequency, fo, is used to determine the compensation to ensure there is sufficient phase margin
for the target bandwidth. The LC output filter should be selected to give a resonant frequency of 10- to 20-kHz
nominal for the best performance. Suggested component values for different ChargeCurrent() REG0x14 settings
are shown in Table 7-2 to Table 7-3 for the available switching frequencies of 300 - 800 kHz. Note that these
tables are generated based on the charging configuration, so the Output Capacitor is the capacitance at the
battery connection, close to the SRN node of the battery charging sense resistor. The procedure for generating
these tables is to first select the inductor value to have a ripple current that is in the range of 20 - 40% of the
target charge current. Once the inductor value has been calculated, the output capacitance is chosen to have an
output stage resonant frequency between 10- to 20-kHz.
Table 7-2. Suggested Component Values by Charge Current for 600-kHz and 800-kHz (Default) Switching
Frequencies
CHARGE CURRENT 2A 3A 4A 6A 8A
L1 (µH) 6.8 or 8.2 5.6 or 6.8 3.3 or 4.7 3.3 2.2
CBATT (µF) 20 20 20 30 40
(Effective after derating)

Table 7-3. Suggested Component Values by Charge Current for 300-kHz and 400-kHz Switching
Frequencies
CHARGE CURRENT 3A 4A 5A 6A 8A
L1 (µH) 10 6.8 or 8.2 6.8 5.6 4.7
CBATT (µF) 15 20 20 20 20
(Effective after derating)

Ceramic capacitors show a DC-bias effect. This effect reduces the effective capacitance when a DC-bias
voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead
to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the
manufacturer's data sheet about the performance with a DC bias voltage applied. It may be necessary to choose
a higher voltage rating or nominal capacitance value to get the required value at the operating point.
7.2.1.2.9 CSYS Capacitance
CSYS capacitance combines with CIN to provide output capacitance when BQ24800 is operating in battery only
boost mode and provides bulk capacitance in all modes to support fast load transients on SYS. The distinction
between CIN and CSYS is that CIN is ceramic capacitor only and must be placed very close to the high side
switching MOSFET Q4. CSYS may be a mixture of ceramic and tantalum capacitors and does not have as tight of
a placement requirement.
If battery only boost mode is supported, the sum of ( CSYS + CIN) is chosen according to the internal
compensation requirement of the Section 7.2.1.2.8 section.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage
is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's data

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sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to get the required value at the operating point.
7.2.1.2.10 Battery Only Boost Internal Compensation
The synchronous boost PWM converter uses a fixed frequency voltage control scheme and internal type III
compensation network. The LC output filter has a characteristic resonant frequency:

(11)

The resonant frequency, fo, is used to determine the compensation to ensure there is sufficient phase margin
for the target bandwidth. The LC output filter should be selected to give a resonant frequency of 3.5- to 6.0-kHz
nominal for the best performance. Suggested output capacitance versus inductor is shown in Table 7-4. The
designer should first determine the inductor value using the tables provided in Section 6.4.6, then use Table 7-4
to determine the appropriate battery only boost output capacitance using that inductor value. These tables are
generated based on the battery-only boost configuration, so the output capacitance is measured at the system
node, which is the sum of CIN and CSYS as shown on Figure 7-1. The minimum capacitance value is calculated
using boost ratio (VSYS / VBATT = VO / VIN) of 1.5 and a resonant frequency of 6.0 kHz. Also, a minimum output
capacitance of 60 µF is recommended regardless of resonant frequency to support the transient response. Table
7-4 shows the minimum suggested value. Additional CSYS may be added for improved transient response.
Table 7-4. Suggested Minimum Component Value for Battery-Only Boost Operation
L1 (µH) 2.2 3.3 4.7 5.6 6.8 8.2
CIN (µF) 20 20 20 20 20 20
(Effective after derating)
Minimum CSYS(µF) 120 80 50 40 40 40
(Effective after derating)

7.2.1.2.11 Power MOSFETs Selection

Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6V of gate drive voltage. 30 V or higher voltage rating MOSFETs are
preferred for 19- to 20-V input voltage.
Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction
loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance,
RDS(ON), and the gate-to-drain charge, QGD. For the bottom side MOSFET, FOM is defined as the product of the
MOSFET's on-resistance, RDS(ON), and the total gate charge, QG.

FOMtop = RDS(on) x QGD; FOMbottom = RDS(on) x QG (12)

The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D=VOUT/
VIN), charging current (ICHG), MOSFET's on-resistance (RDS(ON)), input voltage (VIN), switching frequency (fS),
turn on time (ton) and turn off time (toff):

1
Ptop = D ´ ICHG2 ´ RDS(on) + ´ VIN ´ ICHG ´ (t on + t off ) ´ f s
2 (13)

The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100°C junction
temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are
given by:

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QSW Q
t on = , t off = SW
Ion Ioff (14)

where Qsw is the switching charge, Ion is the turn-on gate driving current and Ioff is the turn-off gate driving
current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge
(QGD) and gate-to-source charge (QGS):

1
QSW = QGD + ´ QGS
2 (15)

Gate driving current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on
gate resistance (Ron) and turn-off gate resistance (Roff) of the gate driver:

VREGN - Vplt Vplt

Ion = , Ioff =
Ron Roff (16)

The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous conduction mode:

Pbottom = (1 - D) x ICHG 2 x RDS(on) (17)

When charger operates in non-synchronous mode, the bottom-side MOSFET is off. As a result all the
freewheeling current goes through the body-diode of the bottom-side MOSFET. The body diode power loss
depends on its forward voltage drop (VF), non-synchronous mode charging current (INONSYNC), and duty cycle
(D).

PD = VF x INONSYNC x (1 - D) (18)

The maximum charging current in non-synchronous mode can be up to 0.25 A for a 10-mΩ charging current
sensing resistor or 0.5 A if battery voltage is below 2.5 V. The minimum duty cycle happens at lowest battery
voltage. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the
maximum non-synchronous mode charging current.
7.2.1.2.12 Input Filter Design
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second
order system. The voltage spike at VCC pin maybe beyond IC maximum voltage rating and damage IC. The
input filter must be carefully designed and tested to prevent over voltage event on VCC pin.
There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic
capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin
voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level.
However these two solutions may not have low cost or small size.
A cost effective and small size solution is shown in Figure 7-3. The R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is
used for reverse voltage protection for VCC pin. C2 is VCC pin decoupling capacitor and it should be place to
VCC pin as close as possible. C2 value should be less than C1 value so R1 can dominate the equivalent ESR
value to get enough damping effect. R2 is used to limit inrush current of D1 to prevent D1 getting damage when
adapter hot plug-in. R2 and C2 should have 10us time constant to limit the dv/dt on VCC pin to reduce inrush
current when adapter hot plug in. R1 has high inrush current. R1 package must be sized enough to handle
inrush current power loss according to resistor manufacturer’s data sheet. The filter components value always
need to be verified with real application and minor adjustments may need to fit in the real application circuit.

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D1
R2(1206)
R1(2010) 10-20W
Adapter 2W
connector VCC pin
C1
2.2mF C2
0.47-1mF

Figure 7-3. Input Filter

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7.2.1.3 Application Curves

No Battery VBAT = 11 V

Figure 7-4. VCC, ACDET, REGN, and ACOK During Figure 7-5. Power On ACOK Delay at 1st and 2nd
Power Up Adapter Plug-in

Figure 7-6. Charge Enable With Soft Start Figure 7-7. Charge Disabled by ILIM

Figure 7-8. Hybrid Power Boost Mode Enabled Figure 7-9. Hybrid Power Boost Mode Doisabled by
ILIM

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Figure 7-10. Converter in Continuous Conduction Figure 7-11. Converter in Discontinuous

Mode (CCM) During Charging Conduction Mode (DCM) During Charging

Figure 7-12. Converter in Continuous Conduction IDPM 4096 mA ICHG 2432 mA VBAT 11 V
Mode During Hybrid Power Boost Mode Figure 7-13. Converter in Discontinuous
Conduction Mode During Hybrid Power Boost
Mode

VIN = 19.5 V IDPM = 3072 mA VBAT = 11 V VIN = 19.5 V IDPM = 2048 mA VBAT 11 V
ICHG = 2048 mA
Figure 7-15. Hybrid Power Boost Mode With
Figure 7-14. Input Current Regulation During Charge Enable
System Load Transient

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VIN = 19.5 V IDPM = 2048 mA ICHG = 2048 mA VIN = 19.5 V IDPM = 2560 mA VBAT = 11 V
VBAT = 11 V ICRIT 120% x IDPM ICHG = 2 A IDCHG = 2048 mA
PROCHOT pulsewidth 0x3C[4:3] = 11
Figure 7-17. Hybrid Power Boost Mode With
Figure 7-16. Hybrid Power Boost Mode with Discharge Current Regulation
Charge Enable, PROCHOT Asserted

VIN = 19.5 V VBAT = 12 V ISYS = 6.0 A VIN = 19.5 V VBAT = 12 V ISYS = 6.0 A
ILIM1 = 4096 mA ILIM2 = 8192 mA ILIM1 = 4096 mA ILIM2 = 8192 mA

Figure 7-18. Peak Power Mode with Figure 7-19. Peak Power Mode with
PKPWR_ENCHRG=0 PKPWR_ENCHRG=1

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VBATT = 12.0 V to VSysMin() = 10.240 VBOOST = 2.3 V VBATT = 9.0 V VSysMin() = 10.24 VBOOST = 2.3 V
6.0 V V V
ISYS = 1.0 A ISYS = 3.0 A VADPT = 20 V

Figure 7-20. Battery Only Boost Entry and Exit by Figure 7-21. Battery Only Boost Exit by Adapter
Battery Voltage Plug In

7.2.2 Migration from Previous Devices (Does not Support Battery Only Boost)
The system schematic shown in Figure 7-22 is compatible with the previous generation BQ24780S. The
BQ24800 may be used in this system configuration; however, this system configuration does not support the
battery only boost mode. The requirements for systems that do not operate in battery only boost are slightly
relaxed. Firstly, less capacitance is required at CSYS. Secondly, the VCC diode selector (D1 and D2) may be
configured to select between the adapter input and battery input. Because this provides a path directly from the
battery to VCC across a single Schottky diode, this configuration may be used in a 1-S lithium-ion battery system
in addition to 2-S, 3-S and 4-S lithium-ion battery systems.

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Adapter RAC System

Q1 Q2 10 m

C3A
C1 C2 0.1 …F D1 D2
R1 1 nF 47 nF (optional)
2 C4 C5
C3 0.1 …F 0.1 …F C6 CIN CSYS
R6
C1 0.1 …F 1 …F 20 …F 20 …F
10
2.2 …F

VCC
R4 R5 ACN Q3
4.02 k 4.02 k
ACP R7: 4.02 k
BATDRV
R8: 10
CMSRC BATSRC
R2 ACDRV Q4
866 k HIDRV
ACDET 1-4S
3.3V BTST C7 L1 RSR
R3 1.05V 47 nF 3.3 …+ 10 m
Battery
133 k
R10: 10 k

R11: 10 k

R12: 10 k

R13: 10 k
BQ24800
R9: 500

PHASE
C8 C9 C10
Q5 0.1 …F 0.1 …F 0.1 …F
LODRV CBATT
SDA
20 …F
SMBus PGND
SCL
R14: 10
ACOK
SRP
Dig I/O BST_STAT
SRN
PROCHOT R15: 10 From battery
BATPRES
IADPT connector
REGN
A/D IDCHG C13 3V3
2.2 uF R17
PMON
CMPOUT

316 k
CMPIN

Host R16 C11 C12 ILIM

30.1 k 100 pF 100 pF R18
100 k

Figure 7-22. Typical System Schematic for Migrating from BQ24780S. Does not support battery only
boost.

7.2.2.1 Design Requirements

Table 7-5. Design Requirements
DESIGN PARAMETER EXAMPLE VALUE
Input Voltage(1) 17.7 V < Adapter Voltage < 24 V
Input Current Limit(1) 3.2 A for 65-W adapter
Battery Charge Voltage(2) 12592 mV for 3-s battery
Battery Charge Current(2) 4096 mA for 3-s battery
Battery Discharge Current(2) 6144 mA for 3-s battery

(1) Refer to battery specification for settings.

(2) Refer to adapter specification for settings for Input Voltage and Input Current Limit.
7.2.2.2 Detailed Design Procedure
Refer to Section 7.2.1.2 for the detailed design procedures for all components except CSYS.
7.2.2.2.1 CSYS Capacitance
CSYS capacitance combines with CIN to provide bulk capacitance in all modes to support fast load transients on
SYS. The distinction between CIN and CSYS is that CIN is ceramic capacitor only and must be placed very close
to the high side switching MOSFET Q4. CSYS may be a mixture of ceramic and tantalum capacitors and does not
have as tight of a placement requirement.

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When battery only boost mode is not supported the value of CSYS should be chosen according to the decoupling
requirements of the system load. A minimum of 20-µF is recommended in addition to the capacitance supplied at
CIN.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage
is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's data
sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to get the required value at the operating point.
7.2.2.3 Application Curves
Refer to Section 7.2.1.3 for the application curves.

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8 Power Supply Recommendations

When adapter is attached, and ACOK goes HIGH, the system is connected to adapter through ACFET/RBFET.
An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. If battery only boost
mode is not used, the adapter detect threshold must be set to a value greater than the maximum battery voltage,
but lower than the minimum allowed adapter voltage. If battery only boost mode is used, the adapter detect
threshold must instead be set to a value greater than the battery boost regulation voltage as determined by
REG0x3E and REG0x38[5].
When adapter is removed, the system is connected to battery through BATFET. Typically the battery depletion
threshold should be greater than the minimum system voltage so that the battery capacity can be fully utilized for
maximum battery life.

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9 Layout
9.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 9-1) is important to prevent electrical
and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout of PCB according to this specific order is essential.
1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use
shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on
different layers and using vias to make this connection.
2. The IC should be placed close to the switching MOSFET’s gate pins and keep the gate drive signal traces
short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching MOSFETs.
3. Place inductor input pin to switching MOSFET’s output pin as close as possible. Minimize the copper area
of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance
from this area to any other trace or plane.
4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area) and do not route the sense leads through a high-current path (see Figure 9-2 for Kelvin connection for
best current accuracy). Place decoupling capacitor on these traces next to the IC
5. Place output capacitor next to the sensing resistor output and ground
6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC
use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling
8. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using power pad as the single ground
connection point. Or using a 0-Ω resistor to tie analog ground to power ground (power pad should tie to
analog ground in this case if possible).
9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible
10. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
11. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the
WQFN information, See Quad Flatpack No-Lead Logic Packages Application Report and QFN and SON PCB
Attachment Application Report.
9.2 Layout Examples
9.2.1 Layout Consideration of Current Path

PHASE L1 R1 VBAT

High
VIN Frequency BAT
Current
Path GND C2
C1

Figure 9-1. High Frequency Current Path

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9.2.2 Layout Consideration of Short Circuit Protection

Charge Current Direction
R SNS

To Inductor To Capacitor and battery

Current Sensing Direction

To SRP and SRN pin

Figure 9-2. Sensing Resistor PCB Layout

9.2.3 Layout Consideration for Short Circuit Protection

The BQ24800 has a unique short circuit protection feature. Its cycle-by-cycle current monitoring feature is
achieved through monitoring the voltage drop across RDS(on) of the MOSFETs after a certain amount of blanking
time. For a MOSFET short or inductor short circuit, the over current condition is sensed by two comparators, and
two counters are triggered. After seven occurrences of a short circuit event, the charger will be latched off. To
reset the charger from latch-off status, remove and then reconnect the adapter. Figure 9-3 shows the BQ24800
short circuit protection block diagram.
Adapter

ACP RAC ACN R BTST High-Side

PCB
MOSFET
SCP1 PHASE

REGN L RDC Battery

COMP1 SCP2 Low-Side

COMP2 C
MOSFET

Count to 7 Latch off

Adapter
Plug in Charger
CLR
Copyright © 2016, Texas Instruments Incorporated

Figure 9-3. Block Diagram of BQ24800 Short Circuit Protection

In normal operation, the low side MOSFET current is from source to drain which generates a negative voltage
drop when it turns on, as a result the over current comparator can not be triggered. When the high side switch
short circuit or inductor short circuit happens, the large current of low side MOSFET is from drain to source
and can trigger low side switch over current comparator. The BQ24800 senses the low side switch voltage drop
through the PHASE pin and GND pin.
The high-side FET short is detected by monitoring the voltage drop between ACP and PHASE. As a result, it
not only monitors the high side switch voltage drop, but also the adapter sensing resistor voltage drop and PCB
trace voltage drop from ACN pin of R AC to charger high side switch drain. Usually, there is a long trance between
input sensing resistor and charger converting input, a careful layout will minimize the trace effect.
To prevent unintentional charger shut down in normal operation, MOSFET RDS(on) selection and PCB layout is
very important. Figure 9-4 shows a improvement PCB layout example and its equivalent circuit. In this layout,
the system current path and charger input current path is not separated, as a result, the system current causes
voltage drop in the PCB copper and is sensed by the IC. The worst layout is when a system current pull point
is after charger input; as a result all system current voltage drops are counted into over current protection

62 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

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 BQ24800
www.ti.com SLUSDO8A – MARCH 2020 – REVISED JANUARY 2025

comparator. The worst case for IC is when the total system current and charger input current sum equals the
DPM current. When the system pulls more current, the charger IC tries to regulate the RAC current as a constant
current by reducing the charging current.
IDPM
R AC System Path PCB Trace
System current ISYS
RAC RPCB
ICHRGIN
Charger input current
Charger Input PCB Trace
ACP ACN Charger IBAT

To ACP To ACN

(a) PCB Layout (b) Equivalent Circuit

Figure 9-4. PCB Layout Example

Figure 9-5 shows the optimized PCB layout example. The system current path and charge input current path
is separated, as a result the IC only senses charger input current caused PCB voltage drop and minimized the
possibility of unintentional charger shut down in normal operation. This also makes PCB layout easier for high
system current application.
R AC System Path PCB Trace IDPM
System current ISYS

Single point connection at RAC

RAC RPCB
Charger input current ICHRGIN

ACP ACN Charger IBAT

To ACP To ACN Charger Input PCB Trace

(a) PCB Layout (b) Equivalent Circuit

Figure 9-5. Optimized PCB Layout Example

The total voltage drop sensed by IC can be express as the following equation.

Vtop = RAC x IDPM + RPCB x (ICHRGIN + (IDPM - ICHRGIN) x k) + RDS(on) x IPEAK (19)

where the RAC is the AC adapter current sensing resistance, IDPM is the DPM current set point, RPCB is the PCB
trace equivalent resistance, ICHRGIN is the charger input current, k is the PCB factor, RDS(on) is the high side
MOSFET turn on resistance and IPEAK is the peak current of inductor. Here the PCB factor k equals 0 means the
best layout shown in Figure 9-5 where the PCB trace only goes through charger input current while k equals 1
means the worst layout shown in Figure 9-4 where the PCB trace goes through all the DPM current. The total
voltage drop must below the high side short circuit protection threshold to prevent unintentional charger shut
down in normal operation.
The low side MOSFET short circuit voltage drop threshold can be adjusted via SMBus command.
ChargeOption() bit[7] disables LSFET protection when set to 0 and enables the protectoin with a threshold
of 250 mV when set to 1. The high side MOSFET short circuit voltage drop threshold can be adjusted via
SMBus command. ChargeOption() bit[8] disables HSFET protection when set to 0 and enables the protection
with a threshold of 750 mV when set to 1. For a fixed PCB layout, host should set proper short circuit protection
threshold level to prevent unintentional charger shut down in normal operation.

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BQ24800
SLUSDO8A – MARCH 2020 – REVISED JANUARY 2025 www.ti.com

10 Device and Documentation Support

10.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following: BQ24800 EVM User's Guide
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
10.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Revision History

Changes from Revision * (March 2020) to Revision A (January 2025) Page

• Changed data sheet status from Restricted to Public........................................................................................ 1
• Updated ILIM1_ACC description in Electrical Characteristics table to add 800 kHz switching frequency and 8.4
V battery test cases by removing previously-listed frequency and battery voltage limiting conditions...............7
• Added Adapter Current Sense Filter section to provide additional detail on the optional C3A adapter current
sensing filter capacitor...................................................................................................................................... 47

64 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

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 BQ24800
www.ti.com SLUSDO8A – MARCH 2020 – REVISED JANUARY 2025

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 65

Product Folder Links: BQ24800
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Jan-2025

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

BQ24800RUYR ACTIVE WQFN RUY 28 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ Samples
24800
BQ24800RUYT ACTIVE WQFN RUY 28 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ Samples
24800

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Jan-2025

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 6-Jan-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ24800RUYR WQFN RUY 28 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
BQ24800RUYT WQFN RUY 28 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 6-Jan-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ24800RUYR WQFN RUY 28 3000 367.0 367.0 35.0
BQ24800RUYT WQFN RUY 28 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
RUY0028A WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK-NO LEAD

4.1 A
B 3.9

PIN 1 INDEX AREA 4.1

3.9

0.8
0.7
C

SEATING PLANE
0.05 0.08 C
0.00
SQ 2.6±0.1
2X 2.4

8 14

24X 0.4
7
15

2X 29 SYMM
2.4

28X 0.25
0.15
21 0.1 C A B
1
0.05 C

28 22
28X 0.5
0.3
SYMM

4219146/C 03/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RUY0028A WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK-NO LEAD

2X (3.8)
SQ (2.6)
2X (2.4)

28 22
28X (0.6)

28X (0.2)
1
21

24X (0.4)
29 SYMM 2X 2X
(2.4) (3.8)

2X (1.05)

7 15

(R0.05) TYP

(Ø0.2) VIA
TYP 8 14
2X (1.05)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND METAL UNDER
METAL SOLDER MASK
EXPOSED
METAL
SOLDER MASK
EXPOSED METAL SOLDER MASK
OPENING
OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219146/C 03/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RUY0028A WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK-NO LEAD

2X (3.8)
4X
SQ (1.15)

28 22
28X (0.6)

28X (0.2)
1 29
21

24X (0.4)
SYMM 2X
(3.8)
2X (0.675)

7 15

(R0.05) TYP

METAL TYP
8 14
2X (0.675)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 15X

4219146/C 03/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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