fco-lecture-8086

Introduction to 8086 Microprocessor
Unit – 11 (GTU Syllabus)
Chapter – 2 & 4

From the Book of
Sunil Mathur, © 2011 by PHI

Outline

Unit No. 11: Introduction to Intel 8086
Architecture
Chapter 2: Introduction to 8086
2.1. Introduction to 8086
2.2. The 8086 Microprocessor
2.2.1 BIU (BUS Interface Unit)
2.2.2 EU (Execution Unit)

Chapter 4: Instructions Set of 8086
4.1 Introduction to instructions set of
8086
4.2.1 Data Addressing Modes
4.3 Instruction Format
4.5. Instruction set of 8086
4.5.1 Data Transfer Instructions
4.5.2 Arithmetic Instructions
4.5.3 Logical Instructions

Outline

Chapter 2: Introduction to 8086
2.1. Introduction to 8086
2.2. The 8086 Microprocessor
2.2.1 BIU (BUS Interface Unit)
2.2.2 EU (Execution Unit)

2.1 Introduction to 8086
Microprocessor 8086 is next generation microprocessor and it is
completely different from its predecessor 8085. Microprocessor
8086 was introduced in 1978. Since its introduction, the
architecture of 8086, so-called X86 architecture has undergone
five major stages i.e. 8086, 8088, and 80186, 80188 are the
members of the first generation of 80X86 family. The next
generation are the 80286 followed by the 80386, and then the
80486. The Pentium is the fifth generation Intel microprocessor.
Each generation built upon the basic concept of the previous with
additional features and improved performance.

The 8086 was the first 80X86 families and is the basis for all Intel
microprocessors that followed. It was a 16-bit microprocessor and
significantly differ from the earlier 8-bit devices. It has 20 address
lines and capable of addressing 1 Mbyte memory space. The
various versions of the 8086 are operated on 5, 8 and 10 MHz
clock frequencies.
4

2.2 The 8086 Microprocessor
The block diagram of 8086 can be represented as
shown in Fig. 2.1 see next slide no.7. The 8086
consists of two main functional unit/sections, namely
the BIS (Bus Interface Unit) and EU (Execution Unit).
The major reason for this separation is to increase
the processing speed of the processor. These two
units are independent of each other and behave as
separate operational processors.
The EU contains the ALU, flags and general purpose
registers. The EU carries out all the arithmetic and
logical operations. All the registers in the 8086 are
16-bit wide, though 16 bit data registers can be used
as two 8-bit data registers. EU is responsible for
executing the instructions of the programs and to
5
carry out the required processing

The BIU has to interact with memory and input and output devices in
fetching the instructions and data required by the EU. The BIU controls
the address, data and control buses. The instruction fetching and
queuing, operand fetch and store, and address relocation are the
operations performed by the BIU. When EU is decoding and instructions
or executing instructions inside the microprocessor, the BIU prefetches
instructions from memory and stores them in the instructions queue for
faster processing. Upto 6 bytes of the instruction, stream can be queued
while waiting for decoding and execution. With the help of a queuing
mechanism of instructions, stream increases the efficiency of memory
utility. Whenever there is room for at least 2 byts in the queue, the BIU
will fetch a word from memory and load it into the queue. Due to this
queuing mechanism of instructions, stream greatly reduces dead-time on
the memory bus. The queue acts as a FIFO (first-in first-out) buffer btn.
the BIU and EU. The EU takes out instruction bytes as and when
required. The first byte, into the queue, immediately goes to the EU when
the queue is empty after the execution of a branch instruction. Also this is
the only occasion when the processor has to wait for instruction (i.e. when
the queue is flushed after a control transfer instruction). Otherwise, all the
other times the execution unit receives pre-fetched instructions from the 6
BIU queue.


AX
BX
CX
DX

Figure 2.1 Block diagram of 8086
7


Architecture of 8086

 The architecture of 8086 includes
 Arithmetic Logic Unit (ALU)
 Flags
 General registers
 Instruction byte queue
 Segment registers

8

2.2.1 Bus Interface Unit (BIU)

 The BIU has
1. Instruction stream byte queue
2. A set of segment registers
3. Instruction pointer

9

Instruction stream byte queue:
Microprocessor 8086 consists of a FIFO (first in first out)
registers set arranged like a pipe and called queue. The BIU
continuously fetch operations from the memory while the
processor is executing the current instructions. BIU unit
stores the fetched bytes in the queue and the EU will read
these bytes from the queue as and when it requires. The
memory interface is usually much slower than the processor
execution time, so this decouples the memory cycle time
from the execution time.
Segment registers:
The memory of 8086 is of 1 MB which is divided into
segments or we can say that the memory of 8086 is
segmentized.
10

Segment registers:
8086 consists of four 16-bit segment registers: the Code Segment (CS), Data
Segment (DS), Stack Segment (SS) and Extra Segment (ES) and these
registers are used with the 16-bit pointer, Index and Base registers to
generate the 20-bit physical address required to allow the 8086 to
address 1 MB memory. The segment registers point to the four
immediately addressable segments.

The Segmented architecture was used in the 8086 to keep compatibility
with earlier processors such as the 8085. It is one of the most significant
elements of the Intel Architecture.

11

Segment registers:
 The memory of 8086 is divided into 4 segments registers namely (i) Code
segment (program memory) (ii) Data segment (data memory) (iii) Stack
memory (stack segment) and (iv) Extra memory (extra segment) and
these registers are used with the 16-bit pointer, Index and Base registers
to generate the 20-bit physical address required to allow the 8086 to
address 1 MB memory. The segment registers point to the four
immediately addressable segments.
 Program memory – Program can be located anywhere in memory
 Data memory – The processor can access data in any one out of 4
available segments
 Stack memory – A stack is a section of the memory set aside to store
addresses and data while a subprogram executes
 Extra segment – This segment is also similar to data memory where
additional data may be stored and maintained

12

The Segmented architecture was used in the 8086 to keep compatibility
with earlier processors such as the 8085. It is one of the most significant
elements of the Intel Architecture.

(a) Code Segment (CS): CS is a 16 – bit register which stores the based
address of 64 KB segment and microprocessor instructions or programs.
The instructions point is the by default register used by the
microprocessor to access the instructions from the CS. Like any other
segment registers, the code segment (CS) register cannot be changed
directly. During the execution of the far jump, far call and far instructions,
the CS register is automatically updated.
(b) Stack Segment (SS): SS is also a 16 bit register containing offset
address of the 64 KB segment. This segment is used for stack memory
which operates on LIFO (last in first out). By default, the stack pointer
(SP) and base pointer (BP) registers are the pointer registers. PUSH and
POP are the main instructions to load and fetch a data from the stack
segment (SS). This segment register (like other segment registers)
cannot be initialized by loading the immediate value in the SS register. It 13
can be changed directly using POP instruction.

(c) Data Segment (DS): The data segment (DS) register is also a 16 bit
register which holds the logical address of the 64 KB long data segment.
The data segment is used to store the data. The by default registers of
this segment are AX, BX, CX , DS and index register (SI, DI). This
segment register initialized by loading the immediate value in the DS
register but can be changed directly using POP and LDS instructions.

(d) Extra Segment (ES): This is similar to the CS, SS and DS, the extra
segment (ES) is also a 16 bit register which contains the starting address
of the 64 KB segment. The segment defined by the ES register is used to
store data. The by default registers of this segment are AX, BX, CX , DS
and index register (SI, DI). This segment by default, is the destination
location for the string data which are always pointed by the DI register.
We cannot initialized the ES register by loading immediate value in it. It
can be changed using POP and LES instructions.
All the above stated segments have their own by default pointers but it is
possible to change default segments (except Instruction pointer (IP))
used by general and index registers by prefixing instructions with a CS, 14
SS, DS or ES prefix followed by a colon.

Instruction Point (IP) and address summation
The IP contains the offset or logical address of the next byte to be read from the code segment. In fact, it shows
the distance of the current location, in bytes, from the base address given by the current code segment (CS)
register. The contents of the CS shifted left by four bit 15 moves to the bit 19 position. The lowest four bits
are filled with zeros or the CS register value is multiply by decimal 16 or hexa decimal 10 H. The resulting
value is added to the instruction pointer contents to make up a 20 bit physical address. The CS makes up a 0
segment base address and the IP is looked as an offset into this segment. 15
Segment register CS

Offset value (16 bits)
X16 or x 10H IP
Segment register (16 bits) |0|0|0|0
Add
Adder

20 – bit address
Physical address (20 bits)

20 – bit address
15

Fig.: Generation of 20 bit physical address

2.2.2 Execution Unit (EU)
The execution unit consists of four 16-bit general purpose data registers
which can be used as eight 8 bit data registers, four 16 bit pointers and
base registers and one 16 bit flag register.

 The Execution Unit (EU) has
i. Control unit
ii. Instruction decoder
iii. Arithmetic and Logical Unit (ALU)
iv. General registers
v. Flag register

16


i. Control unit is responsible for the co-
ordination of all other units of the processor

ii. The instruction decoder translates the
instructions fetched from the memory into a
series of actions that are carried out by the
EU

iii. ALU performs various arithmetic and logical
operations over the data 17

The execution unit consists of four 16 bit general
purpose data registers which can be used as eight
8 bit data registers, four 16 bit pointers and base
registers and one 16 bit flag register.
General purpose data- Registers
Microprocessor 8086 consists of four 16 bit data
regisers AX, BX, CX and DX and each of these
registers can be divided into two parts as higher
and lower part to store 8 bit data. These are shown
in next Table the slide no. 19

18


Table 2.1 Data Register of 8086 19

 General registers are used for temporary
storage and manipulation of data and
instructions
 Accumulator register (AX) consists of two 8-bit
registers AH and AL each, which can be
combined together and used as a 16-bit
register AX
 Accumulator can be used for I/O operations
and string manipulation

20


 Base register (BX) consists of two 8-bit registers BH
and BL, which can be combined together and used as
a 16-bit register BX
 BX register usually contains a data pointer used for
based, based indexed or register indirect addressing
 Count register (CX) consists of two 8-bit registers CH
and CL, which can be combined together and used as
a 16-bit register CX
 Count register can be used as a counter in string
manipulation and shift/rotate instructions

21


 Data register (DX) consists of two 8-bit registers DH
and DL, which can be combined together and used as
a 16-bit register DX
 Data register can be used as a port number in I/O
operations
 In integer 32-bit multiply and divide instruction the DX
register contains high-order word of the initial or
resulting number

22

Pointers and base registers:

23

Pointers and base registers:
Stack Pointer (SP) is a 16-bit register pointing to
program stack
Base Pointer (BP) is a 16-bit register pointing to data in
stack segment. BP register is usually used for based,
based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for
indexed, based indexed and register indirect
addressing, as well as a source data addresses in string
manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for
indexed, based indexed and register indirect
addressing, as well as a destination data addresses in
string manipulation instructions. 24

Flag register
15 0

Carry flag
Overflow
Direction Parity flag

Interrupt enable Auxiliary flag

Trap Zero

Sign
Figure: Format of the flag register
Microprocessor 8086 consist of 16 bit flag register. The flag register is a set of 16 independent flip-flops. Out of
these 16 flip-flops, 6 flip-flops are used to indicate some data conditions and 3 flip-flops are used to
control some machine control operation and the remaining flip flops are reserved for future use/upcoming
microprocessors.

(a) Status- Flags
1) Zero Flag (ZF) - set if the result is zero.
2) Carry Flag (CF) - set if there was a carry from or
borrow to the most significant bit during last result
calculation
3) Sign Flag (SF) - set if the most significant bit of the
result is set.
4) Parity Flag (PF) - set if parity (the number of "1"
bits) in the low-order byte of the result is even.
5) Auxiliary carry Flag (AF) - set if there was a carry
from or borrow to bits 0-3 in the AL register.
6) Overflow Flag (OF) - set if the result is too large
positive number, or is too small negative number to
fit into destination operand

26

(a) Control-Flags
1. Single-step Trap Flag (TF) - if set then single-step
interrupt will occur after the execution of the next
instruction. This flag is used for single step
debugging.
2. Interrupt-enable Flag (IF) – This flag is used to
mask/unmask the maskable interrupt. When this
flag is set, maskable interrupts will cause the
microprocessor to transfer its control to an interrupt
vector specified location.
3. Direction Flag (DF) - if set then string manipulation
instructions will auto-decrement index registers. If
cleared then the index registers will be auto-
incremented.

27

Outline

Chapter 4: Instructions Set of 8086

8086
4.5. Instruction set of 8086

8086
Program is a set of instructions written to solve a problem. Instructions are
the directions which a microprocessor follows to execute a task or part of a
task. Broadly, computer language can be divided into two parts as high-level
language and low level language. Low level language are machine specific.
Low level language can be further divided into machine language and
assembly language.

Machine language is the only language which a machine can understand.
Instructions in this language are written in binary bits as a specific bit pattern.
The computer interprets this bit pattern as an instruction to perform a
particular task. The entire program is a sequence of binary numbers. This is
a machine-friendly language but not user friendly. Debugging is another
problem associated with machine language.

To overcome these problems, programmers develop another way in which
instructions are written in English alphabets. This new language is known as
Assembly language. The instructions in this language are termed mnemonics.
As microprocessor can only understand the machine language so
mnemonics are translated into machine language either manually or by a
program known as assembler.

Efficient software development for the microprocessor requires a complete familiarity
with the instruction set, their format and addressing modes. Here in this chapter, we will
focus on the addressing modes and instructions formats of microprocessor 8086.

The 8086 microprocessor introduces many new technique to access the
memory by introduction of many more types of addressing modes. With
these new memory related addressing modes, it can access memory in
many different ways and these addressing mode provide flexibility to the
processor to access memory, which in turn allows the user to access
variables, array, records, pointers, and other complex data types in a
more flexible manner.

Microprocessor 8086 addressing modes is the first step towards the
understanding of 8086 assembly language. Microprocessor 8086 has all
the five data addressing modes available in 8085 i.e. implied, register,
immediate, direct and register indirect. The register indirect addressing
mode in 8086 works with SI, DI, BX and BP registers.

Apart from these, 8086 also have five more addressing modes and
these are
1. Base addressing mode
2. Index addressing mode
3. Based index addressing mode
4. Based indexed with displacement addressing mode
5. String addressing mode

Different addressing modes may take different amounts of time to compute
the effective address. Complex addressing modes take more time to
compute the effective address than the simpler addressing modes.
Complexity of an addressing mode will go on increasing with the number
of terms in the addressing mode. e.g. [BX] [DI] is more complex than [DI]
similarly disp [BX] [DI] is more complex than [BX] [DI].

The displacement in all the memory-related addressing modes can be a
signed 8 bit constant or a signed 16 bit constant. For 8 bit displacement
the offset is in the range of -128 .. + 127 and the instruction will be shorter
and faster as compared to the instructions which uses the 16 bit signed
displacement. Always preferable to use a small displacement (8 bit) and a
large number in the registers(s) instead of using large displacement (16
bit) and small value in the registers(s) because the size of the value in the
register does not affect the execution time or size.

Immediate addressing mode:
In immediate addressing mode the operands are specified within the
instruction itself. The immediate operand can only be the source operand
e.g.

MOV AX, 2500H
Here the immediate data is 2500H and the data itself is provided in the
instruction

Register addressing mode:
Most 8086 instructions can operate on the 8086s general purpose
register set and the contents of a register can be accessed by
specifying the name of the register as an operand to the instruction.
e.g. the following MOV instructions copies the data from the source
operand to the destination operand
MOV AX, BX
MOV DL, AL
MOV SI, DX
Pls. note that the 8 and 16 bit registers are the valid operands for this instruction.
The only restriction is that both operands must be of the same size. The registers
are the best place to keep often used variables. Instructions using the registers are
shorter and faster than those that access memory. Segment register can never be
used as data registers to hold arbitrary values. They should be only contain
segment address.

Direct addressing mode /the displacement only addressing mode–
Direct addressing mode displacement only addressing mode may be defined as
the addressing mode in which the address of the memory is specified in the
instruction itself. In this addressing mode the instruction consists of a 16 bit
memory address or an 8 bit IO address. The 16 bit memory address is always
written inside the square brackets. e.g. the instruction MOV BL, [2000H],
transfers the content of the memory location 2000H in the BL register. Similarly
the instruction MOV [1234H], DL transfers the content of the DL register in the
memory location specified by 1234H.
Fig. 4.1 shows the direct addressing mode.
By default all the direct addressing mode
point in the data segment. The segment
override prefix is to be used before address
if we have to point any other memory
segment e.g. to access location 4321H
in the extra segment ES the
instruction will be of the form BL 2000H
MOV AX, ES:[4321H] MOV BL, [2000H]

DL 1234H
MOV [1234H], DL

Register indirect addressing mode: – The instruction specifies a
register containing an address, where data is located. This address is also
used in concern with memory and IO. In this addressing mode the memory
address is specified by some pointer, index or base registers and these
registers are written inside the square brackets. These are four forms of
addressing mode on the 8086, best demonstrated by the following
instructions:
MOV DX, [BX]
MOV DX, [BP]
MOV DX, [SI]
MOV DX, [DI]
These four addressing modes refer the word at the offset found in the BX,
BP, SI or DI registers, The [BX], [SI], [DI] modes use the DS segment by
default. The [BP] addressing mode uses the stack segment (SS) by default.
To access data from other than the default segment, the segment override
prefix symbols are to be used. The following instructions demonstrate the
use of these overrides:
MOV AX, CS:[BX]
MOV AX, DS:[BP]
MOV AX, SS:[SI]
MOV AX, ES:[DI]

Base addressing mode: - 8-bit or 16-bit displacement instruction operand is
added to the contents of a base register (BX or BP), the resulting value is a
pointer to location where data resides. In this addressing mode, the memory
location is calculated by adding the signed 8 bit or 16 bit displacement to
either BX or BP register.
Memory location =BX 8 bit displacement
+-
= BP 16 bit displacement
e.g. If BX = 2000H, the instruction is
MOV AL, [BX + 15]
In this example, the contents of the memory location 200FH (2000H + 0FH
(equivalent to decimal 15) is transferred to AL register. The maximum 8 bit
displacement can be +-127 and the maximum 16 bit displacement can be +-
32767.
These are four possible combinations of the base addressing modes ie.
Memory location = BX +- 8 bit displacement
= BX +- 16 bit displacement
= BP +- 8 bit displacement
= BP +- 16 bit displacement
The displacement can also be written as
MOV AL, DISP [BX]
The addressing modes involving BX, use the data segment, the addressing mode
involving [BP] uses the stack segment by default.
MOV AL, SS: DISP [BX]
MOV AL, ES: DISP [BP]

Indexed addressing mode:
This addressing mode is similar to the base addressing mode with the
difference is that this mode is having 8-bit or 16-bit displacement
instruction is added to the contents of an index register (SI or DI), the
resulting value is a pointer to location where data resides. In this
addressing mode, the memory location is calculated by adding the
signed 8 bit or 16 bit displacement to either SI or DI register.

Memory location = SI 8 bit displacement
+-
= DI 16 bit displacement
There are four possible combinations of the base addressing modes i.e.
SI +- 8 bit displacement
SI +- 16 bit displacement
DI +- 8 bit displacement
DI +- 16 bit displacement

Data segment is the default segment for this addressing mode. As with the register
indirect and base addressing modes, the segment override prefixes can be used
to specify a different segment.
MOV AL, CS: DISP [SI]
MOV AL, SS: DISP [DI]

Based Indexed addressing mode:
The based indexed addressing modes are simply the combinations of the register
indirect addressing modes. Here, the contents of a base register (BX or BP) is
added to the contents of an index register (SI or DI), the resulting value is a pointer
to location where data resides
Memory location = SI BX
+
DI BP
The following forms for these addressing modes are:
MOV AL, [BX] [SI]
MOV AL, [BX] [DI]
MOV AL, [BP] [SI]
MOV AL, [BX] [DI]
e.g., If BX = 2000H and SI = 5400H, the instruction is
MOV AL, [BX + SI]
In this example the contents of the memory location 7400H (2000H + 5400H) is
transferred to AL register. The addressing modes that do not involve bp use the
data segment by default. Those that have bp as an operand use the stack segment
by default. There are four possible combinations of the base addressing modes, i.e.
Memory location = SI + BX
SI + BX
DI + BP
DI + BX

Based Indexed with displacement addressing mode:
In this addressing mode, the offset address is generated by the sum of
Base register and Index registers along with 8-bit or 16-bit displacement
instruction operand is added to the contents of a base register (BX or
BP) and index register (SI or DI), the resulting value is a pointer to
location where data resides.

Memory location = SI BX 8 bit displacement
+ +-
DI BP 16 bit displacement
In this addressing mode the memory location is calculated by adding the
signed 8 bit or 16 bit displacement to the sum of the content of SI + BIP
or SI + BX or DI + BP or DI + BX

Considering the same example i.e. if BX = 2000H and SI = 5400H, the
instruction is
MOV AL, [BX + SI + 15]

In this example, the contents of the memory location 740FH (2000H + 5400H
+0FH i.e. equiv. to decimal 15) is transferred to AL register. Again the
maximum 8-bit displacement can be +- 127 and the maximum 16 bit
displacement can be +- 32767.
There are eight possible combinations of the base index with displacement
addressing mode i.e.
SI +BP +- 8 bit displacement
SI + BX +- 8 bit displacement
DI + BP +- bit displacement
Memory location = DI + BX +- 8 bit displacement
SI + BP +- 16 bit displacement
SI + BX +- 16 bit displacement
DI + BP +- 16 bit displacement
DI + BX +- 16 bit displacement
Following are some of the examples of these addressing modes:
MOV AL, DISP [BX] [SI]
MOV AL DISP [BX + DI]
MOV AL [BP + SI + DISP]
MOV AL, [BP] [DI] [DISP]

String addressing modes:
This mode uses index registers. The string instructions automatically assume SI to
point to the first byte or word of the source operand and DI to point to the first
byte or word of the destination operand.
The segment register for the source is DS and may be overridden. The segment
register for the destination must be ES and cannot be overridden. The contest
of SI and DI are automatically incremented by clearing DF (Direction Flag) to 0
by CLD instruction or automatically decremented by setting DF to 1 by STD
instruction. Table 4.1. summarizes all the 32 possible data addressing modes
of 8086

(BX) + (SI) (BX) + (SI) + d8 (BX) + (SI) + d16 AL AX
(BX) + (DI) (BX) + (DI) + d8 (BX) + (DI) + d16 CL CX
(BP) + (SI) (BP) + (SI) + d8 (BP) + (SI) + d16 DL DX
(BP) + (DI) (BP) + (DI) + d8 (BP) + (DI) + d 16 BL BX

(SI) (SI) + d8 (SI) + d16 AH SP
(DI) (DI) + d8 (DI) + d16 CH BP
d16 (BP) +d8 (BP) +d16 AH SP
(BX) (BX) +d8 (BX) +d16 BH DI

The instructions of 8086 may be one to six byte long. These instructions have different formats
and following figure shows some of the instruction formats.
OPCODE
OPCODE REG
OPCODE REG MOD REG R/M
OPCODE REG MOD REG R/M Lower Disp Higher Disp
OPCODE REG MOD REG R/M Lower Disp Higher Disp Lower Data Higher data
opcode (operation code) is the portion of a machine language instruction that specifies the
operation to be performed. Their specification and format are laid out in the
instruction set architecture of the processor. In assembly langage mnemonic form an opcode
is command e.g. MOV, AL, 34h here the opcode is MOV instruction and other parts are
operands.
The first byte always consist of the opcode. The opcode may be of 8 bit or occupy MSB six
bits (most significant bit) of the first bytes and it defined the operation to be carried out by the
instruction and the remaining two bits are any of the following bits
1. Direction bit (D) defines whether the register operand in byte 2 is the source or destination
operand.
D = 1 specifies that the register operand is the destination operand
D = 0 indicates that the register is a source operand
2. Data size bit (W) defines whether the operation to be performed is an 8 bit or 16 bit data
W = 0 indicate 8 bit operation and W = 1 indicates 16 bit operation
3. Sign bit (S) is used for sign extension of an 8 bit 2s compliment number to a 16 bit 2s
compliment number. This is done by making all the bits in high order byte same as that of
MSB in the lower order byte. This bit appears with the W bit in add, subtract and compare
instructions. For 8 bit operation S:W bits are 00 and these bits are 01 for 16 bits operation
with 16 bit immediate operand.
S:W bits are 11 for 16 bit operation with a sign extended 8 bit immediate operand

4. V bit is used in shift and roate instruction to determine the number of shifts
V = 0 indicates that the shift count is 1 , V=1 indicate the CL register contains the shift count

5. The Z bit is used in REP instruction. The Z bit is matched with the zero flag bit. The REP instruction goes
on executing till the Z bit does not match with the zero flag.

A summary of these bits encoding is shown in Table 4.2. below
Field Value Function
S 0 No sign extension
1 Sign extend 8 bit immediate data to 16 bits if W = 1
W 0 Instruction operates on byte data
1 Instruction operate on word data
D 0 Instruction source is specified in REG field
1 Instruction destination is specified in REG field
V 0 Shift/rotate count is one
1 Shift/rotate count is specified in CL register
Z 0 Repeat/loop while zero flag is clear
1 Repeat/loop while zero flag is set

As shown in the previous figure, depending on the instruction, the opcode byte may be the only byte in the
instruction or may be followed by
- One or two byte long immediate data
- One or two byte long displacement
- One or two byte long displacement and then ne or two byte long immediate data
- Two byte long direct address
- Two byte long displacement and then two byte long segment address

4.5 Instruction set for 8086 microprocessors
The instruction set of 8086 microprocessor can be broadly classified
into eight group depending on the function these instruction perform
1 Data Transfer Instruction : Use for transferring data from source
location to destination
2 Arithmetic Instruction : Use to perform arithmetic operations e.g
addition subtraction ,multiplication and division

3 Logical Instruction : Use to perform logical operation e.g CMP,
AND,NOT, OR,EX-OR, operation
4 Shift and rotate operation / Instructions: Use to perform the logical and
arithmetic shift operations and left and right shifting
5 String Instructions: Use to perform string related operations
6 Data Adjust Instructions: Use to convert the binary data in ASCII or in
BCD format
7 The control Transfer Instructions: Use to transfer the control within the
program or from main program to subroutine program or from subroutine
program to main program
8 Machine control instructions are used to perform the machine control
operation like halt etc.


MOV
ADD, SUB, MUL, DIV, INC, DEC, NEG
CMP, AND, OR, NOT, XOR

Let us now going to investigate these instructions in details.

MOV destination, source
The MOV instructions copies the second operand (source) to the first
operand (destination) without modifying the contents of the source and pls.
remembers this is not data transfer/move but data copy instructions. Here,
the source operand can be general purpose register or memory locations
and the destination register can be a general purpose register or memory
location. Both operands must be of the same size which may be byte or
word.
Following type operands are supported
MOV REG, Memory
MOV Memory, REG
MOV REG, REG
MOV Memory, immediate
MOV REG, Immediate
Gen. purpose register AX, BX, CX, DX, AH, AL etc. and the memory may
be specified by any othe memory related addressing mode.

MOV destination, source
For Segment registers only these type of MOV are supported
MOV SREG Memory
MOV Memory SREG
MOV REG REG
MOV SREG REG
Pls. note that data can’t be transferred from one memory to another memory, from
memory to an IO, from one IO to another IO and from IO to memory. IO can
communicate with Accumulator only.
The MOV instructions cannot set the value of CS and IP register, also it cannot
copy value of one segment register to another segment register.
e.g If we want to initiative the Data segment by memory location 02500H, then first
we have to load, the values 2500H in AX register and then transferring the
contents of AX to DS register with the help of the following instruction
MOV AX, 2500H
MOV DS, AX
In MOV instructions the flag remain unchanged.

ADD, SUB, MUL, DIV, NEG, INC, DEC
Microprocessor 8086 may perform the arithmetic operation on four types of data ie.
Signed binary, Unsigned binary, Unsigned packed BCD (same number would fit
into a single byte) and Unsigned Unpacked BCD. The binary no. of 8 bit/16 bit
and the BCD number are always unsigned.
ADD Add
Operands REG, Memory
Memory, REG
REG, REG
Memory, Immediate
REG, Immediate
These instructions add a data from the source operand to a data from the
destination and save the result in the destination operand provided source and
destination of the same size, same type i.e. byte/word. But pls. note that the
Segment register can’t be use as an operand in ADD instruction. Memory to
memory and IO to memory addition is also not allowed.

e.g. add instructions can be used to perform the
operation
F = X+Y+Z
MOV AX, X
ADD AX, Y
ADD AX, Z
MOV F, AX
Flag bit are modified as per the result of the
operations.

SUB Subtract
Operands REG, Memory
Memory, REG
REG, REG
Memory, Immediate
REG, Immediate
This instructions subtract the source operand from the destination operand
store the result in the destination operand. Pls. note that the Segment register
can’t be use as an operand. Memory to memory and IO to memory addition is
also not allowed. Flag bits are modified as per the result of the operation
e.g
MOV AL, 05H SUB AL, 02H
After the execution of the Sub instruction AL will contain 03H

MUL Multiplication
Operands REG
Memory
This instructions multiply the contents of the AL or the AX by a specified source
operand. The AL and AX are the destination operands for 8 bit and 16 bit
multiplication, again both the implied operand and the source operand must be of
the same size. For a 16 bit multiplication, the implied operand will be AX register.
After the multiplication the product, ie. 32 bits, will be stored into the DX: AX
register pair.
AX AX
x x
16 bit operand 8 bit operand
DX AX AH AL
e.g. MOV AL, 0FDH
MOV CL, 05H
MUL CL; AX = 04F1H
CF =0F=0 when high section of the result is zero.

MUL Multiplication
Operands REG
Memory
For an 8 bit multiplication, the implied operand will be the AL register. After the
multiplication the product, which is of 16 bits, will be stored into the AX register. If
after the multiplication the product, which is of 16 bits, will be stored into the AX
register. If after the multiplication DX is not 0 for 16 bit operands or AH is not zero
for 8 bit operands, then the carry and overflow flags will set. The A, P, S and Z
flags are undefined, i.e. the value of these flag bits may be either 0 or 1.
See the previous slide….

DIV division
Operands REG
Memory
This instruction divides the contents of the AX or the DX: AX by a specified source operand. The AX and the
DX:AX is the implied destination operands for 16 bit and 32 bit division. This is an unsigned operation and
hence both operands are treated as unsigned operands. If the divisor is 16 bits wide, then the dividend is
the DX: AX register pair. After the division the quotient will be stored into AX and the remainder into DX.
When the divisor is of 8 bits the dividend is AX. And in this case the quotient will be stored in AL and the
remainder in AH.
Following Fig. shows the representation of DIV. All the flag bits are undefined ie. The value of all the flag bits may
be either 0 or 1
AX DX AX
÷ ÷
8 bit operand 16 bit operand
AH AL DX AX
Remainder Quotient Remainder Quotient

e.G
MOV AX, 00C8H
MOV CL, 06H
DIV CL
After this program the result is available in AL (=21H) and the remainder is present in AH (=02H)

NEG Negate
Operands REG
Memory
This instruction produces the two’s compliment of the specified operand and stored the result in
the same operand. Microprocessor performs the negate (NEG) operation by subtracting the
operand from 0. This is done to represent a negative number. All the flag bits are modified
as per the result. The carry flag will be set for a non-zero operand and for a zero operand it
will be reseted. If the operand contains the maximum possible negative value (-128 for 8 it
operands or -32768 for 16 bit operands), the value does not change, but the overflow and
carry flags are set.
e.g
MOV AL, 15H
NEG AL; AL = 0EBH (2’s complement of 15 H)

INC Increment
Operands REG
Memory

Increment the operand by 1. This instruction increment the destination operand by 1. This
instruction differs with the ADD by 1 instruction in the way that the INC instruction does not
affect the carry flag whereas the ADD instruction modifies the carry flag. The INC instruction
is more compact and often faster than the comparable ADD instruction because it is a one
byte instruction.
In INC all flags, except the carry flag, changes as that of in ADD instructions

DEC Increment
Operands REG
Memory

Decrement the operand by 1. This instruction decrement the destination operand by 1. This
instruction differs with the SUB by 1 instruction in the way that the DEC instruction does not
affect the carry flag whereas the SUB instruction modifies the carry flag. The DEC
instruction is more compact and often faster than the comparable ADD instruction because it
is a one byte instruction. In DEC except the carry flags, all other flag changes as that of in
SUB instructions

CMP, AND, NOT, OR, XOR
The 8086 provides six logical instructions but above five(5) are in your course. These
instruction can manipulate bits, convert values, do logical operations.
CMP Compare
Operands REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction compare the source operand with the destination operand.
Microprocessor executes this CMP instruction by subtracting the source operand
from the destination operand but none of the operands are modified. The result is
reflected by the flag bits. Generally, the result (i.e. flag conditions) of this
instruction is used for conditional control transfer instructions. The comparison
may be a signed comparison or an unsigned comparison. For unsigned
comparison, the result is reflected by the Carry and Zero flag bits whereas for
signed comparison the result is reflected by the Zero, Sign and the Overflow flag.

For unsigned comparison operation, consider instruction CMP AX, BX , the microprocessor perform the
AX-BX operation.
Now if AX = BX, then the result will be zero and hence the zero flag will set. If AX is greater than BX,
the result will be non-zero and positive and hence both the Zero and Carry are reset. Similarly, when
BX is greater than AX, then to perform AX-BX we require to take borrow and hence the Zero flag is
reset and the carry is set.
For signed comparison if the EX-OR operation of the Sign and Overflow flag is 1, then the result is
negative. It is to be noted that for signed comparisons, the sign flag doesn't show the proper status.

e.g.
Flag condition Result
Sign flag Overflow flag
0 1 AX < BX
1 0 AX < BX
0 0 AX > BX
1 1 AX > BX

The CMP instruction also affects the parity and auxiliary carry flags, but these two flag are rarely tested after
a compare operation.

NOT Logically NOT

Operands REG
memory
This instruction complements the individual bits of the operand and save the result in
the same operand. We can say that it generates the 1’s complement or the NOT
operation of the operand. After this instruction the flag register remain
unmodified.
MOV AL, 39H
NOT AL; AL = C6H

OR Logically OR

memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction performs a bitwise logical OR operation between the source and
destination operands. The result is stored in the destination operand. After the
operation, the Z, S and P flag bits are modified whereas the carry and overflow
flag bits are 0 and auxiliary carry is undefined (i.e. may be 0 or 1).

XOR Logically EX-OR

memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction performs a bitwise logical exclusive OR operation between the
source and destination operands. After the operation, the result is stored in the
destination. The Z, S, and P bits of the flag register are modified as per the result
whereas the carry and overflow flag bits are set to 0 and auxiliary carry is
undefined (i.e. may be 0 or 1).

AND Logically AND
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction performs a bitwise Logical AND of destination operand and the source operand.
The result of the operation is stored in the destination operand. The AND operation is
performed as per following table. The Z,S, and P flag bits are modified as per the result. The
carry and overflow flag bits are 0 and auxiliary carry is undefined (i.e. may be 0 or 1)
AND OR EXCLUSIVE OR NOT
A B A.B A B A-B A B A(-)B A /A
0 0 0 0 0 0 0 0 0 0 1
0 1 0 0 1 1 0 1 1 1 0
1 0 0 1 0 1 1 0 1 - -
1 1 1 1 1 1 1 1 0 - -
e.g.
MOV AL, 61H; AL = 01100001
AND AL, CFH; AL = 01000001

fco-lecture-8086

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