Aneesh Raveendran

processor design ip core micro controller branch prediction vhdl fpga microprocessor processor pipe lining idealism mips pipeline stalls computer architecture uart ieee 802.15.1 protocol rs232 arm cortex-a8 neon fpu arm system on chip bluetooth on fpga soc bluetooth refcomm alu arithmetic and logic unit fetch module asic decoder execute cisc transistors analog design electronic circuits universal asynchronous receive and transmit serial communication rs 232 instruction set control hazard data hazard tcl modelsim reversible logic gates fredkin gate feynman gate not gate toffolli gate reversible computing aligned memory access unaligned memory access memory access external fragmentation internal fragmentation pipe lining superscalar l1 cache