Unit 1 8085 Timing diagram - lecture 5b

MICROPROCESSOR
& MICROCONTROLLER APPLICATIONS
54 EC 51
Lecture 5b – 8085 ALP & TIMING DIAGRAM
By DICKSON NKONGO, MSc.
ECE Department

MP & MC APPLICATIONS
Lecture 5b – 8085 ALP & Timing Diagram
Mr.DicksonNkongo:SJUCET--2017/2018

MACHINE CYCLES And Their Timing OF 8085:
Lecture 5 – 8085 ALP & Timing Diagram
As far as execution of instructions is concerned, in
8085 microprocessor, each instruction is divided into
two parts:
1- The operation code(opcode) and
2 - The operand
The opcode tells us what the operation is and the
operand is the necessary information required for the
instruction. The operand may be either data or an
address or other information required for the
instruction.
Each instruction is divided into machine cycles and
each machine cycle is divided into clock cycles or T-
states

MACHINE CYCLES And Their Timing OF
8085:
During normal operation, the microprocessor
sequentially fetches, decodes and executes one
instruction after another until a halt instruction
(HALT).
Timing Diagram is the graphical representation
of the time taken for the execution of each
instruction by a microprocessor.
The execution time is represented in T-states.

MACHINE CYCLES And Their Timing OF 8085:
Instruction Cycle:
Is the time required to execute an instruction
Machine Cycle:
The time required to access the memory or
input/output devices is called machine cycle.
T-State:
The machine cycle and instruction cycle takes
multiple clock periods.
A portion of an operation carried out in one
system clock period is called as T-state.

• Clock Signal
The 8085 divides the clock frequency provided at X1 and
X2 inputs by 2 which is called operating frequency.
One T-state is equal to the time period of the internal
clock signal of the microprocessor
For Ex: If the internal clock frequency of 8085
microprocessor is 3 MHZ, One T-state is equal to
•
𝟏
𝒇
=
𝟏
𝟑𝒙𝟏𝟎 𝟔 = 0.333x10-6sec=333x10-9sec
• (333 nano seconds nearly)

• Clock Signal
T-State
1 Clock cycle
Rise time and fall time

• Single Signal
Single signal status is represented by a line. It may
have status either logic 0 or logic 1 or tri-state
Logic 0
Logic 1
Tri state

• Group of signals
Group of signals is also called a bus.
Eg: Address bus, data bus
State changes
Valid state
Tri state

Machine cycle 2 Machine cycle 5
Instruction cycle
T – State 1 T – State 2 T – State 3 T – State 6
Machine cycle 1

The 8085 microprocessor has 5 basic machine
cycles. They are
1. Opcode fetch cycle (4T)
2. Memory write cycle (3T)
3. I/O read cycle (3T)
4. Memory read cycle (3T)
5. I/O write cycle (3T)
Some more machine cycles for 8085:
1. Interrupt Acknowledge
2. Bus Idle

8085 Machine Cycles
The three status signals IO/M*, S1 and S2 identify each
type
DICKSON NKONGO, MSc. : ECE Department.

The Control and Status Signals
•There are 4 main control and status signals. These are:
• ALE: Address Latch Enable. This signal is a pulse that become
1 when the AD0 – AD7 lines have an address on them. It
becomes 0 after that. This signal can be used to enable a
latch to save the address bits from the AD lines.
• RD’: Read. Active low indicates that the data must be read
from the selected memory location or I/O port via data bus.
• WR’: Write. Active low indicates that the data must be
written into the selected memory location or I/O port via
data bus..
• IO/M’: This signal specifies whether the operation is a
memory operation (IO/M=0) or an I/O operation (IO/M=1).
• S1 and S0: Status signals to specify the kind of operation
being performed .Usually un-used in small systems.

Signal Timings
ALE
 This signal is active high signal. It is activated in the
beginning of T1 state of each machine cycle except
bus idle machine cycle and it remains active in the T1
state

Signal Timings
A0 - A7 (Lower Byte Address)
This is available on the multiplexed address/data bus (AD0 -
AD7) during T1 state of each machine cycle except bus idle
machine cycle.

Signal Timings
D0 - D7 (Data Bus)
The data from memory or I/O device and from
microprocessor to memory or I/O device is transferred
during T2 and T3 – states.
N.B: In read machine cycle, data will appear on the
data bus during the later part of the T2 - state as shown
in fig. (next slide).
This is because to read data from memory or I/O device
it is necessary to select memory or I/O device, after the
selection, device will put the data from the selected
location on the data bus. This action needs finite time.
This time is referred as “Access Time”.

Signal Timings
D0 - D7 (Data Bus)
In case of write cycle, data is available in the register set
of the microprocessor and it can put that data on the
data bus with zero access time.
Read Write

Signal Timings
A8 - A15 (Higher Byte Address)
 The higher byte of address is available on the A8 –
A15 bus during T1, T2, and T3 – state of each
machine cycle, except bus idle machine cycle

Signal Timings
IO/M*, S0, S1:
 These are called status signals. They decide the type of
machine cycle to be executed. They are activated at the
beginning of T1 – state of each machine cycle and remain
active till the end of the machine cycle

Signal Timings
RD* and WR* (‘*’ here denotes Bar)
These decide the direction of the data transfer.
When RD* signal is active, data is transmitted
from memory or I/O device to microprocessor.
When WR* signal is active, data is transmitted
from microprocessor to the memory or I/O device.
Both signals are never active at a time.
**And since the data transfer in 8085 takes place
during T2 and T3, these signals are activated
during T2 and T3 as shown in the next slide

RD* and WR*

• 8085 Machine cycles

The Control and Status Signals
• (* ) means ‘bar’ i.e. active low
IO/M* RD* WR* REMARKS
0 0 1 Reading from memory
0 1 0 Writing into memory
1 0 1 Reading from IO device
1 1 0 Writing into IO device
X 1 1
No communication with
peripheral

1. Opcode Fetch Machine Cycle
• The first step of executing any instruction is the Opcode
fetch cycle.
– In this cycle, the microprocessor brings in the
instruction’s Opcode from memory.
• To differentiate this machine cycle from the very
similar “memory read” cycle, the control & status
signals are set as follows:
– IO/M’=0, s0 and s1 are both 1.
– This machine cycle has four T-states.
• The 8085 uses the first 3 T-states to fetch the opcode.
• T4 is used to decode and execute it.
– It is also possible for an instruction to have 6 T-states in
an opcode fetch machine cycle.

Machine Cycles
1. Opcode Fetch Machine Cycle:
Step 1: (State T1)
The 8085 places the contents of PC (Program
counter) on the address bus. Higher-order byte of
the PC is placed on the A8-A15 lines, while lower-
order on AD0-AD7 lines which stays on only
during T1.
Microprocessor activates ALE which is used to
latch the low-order byte of the address before it
disappears.
8085 also sends status signals IO/M* = 0, S1=1
and S0 = 1.

Machine Cycles
Step 2: (State T2)
Lower-byte address disappears from the AD0-
AD7 lines. However A0-A7 remain available as
they were latched during T1.
8085 sends RD* signal low to enable the
addressed memory location.
Then memory device places the contents of the
addressed memory location on the data bus
(AD0-AD7).

Machine Cycles
Step 3: (State T3)
8085 loads the data (opcode in this case) from
the data bus in its Instruction register.
Then raises RD* to high which disables the
memory device (deactivate RD signal)

Machine Cycles
Step 4: (State T4)
Microprocessor decodes the opcode, and on the
basis of the instruction received, it decides
whether to enter state T5 or to enter state T1 of
the next machine cycle.
One byte instructions which operates on eight bit
data (8 bit operand) are executed in T4. (e.g.
MOV A, B, ANA D, ADD C). This is because for
one byte instructions which operate on eight bit
data, data is always available in the internal
memory of 8085 i.e. registers

Machine Cycles
Step 5: (State T5 and T6)
Used for internal microprocessor operations
required by the instruction.
One byte instructions which operates on
sixteen bit data (16 bit operand) are executed
in T5 and T6. (e.g. DCX H, PCHL, SPHL,
INX H etc.

Timing Diagram for Opcode Fetch Machine Cycle

State T1
IO/M*=0, S1=1, S0=1
State T2
.
.
RD* = 0
Data
State T3
RD* = 1
State T4
Opcode
Decoded

(b)Timing Diagram for Opcode Fetch Machine Cycle

Machine Cycles
2. Memory Read Cycle:
 8085 executes this cycle to read the contents of R/W
memory (RAM) or ROM.
 The length of this machine cycle is 3-T states (T1-
T3).
Step 1: (State T1)
Microprocessor places the address on the address
lines from stack pointer, general purpose register
pair or program counter and then activates the
ALE signal for latching the low-byte of address.
Also microprocessor sends status signals: IO/M* =
0, S1 = 1, and S0 = 0 (for memory read machine
cycle)

Machine Cycles
Step 2: (State T2)
Microprocessor sends RD* signal low to enable
Then memory device places the contents of the
addressed memory location on the data bus (AD0-
AD7)
Step 3: (State T3)
8085 loads the data from the data bus into
specified register (A, B, C, D, E, H, H, and L) and
raises RD* to high which disables the memory
device

Machine Cycles
.

State T1
IO/M*=0, S1=1, S0=0
State T2
.
.
RD* = 0
Data
State T3
RD* = 1

Timing Diagram for Memory Read Machine Cycle

Timing diagram for MVI A, 30H instruction
– To understand the memory read machine cycle, let’s
study the execution of the following instruction:
• MVI A, 30
– In memory, this instruction looks like:
• The first byte 3EH represents the opcode for
loading a byte into the accumulator (MVI A), the
second byte is the data to be loaded.
2000H
2001H
3E
30

The 8085 needs to read these two bytes from memory
before it can execute the instruction. Therefore, it will
need at least two machine cycles.
1. The first machine cycle is the opcode fetch
discussed earlier.
2. The second machine cycle is the Memory Read
Cycle.
2000H
2001H
3E
30

Machine Cycles
3. Memory Write Cycle:
8085 executes this cycle to store the data into data
memory or stack.
The length of this machine cycle is 3-T states (T1-
T3).
Step 1: (State T1)
pair and then activates the ALE signal for latching
the low-byte of address.
0, S1 = 0, and S0 = 1 (for memory write machine
cycle)

Machine Cycles
3. Memory Write Cycle:
Step 2: (State T2)
Microprocessor places the data on the data bus
and sends WR* signal low for writing into the
Step 3: (State T3)
8085 writes (stores) the data from the data bus
into addressed memory location and raises
WR* to high which disables the memory device
and terminates the write operation.

Memory Write Data Flow

State T1
IO/M*=0, S1=0, S0=1
State T2
.
.
WR* = 0
DataState T3
WR* = 1
Data

Timing Diagram for Memory Write Machine Cycle

The I/O Read and I/O Write Operation
• the I/O read and I/O write machine cycles are
similar to the memory read and memory write
machine cycles respectively, except that
IO/M* signal is High (1) for I/O read and I/O
write machine cycles.
• High IO/M* indicates that it is an I/O
operation.

Machine Cycles
4. I/O Read Cycle:
8085 executes this cycle to read the data from I/O
device.
T3).
Step 1: (State T1)
pair or program counter and then activates the
ALE signal for latching the low-byte of address.
1, S1 = 1, and S0 = 0 (for I/O read machine cycle)

Machine Cycles
4. I/O Read Cycle:
Step 2: (State T2)
Microprocessor sends RD* signal low to enable
Then I/O device places data on the data bus
(AD0-AD7)
Step 3: (State T3)
8085 loads the data from the data bus into
specified register (A, B, C, D, E, H, H, and L) and
raises RD* to high which disables the I/O device

Machine Cycles
4. I/O Read Cycle:
.

Machine Cycles
4. I/O Read Cycle:
.
Timing Diagram for I/O Read Machine Cycle

Machine Cycles
5. I/O Write Cycle:
8085 executes this cycle to store the data into data IO
device.
T3).
Step 1: (State T1)
pair and then activates the ALE signal for latching
the low-byte of address.
1, S1 = 0, and S0 = 1 (for I/O write machine cycle)

Machine Cycles
5. I/O Write Cycle:
Step 2: (State T2)
Microprocessor places the data on the data bus
and sends WR* signal low for writing into the
addressed I/O device.
Step 3: (State T3)
8085 writes (stores) the data from the data bus
into addressed I/O device and raises WR* to
high which disables the I/O device and
terminates the write operation.

Unit 1 8085 Timing diagram - lecture 5b

Timing Diagram for I/O Write Machine Cycle

Unit 1 8085 Timing diagram - lecture 5b

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