Fault Simulation (Testing of VLSI Design)

Fault Simulator
Testing of VLSI Design
Usha Mehta

Acknowledge
• This presentation has been summarized from
various books, papers, websites and presentations
on VLSI Design and its various topics all over the
world. I couldn’t itemwise mention from where
these large pull of hints and work come. However,
I’d like to thank all professors and scientists who
created such a good work on this emerging field.
Without those efforts in this very emerging
technology, these notes and slides can’t be
finished.
03-12-2019 Dr Usha Mehta 2

Introduction
• Applying
Deterministic TPG:
• For given fault
– Fault sensitization
– Fault Propagation
– Justification
• It will generate 31
possible patterns
for given fault

• TPG generates “Many patterns for one fault”
• Do we really need this many patterns for one fault?
• TPG is the time consuming iterative process.
• As the number of fault is large, the TPG is to be
executed for each of the fault.
• Why not to have “One pattern for many faults”?
• Fault simulation
Comparatively fault simulation is easy and fast

• Randomly selecting
any pattern
– 1 0 0 0 1-----11111
– This pattern generates
0 on o/p of G1, 1 on
G2 to G5 and 0 on G6
– Hence it can detect sa1
on G
– 1 1-----11111
– This pattern can detect
sa0 on any net
• Two pattern can
detect 33 faults!

Fault Simulation process
1. Generate a random pattern
2. Determine the output of the circuit for that random pattern as
input
3. Take fault from the fault list and modify the Boolean
functionally of the gate whose input has the fault.
4. Determine output of the circuit with fault for that random
pattern as input.
5. If the output of normal circuit varies from the one with fault,
then the random pattern detects the fault under consideration.
6. f the fault is detected, it is removed from the fault list.
7. Steps 3 to 6 are repeated for another fault in the list. This
continues till all faults are considered.
8. Steps 1 to 7 are repeated for another random pattern. This
continues till all faults are detected.

Major Steps of Fault Simulation
1. Generate random pattern
2. For given pattern, find the golden output of the
fault free circuit (Circuit/Logic Simulation)
3. Insert the intended fault in the fault free circuit
4. Again apply the generated pattern and find the
output of the circuit in presence of fault (Fault
Simulation)

Circuit (Logic)
Simulators

Simulator
• Definition
– Simulation refers to modelling of a design, eg. its function
and performance.
• A software simulator is a computer program
• An emulator is a hardware simulator
• Simulator is used for design verification
– Validate assumptions
– Verify logic
– Verify performance (timing)

Simulator-Block Diagram
Specification
Circuit
Description
Simulated
Responses
Input Stimuli
Expected
Responses
Manual design
or via Synthesis
Testbench
Development
Response
Analysis
Bug?
Next Design
Stage
yes
no

Simulation Process

Abstraction Level for Simulator
• System level
• Architecture level
• Functional level/RTL level
• Gate/structural level
• Switch/transistor/circuit level
• Mixed level

Modelling
• Modules, blocks or components described by
– Input/output (I/O) function
– Delays associated with I/y /O signals
– Examples: binary adder, Boolean gate, etc.
• Interconnects represent
– Ideal signal carriers or ideal electrical conductors
• Netlist
– A format (or language) that describes a design as an
interconnection of modules. Netlist may use hierarchy.

Signal States
• Two-states (0, 1) can be used for purely
combinational logic with zero-delay.
• Three-states (0, 1, X) are essential for timing
hazards and for sequential logic initialization.
• Four-states (0, 1, X, Z) are essential for MOS
devices. See example below.
• Analog signals are used for exact timing of digital
logic and for analog circuits.

Information Loss in ternary Logic
• Simulation based on ternary logic is pessimistic
• A signal may be reported as unknown when its value can be
uniquely determined as 0 or 1
A
B
C u
u
u
u
u
K
G2
G4
G3G1
0
1
A
B
C 0 or 1
0
1 or 0
0 or 1
0 or 1
K
G2
G4
G3G1
0
1

Gate Evaluation Method
• Choice of evaluation technique depends on
– Considered logic symbols
– Types and models of logic elements
• Commonly used approaches
– Truth table based
– Input scanning
– Input counting
– Parallel gate evaluation

Truth Table Based
• The most straightforward and easy to implement
– For binary logic, 2n entries for n-input logic
element
– May use the input value as table index
– Table size increases exponentially with the
number of inputs
• Could be inefficient for multi-valued logic
– A k-symbol logic system requires a table of 2mn
entries for an n-input logic element
• m = log2k
• Table indexed by mn-bit words

Input Scanning Based
• The gate output can be determined by the types of
inputs
– If any of the inputs is the controlling value, the gate
output is ci
– Otherwise, if any of the inputs is u, the gate output is u
– Otherwise, the gate output is c'i
Table 3.2: Thec (controlling)and
i (inversion) values of basic gates
c i
AND 0 0
OR 1 0
NAND 0 1
NOR 1 1

Input Scanning

Input Counting Based
• Knowing the number of unknown and controlling
inputs is sufficient to evaluate the AND, OR, NAND
and NOR gates
• c_count, u_count
• When any gate input is changed, these two
variables are updated.
• Suppose, for NOR, one of the input changes from 1
to u, then c_count is decreased and u_count is
increases.
• Then similar to input scanning…

Simulator
• Event driven
• Cycle Based
• Compiled Code

Event Driven Simulator
• Event: change in logic value at a node, at a certain instant of
time ® (V,T)
• Performs both timing and functional verification
– All nodes are visible
– Glitches are detected
• Most heavily used and well-suited for all types of designs
• Uses a time wheel to manage the relationship between
components
• Time wheel = list of all events not processed yet, sorted in
time (complete ordering)
• When event is generated, it is put in the appropriate point in
the time wheel to ensure causality
• Faster compared to cycle based simulator because in large
logic circuits about 0.1 to 10% gates become active for an
input change

Event Driven Simulation

Event Driven Simulation FlowChart

Efficiency of Event Based Simulator
• Simulates events (value changes) only
• Speed up over compiled-code can be ten times or
more; in large logic circuits about 0.1 to 10% gates
become active for an input change
Large logic
block without
activity
Steady 0
0 to 1 event
Steady 0
(no event)

Cycle Based Simulator
• Take advantage of the fact that most digital designs
are largely synchronous (state elements change
value on active edge of clock)
• Compute steady-state response of the circuit
• at each clock cycle
• at each boundary node
• Only boundary nodes are evaluated

Compiled Code Simulation
• To translate the logic network into series of
machine instruction
• Logic Optimization and Levelization is performed
before actual code generation process

Logic Optimization

Levelization

Code generation and Simulation

Compiled Code Simulation
• Applicable to zero-delay combinational logic
• Also used for cycle-accurate synchronous sequential circuits
for logic verification
• Efficient for highly active circuits, but inefficient for low-
activity circuits
• High-level (e.g., C language) models can be used

Fault Simulation
• Fault simulation
– In general, simulating a circuit in the presence
of faults is known as fault simulation
– Predicts the behavior of faulty circuits As a
consequence of inevitable fabrication process
imperfections
• The main goals of fault simulation
– Measuring the effectiveness of the test patterns
– Guiding the test pattern generator program
– Generating fault dictionaries

Fault Simulation…..
• Outputs of fault simulation
– Fault coverage - fraction (or percentage) of
modeled faults detected by test vectors
– Set of undetected faults
• An important tool for test and diagnosis
– Estimate fault coverage
– Fault simulator
– Test compaction
– Fault diagnosis

Fault Simulation Tasks
• What is fault simulation?
– Given
• A circuit
• A set of test patterns
• A fault model
– Determine
• Faulty outputs
• Undetected faults
• Fault coverage

Time Complexity
of Fault Simulator
• Proportional to
– n: Circuit size, number of logic gates
– p: Number of test patterns
– f : Number of modeled faults
• Since f is roughly proportional to n, the overall time
complexity is O(pn2)

Faults
• Mostly single stuck-at faults
• Sometimes stuck-open, transition, and path-delay
faults; analog circuit fault simulators are not yet in
common use
• Equivalence fault collapsing of single stuck-at
faults
• Fault-dropping -- a fault once detected is dropped
from consideration as more vectors are simulated;
fault-dropping may be suppressed for diagnosis
• Fault sampling -- a random sample of faults is
simulated when the circuit is large

Fault Simulator (in detail)

Serial Fault Simulation
• First, perform fault-free logic simulation on the original circuit
– Good (fault-free) response
• For each fault, perform fault injection and logic simulation
– Modify netlist by injecting one fault
– Simulate modified netlist, vector by vector, comparing responses
with saved responses
– If response differs, report fault detection and suspend simulation
of remaining vectors
• Advantages:
• Easy to implement; needs only a true-value simulator, less
memory
• Most faults, including analog faults, can be simulated

Serial Fault Simulator (cont.)
• Disadvantage: Much repeated computation; CPU
time prohibitive for VLSI circuits
• Alternative: Simulate many faults together
03-12-2019 Dr Usha Mehta 40Courtesy: Agrawal & Bushnell

Parallel Simulators
• To speed up the logic simulation
• To simulate the concurrency on host computer
where there is 32-64 bit wide processor available
• For four bit data word, parallelism of four input
combinations are possible, e.g.
• abc = {110, 010, 011, 100}

Parallel Fault Simulation
• Compiled-code method; best with two-states (0,1)
• Exploits inherent bit-parallelism of logic operations
on computer words
• Storage: one word per line for two-state simulation
• Multi-pass simulation: Each pass simulates w-1
new faults, where w is the machine word length
• Speed up over serial method ~ w-1
• Not suitable for circuits with timing-critical and
non-Boolean logic

Courtesy: Agrawal & Bushnell

Parallel Simulation of
Multivalued Logic
• For three valued logic
• For w bit data words, two words denoted by X1 and X2
are used for signal X
• AND and OR are still same
• The compliment operation is :
• Note that the compliment of u is still unknown i.e. u

Limitations of Parallel Fault
Simulation
• Useful for two (1,0) or three (0,1,X) logic values, not
suitable for multiple logic values, e.g. (0,1,U,R,F,…)
– Multiple logic values can be handled but operations are
complex
• Wasted computations
– Fault dropping not carried out effectively
– Not possible to discard faults that are in the same word

Fault Simulation (Testing of VLSI Design)

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