Jay_Vicory_Resume_2018

Jay Vicory
36 Galloway Road
Chelmsford, MA 01824
Phone (617) 999 - 4259
mailto:vicorjh@silicon-works.net

PROFESSIONAL SUMMARY
Engineering Practice and Management
 Experienced with developing long term strategic development plans that address internal and
external customer needs, reusability, quality, and cost containment.
 Experienced in the identification of system requirements from marketing through customer
interaction over the life cycle of a project.
 Experienced with distilling, defining, and clarifying interim objectives and milestones as
required to meet business objectives while addressing both short and long term deliverable
goals.
 Experienced with managing across domain expertise including hardware, software and
mechanical development.
 Experienced in the decomposition of system engineering problems into disparate
components and in the definition of component interface and integration.
 Extensive embedded system development experience throughout the development cycle
from research and conceptualization to postmortem analysis.
 Experienced in the mitigation of design and implementation risk and planning for product
migration.
 Experienced in constraint driven system design including design for manufacturing,
mechanical footprint, unit cost, and operating environment.
 Experience and exposure to quality focused environments including FIT analysis, FMEA,
accelerated environmental testing, unit testing, issue tracking, and EOL/manufacturing test.
 Experienced with small business development, logistics, accounting, payroll, accounts
payable / receivable, tax compliance, contract development, SBIR.
 Consulting engineer with extensive experience supporting client development efforts.
 Extensive experience generating and managing internal and end-user focused
documentation.
Embedded Hardware and FPGA Development
 Architectural and system level design.
 Full lifecycle hardware/firmware/software development.
 Experienced with design for manufacturability.
 FPGA architecture and development with emphasis on HDL including Verilog and VHDL.
 Mixed signal, algorithmic pipeline, and signal processing design experience.
 Experienced with design for signal integrity and EM compliance.
 Experienced with a full range of engineering software tools.
 Mechanical form and fit, thermal evaluation, reliability evaluation, and rapid prototyping
experience.
 Hands-on development and extensive experience with typical hardware development tools
including logic analyzers, oscilloscopes, and hardware emulation.
Embedded Software and System Development
 Low-level design and hardware interaction experience including BSP development, platform
integration, and board / design bring-up.
 Experienced in the implementation and utilization of a variety of real time operating systems
including embedded Linux and associated boot loaders.
 Experienced software development for a variety embedded system architectures including
FPGA and DSP based systems. CUDA based signal and image processing.

FORMAL EDUCATION
Boston University, Boston, MA
Masters of Science in Computer Science
Additional Concentrations: Security, Computer Networks
Milwaukee School of Engineering, Milwaukee, Wisconsin
Bachelor of Science in Electrical Engineering
PROFESSIONAL EXPERIENCE
June 2004 to SiliconWorks Corporation
Present Director / Consulting Engineer
SiliconWorks Corporation is a privately owned C corporation that engages and assists external clients
with diverse and complex engineering needs ranging from conceptual project definition, architectural
development, physical engineering, and post-mortem analysis. Clients include Corning Incorporated,
DuPont Photonics, MIT Lincoln Laboratory, Shure, Bolton Engineering, Innovative Photonics, Extreme
Electronic Designs (NASA/MIT), and Summit Technologies.
 HDL development and test of a scalable multi-channel phase generator with event sequencer
utilizing an Altera Cyclone V Arm based SOC for use as a multi-phase liquid lens controller.
Customized generation of the SOC/FPGA fabric, boot chain, and kernel.
 Project lead. Architectural, design, and implementation responsibilities for a small form factor
high speed arbitrary waveform generator (4 GSPS). Digital design, HDL, documentation,
operating system development, bring-up, and test responsibilities in a partnered arrangement.
HDL and architectural implementation based on a Xilinx Kintex-7 FPGA. Design included the
implementation of a soft-core controller that was internally interfaced to a high-speed timing
aligned DDR waveform synthesis block.
 Project lead. Design and development of a prototype high-fidelity fingerprint image analysis
platform utilizing custom Nvidia CUDA based image processing algorithms executing on an
Nvidia TX1 platform. Image capture, websockets based streaming video, user interface control
GUI, and image processing algorithms written in C++ and C#. Algorithms written to utilize
OpenCV core routines.
 Project lead. Footprint constrained hardware development of a laser based Raman spectroscopy
platform. Mixed signal design including the utilization of FPGAs, high speed DACs, closed loop
thermal electric cooling, and high speed / high current closed loop laser diode gain control.
 Project lead. Cost and footprint constrained hardware, software, and FPGA development of high
density laser projection platforms. Multiple unique road-mapped designs. Mixed signal designs
including the utilization of FPGAs, high speed DACs, high speed ADCs, and high speed / high
current laser diode gain control. Fully documented designs including end-user guides and a PC
based interface GUI.
 Project lead. Unit cost and footprint constrained hardware, software, and FPGA development of
a high density reduced footprint digital controller utilizing an Altera Cyclone III FPGA with
stackable daughter card capability. Voltage translated high speed stackable daughter card
interface. NIOS II soft-IP microprocessor interface to 400 MHz DDR2 memory. FPGA firmware in
Verilog. Fully documented design including engineering and end-user guides.

 Project lead. Hardware development of a digital video processing system utilizing DVI-I
(analog/digital video IO) interfaced to an Altera Stratix2GX FPGA. Design includes a dual channel
bidirectional RapidIO interface for expansion, associated power supplies and protection circuitry,
and thermal control circuitry. FPGA firmware written in Verilog.
 RFID tag design with an embedded PCB antenna utilizing an RFID to I2C interface. RF design for
a proprietary patent pending purpose. Power harvesting RFID memory with I2C interface.
Freescale low power microcontroller. Embedded PCB antenna(s). Pass through SFP transceiver
interface.
 VHDL development for a long-haul infrared transceiver / switch ROADM. System GLU, control,
and interface (I2C) FPGA firmware written in VHDL for the DuPont Photonics iRoad ROADM.
 EMC compliance and emissions consultation, analysis, and design updates on a high-end
conferencing system for a large professional audio company. Non-destructive modifications for a
design that was failing class-A emissions testing. Certified Class-A compliance after extensive
chamber evaluation and testing.
 UHF amplitude shift key design for miniaturization of a radio transmitter for a large professional
audio company. Research and design project to evaluate implementation of an ASK transmitter in
a Cypress PSOC reconfigurable mixed signal chipset.
 Embedded Linux development including boot (U-boot) and kernel 2.4.x/2.6.x (uClinux) ports to
the Analog Device Blackfin processor series and the Xilinx Virtex II Pro PowerPC core based
FPGA.
 Software lead. Port of embedded Linux and a custom boot kernel to the Analog Device Blackfin
series DSP. Port and development of a customized U-Boot boot loader for an up-coming
consumer product. Kernel IDE/ATA driver development and BSP for a consumer based product.
Implementation of custom USB device drivers.
 Project lead. Hardware and software development for a consumer oriented VOIP end-point.
 Development of a custom dual-mode USB device driver for streaming MPEG video using RNDIS
and CDC Ethernet communication layers for an IXP425 ARM based embedded Linux system
(Motorola NIM100 MoCA).
 HDL development of an AES Rijndael cryptographic core, an encryption software package for
multiple OS platforms, and Megaco stack development.
 Architectural development of an FPGA based JPEG2000 HD-SDI video compression controller.
Streaming SMPTE HD video format encoding and decoding written in Verilog. ADI codec
interface written in Verilog. SPI4 core integration. Architectural contribution to the design
specifications.

September 2014 to Broadcom Corporation
October 2015 Principal Engineer
Broadcom Corporation is a leading global semiconductor development and manufacturing firm.
 ARM AARCH64 (A57) based SOC silicon bring-up (64-bit A57 based SOC consisting of a quad
core processor cluster along with a variety of advanced technology peripherals).
 Lead and develop the internal software security architecture roadmap.
 Port, integrate, and test Arm Trusted Firmware on a first generation custom SOC architecture.
 Secure chain of trust boot and overall ARM Trustzone implementation.
 Silicon debug in conjunction with the IC, verification, hardware, and software teams.
 ARM Fastmodel simulation and development.
March 2012 to DAG ( MIT Lincoln Laboratory )
October 2013 Consulting Engineer
MIT Lincoln Laboratory is a federally funded research and development laboratory that is involved in the
research and development of advanced technologies for use in US defense and commerce.
 Team based architectural development of a high performance software defined radio system with
beam-formed MIMO and HDLC backchannels.
 Bring-up of a multi-target 25.6 Gbps AURORA based backplane architecture.
 Architectural/firmware/software design and development of an intent purposed Virtex-6 FPGA
based network processor including multiple scatter gather DMA engines, a soft-IP Microblaze
processor, and an interrupt/queue based operating system executing across an AXI (ARM)
protocol bus.
 Development of a Matlab GUI for quadrature RF signal analysis of streaming RX data.
 Development of embedded FTP, streaming data, and command and control servers.
 Development of a custom s-record boot-loader system.
 Network stack integration and performance optimization.
 Development of generic data processing tools for system bring-up and debug.
 Port and integration of a write-leveling FLASH file system.
 MIT rapid prototyping X-Tec award (2nd
).

June 2000 to Aspect
June 2004 DSP Engineer
Aspect Software is a global leader in the development of telecommunication products for use in call
center and IVR applications.
 Project lead. Embedded Linux development for a Motorola PowerQUICC based platform.
 Project lead. Designed and brought to production a high capacity T1/E1 telephony interface
board.
 Project lead. Design and implementation of an any-to-any conferencing switch with DSP in
Verilog. Custom 128 channel by “N” control bridge any-to-any audio conferencing with a-law / u-
law transcoding. Implementation in Verilog and targeted to a Xilinx Virtex 2 FPGA. Patent
awarded.
 Improvements to a high-speed design compliance (class A to class B) utilizing signal integrity and
emissions modeling.
 Developed audio conferencing and companding algorithms for HDL implementation. Linear coded
audio to A-law companding, linear coded audio to Mu-law companding, Mu-law to linear
encoding, A-law to linear encoding, and Mu-law to A-law transcoding written in Verilog.
 Designed and developed firmware for an OC-3 ATM SAR on an embedded telephony board.
Abstracted board support package for an OC-3 rate ATM Segmentation and Reassembly ASIC.
 Port of an ISDN primary rate stack and protocol enhancements for world-wide use.
 Developed enhancements for both hardware and software to meet international compliance test
requirements.
 Developed an architectural design for a multi-DSP packet processor.
 Developed an FPGA / Boot flash sharing scheme for cost reduction.
June 99 to Raytheon Systems - Signal Processing Section
June 2000 Senior Engineer
Raytheon is a global leader in the development of technology-driven solutions that provide integrated
mission systems for critical defense, cybersecurity, and non-defense needs.
 Member of a large team developing signal processing for advanced ground based radar systems.
 Involved with the implementation, optimization, test, and analysis of algorithms for a real-time
multi-processor system.
 Developed a reusable vector, highly parallel, and optimized math library for the Theater High-
Altitude Area Defense (THAAD) and other X-band radar systems for Raytheon Systems.
 Developed a client/server application for the test of the Tartar naval radar under VxWorks.
 Developed ASIC functional test beds for a custom phase array radar ASIC design in VHDL.
 Integrated a 100mBit Fiber PMC interface on an embedded VxWorks based COTS system.
 Developed a kernel mode RAM disk for a VxWorks based COTS system.
 Developed radar return signal processing software for a multi-processor platform (HP Convex).

January 97 to CGN and Associates ( Caterpillar )
June 99 Software Engineer
Caterpillar is the world leader in the manufacturing of construction and mining equipment, diesel and
natural gas engines, industrial gas turbines and diesel-electric locomotives.
 Design and implementation of end-of-line test software for the next generation of Caterpillar
engine (ADEM3) and machine control (ABL) modules.
 Responsible for embedded systems bring-up.
 Interfaced with the core teams involved with hardware, software, and manufacturing to create
a robust system increasing quality and reducing manufacturing defects. Served as the point
of contact for manufacturing issue resolution. Developed manufacturing test specifications.
Responsible for ensuring the health of the production test process.
 I was instrumental in solving several challenging production and design issues leading to
increased quality and lowered cost.
 Developed an architecture and documentation for a reusable software package for the next
generation of 32-bit Caterpillar engine and machine control modules. The architecture
included a standardized interface protocol providing the ability to utilize the embedded
software from various front-end tools. This tool assisted both the production and hardware
development team’s development and testing tasks including the ability to perform early
emissions testing. The architecture utilized a “plug and play” scheme to allow for rapid
software customization. Overall effect was the reduction of development man-hours and
improved end quality of the finished design.
 Followed several designs into production and was key in the reduction of the per-unit testing
time (5 minutes to less than 1 minute per module) realizing a significant production cost
savings. The Adem3 engine control module, at the time, was being produced at about 200K
per year and was continuing to ramp up. The field return rate was less than one percent and
falling. This is largely due to the test software since it has been instrumental in uncovering
manufacturing and supplier defects.
PUBLICATIONS AND MEMBERSHIPS:
“An Efficient Multiplexed Conferencing Engine”, United States Patent 7,688,961.

ADDITIONAL EDUCATION AND EXPERIENCE
 Engineering Specific Continuing Education: VHDL design coursework provided by Mentor
Graphics, PowerPC architecture and design coursework, High Speed Design Signal Integrity
coursework (Mentor Graphics / Esperan), a variety of vendor specific coursework for FPGA
and microcontroller development. The Linux Foundation Kernel Internals certification. ARM
A53/A57 Training.
 FPGA Silicon and IP: Xilinx and Altera FPGAs and CPLDs. Altera soft-ip CPUs NIOS/NIOS2.
Altera ARM hard-ip. Xilinx soft-ip Microblaze CPU. Xilinx PPC Virtex2 PRO hard-ip. Lattice
CPLDs. Third party soft-IP including DDR controllers, UARTs, Ethernet MACs, and
configuration controllers.
 FPGA Development Tools: Xilinx ISE/Vivado, Altera Quartus, Mentor Graphics HDL
Designer, Mentor Graphics Modelsim, Mentor Graphics Catapult (C to HDL), Leonardo
Spectrum/Precision.
 Embedded OS: Embedded Linux kernels, U-Boot. Arm Trusted Firmware and Trustzone.
VRTX RTOS, TI DSP BIOS, uC/OS, and other various RTOS.
 Bring-up Development Tools: Including In-Circuit emulators, background and JTAG
debuggers, high speed oscilloscopes, logic analyzers, typical bench supplies and meters,
protocol analyzers, Agilent 89600 VSA, FLIR, and other specialty tools as required.
 Schematic, Layout, and Simulation Tools: Cadence Allegro/PCB Editor, Cadence
PSPICE/OrCAD, Cadence SpectraQuest/SigXplorer, Mentor Graphics Hyperlynx, Mentor
Graphics Viewdraw and ePD series, Mentor Graphics LP Wizard.
 Mechanical development tools: Dassault Solidworks.
 Configuration and Source Control Tools: Clearcase, CVS, Microsoft Team Foundation
Server, APEX, GIT.
 Embedded Code Development Tools: ARM DS-5, GNU toolchain and GDB, a variety of IDEs
and Eclipse implementations, Codewarrior, TI Code Composer Studio.
 PC Development Tools: Microsoft Visual Basic/Visual C++/C#, third party development
libraries.
 Miscellaneous Tools: Matlab and Simulink.
 Intent purposed USB, ATA, and ATAPI IDE device driver and hardware development.
 Miscellaneous Processor Families: ARM AARCH64 A57, NVidia TK1/TX1, Texas Instruments
Keystone II (ARM and C66X based SOC), Motorola MC68xxx, DSP56K, 68HCxx,
CAN/J1939, J1922, RS232, SPI, TI DSP C67x series, Motorola PowerQUICC III, Intel
XScale, Motorola MC9xxx series, TI Piccolo, ADI Blackfin BF5xx series, Freescale.

PORTFOLIO EXAMPLE: High Speed Arbitrary Waveform Generator
The following section is a short description of an embedded system design that was
developed, in a partnership arrangement, for MIT Lincoln Laboratory.
The high speed arbitrary waveform generator, illustrated in Figure 1, is the first design in a
series of high speed waveform generators capable of direct RF generation at up to 4 giga-
samples per second (GSPS) at 12-bits. This design was specifically targeted for a small form
factor (4in x 2in) footprint and for the generation of repetitive pulsed waveforms or continuous
periodic waveforms.
Figure 1: Small Form Factor High Speed Arbitrary Signal Generator
A Xilinx Kintex-7 was utilized as the digital waveform source used to drive a high-speed DAC
at 4 GSPS.
Figure 2: Test Waveform Example (no anti-aliasing filter)
The design was primary segmented into two clock domains, a high-speed waveform
generation domain and a slower control system domain. The high-speed domain utilized
delayed serializers/deserializers (SERDES) on a per bit basis with data sourced from internal
dual-ported BRAM. The slow control system domain was utilized to produce a user interface
via a USB to serial console, control operating parameters, perform calibration, generate test

waveforms, allow for the upload of user generated waveforms, and to program the waveform
for playback via the internal dual ported BRAM. A soft-IP Microblaze processor was utilized
as the core system controller with the operating system software written in “C”. VHDL was
chosen as the HDL language for this particular design.
The high-speed portion of the design was fully test-benched and simulated prior to receiving
hardware. Data flight delays were estimated from an interactive signal integrity analysis using
Cadence SigXplorer (Figure 3). With extensive data path simulation and verification, the
entire design was functional on the first pass from both a hardware and HDL perspective.
Figure 3: Data Flight Time Simulation Example
Responsibilities for this particular design include:
1. System architecture, design, and documentation.
2. HDL development and verification.
3. Digital system design and pin-out assignment and verification in conjunction with design
partner.
4. Pre and post layout signal integrity simulation. Analog system verification in conjunction
with design partner.
5. Operating system development including console terminal, test waveform generation,
BSP, and waveform upload written in ‘C’
6. System bring-up, test, and verification.
7. Mechanical prototype generation for customer consumption.
8. System user documentation.

PORTFOLIO EXAMPLE: Small form factor synthetic green laser controller
The following section is a short description of an embedded system design that I had
developed, as a consulting engineer, for the R&D division of large corporation.
The Small form factor synthetic green laser controller, illustrated in figure 2, is a customer
evaluation platform utilized to evaluate and test control algorithms for a proprietary synthetic
green laser. The synthetic green laser is a high quality and high modulation speed capable
laser for utilization in pico-projection or in applications that require tight wavelength and beam
control. Some typical applications include heads-up displays, handheld video projection,
Raman spectroscopy, and high power movie theater projection. This particular laser is being
developed for the mass market by the R&D arm of a large multi-national corporation.
Key design metrics for this design include: customer facing evaluation platform, form factor of
2 inch by 3 inch, unit BOM cost in quantities of 100 units to be less than $200, high quality
low noise, fault tolerant, utilization of a custom mixed mode Maxim drive ASIC, and
configuration flexibility to meet a diverse set of customer needs.
Figure 2: Small Form Factor Synthetic Green Laser Controller
This particular design includes several modes of laser gain control including manual (GUI
based) control, video gain control, and a high speed A/D based gain control for utilization in
pico-projectors.
Of the several laser gain control paths, the video gain path is supplied by a DVI-I interface
and decoder allowing for both analog and digital video input. The analog gain path is supplied
via a separate 100MHz high speed A/D 0-1V breakout PCB (not shown in the illustration).
The manual gain path is controlled via a USB to serial terminal interface (NIOS II terminal
interface / host GUI).
A Cyclone III FPGA is utilized to provide interface GLU including gain path multiplexing
between the three modes of gain control. The FPGA provides gain data to a high speed
Maxim laser driver and also interfaces to a Texas Instruments Piccolo microcontroller via I2C.
Closed loop laser control algorithms are implemented in C in the microcontroller. A
photodiode tap box interfaces with a TIA whose output is digitized and fed back into the
microcontroller based control algorithms. This forms a closed loop gain control. The laser
DBR section, in this instance, is driven by a duty adjusted PWM driver. Power into the DBR
section is adjusted by the closed loop gain control algorithms.

A sample of the laser modulation output result for this design is illustrated in figure 3.
Figure 3: Sample Scanned Projection (Green Laser Only)
Responsibilities for this particular design include:
1. Product lead. System architecture and design based, in part, on team generated
specifications. Responsible for the product roadmap, presentation, and negotiating
program management sign-off.
2. Project planning and management. Scheduling and moderation of design team meetings.
3. Interfaced with and developed product specifications based on feature request and
requirements from key customers including internal R&D staff and the external customer
base.
4. Architectural and development presentations to program executives and staff.
5. Schematic design including a mixed signal DVI-I video interface, power supplies, power
protection circuitry, custom laser driver ASIC integration, USB interface, TIA A/D, and
various interface and driver circuitry.
6. FPGA (Cyclone 3) board support package including an I2C interface, gain logic mux,
custom interface protocols, and proprietary laser control algorithms written in Verilog.
7. Microcontroller (TI Piccolo) I2C interface BSP written in C.
8. Breakout PCB consisting of a high speed A/D differential input converter and a debugger
interface.
9. Signal integrity and power supply integrity evaluation. Thermal evaluation.
10. Board bring-up tasks. Test and manufacturing support.
11. Form and fit. Management of layout and mechanical progress.
12. Interface GUI development and documentation.

PORTFOLIO EXAMPLE: Discrete Drive Synthetic Green Laser Controller
The following section is a short description of an embedded system design that I had
developed, as a consulting engineer, for the R&D division of large corporation.
The Small form factor discrete synthetic green laser controller, illustrated in Figure 4,
is a customer evaluation platform utilized to evaluate and test control algorithms for a
proprietary synthetic green laser.
The synthetic green laser is a high quality and high modulation speed capable laser
for utilization in pico-projection or in applications that require tight wavelength and
beam control. Some typical applications include heads-up displays, handheld video
projection, Raman spectroscopy, and high power movie theater projection.
Key design metrics for this design include: customer facing evaluation platform, form
factor of less than 2 inch by 3 inch, unit BOM cost in quantities of 100 units to be
less than $150, high quality low noise, improved power efficiency, fault tolerant,
discrete analog drive control circuitry, configuration flexibility to meet a diverse set of
customer needs, and in-field firmware update capable.
Figure 4: Small Form Factor Synthetic green Laser Controller
Unlike the previously illustrated design, this version does not utilize a discrete
microcontroller for system control. Instead, an FPGA based soft IP NIOS 2
microcontroller along with signal processing is utilized to drive a synthetic green
laser.
Discrete analog laser drive circuitry is utilized as opposed to a custom mixed mode
Maxim ASIC. The long term goal is the generation of a custom mixed signal ASIC
based on the generated FPGA and discrete drive circuitry designs.
This particular design includes several modes of laser gain control including manual
(GUI based) control, a high speed A/D and D/A, and differential gain pass-through.
The laser adaptive optics section (MEMS) is controlled by an FPGA based delta
sigma convertor (Verilog) and an external integrator. The DBR section of the laser is,
likewise, driven by a delta sigma convertor written in Verilog.
My responsibilities for this particular design includes:

1. Product lead. System architecture design based, in part, on team generated
specifications.
2. Project planning and management. Scheduling and moderation of design team
meetings.
3. Architectural and development presentations to program executives and staff.
4. Schematic design (Cadence OrCad) including a mixed signal DVI-I video
interface, power supplies, power protection circuitry, custom laser driver ASIC
integration, USB interface, TIA A/D, and various interface and driver circuitry.
5. FPGA (Altera Cyclone 3) board support package including an I2C interface, gain
logic mux, custom interface protocols, and proprietary laser control algorithms
written in Verilog.
6. Altera NIOS II soft-IP core BSP written is C.
7. Custom FPGA bootloader allowing multiple FPGA and microcontroller images.
8. XMODEM based USB in-field upgrade code written in C.
9. Breakout PCB consisting of a high speed A/D differential input converter and a
debugger interface.
10. Signal integrity and power supply integrity evaluation (Mentor Hyperlynx,
Cadence SigXplorer, and proprietary analysis tools).
11. Form and fit, management of layout and mechanical progress (Cadence Allegro,
Dassault Solidworks).
12. Various board bring-up tasks and manufacturing support.
13. Interface GUI (PC based host) and documentation (Adobe Framemaker).

PORTFOLIO EXAMPLE: Small Form Factor Digital Controller
The small form factor digital controller is an FPGA based stackable module for use in a
configurable multi-intent purposed system. The design is such to provide a great deal a
flexibility for repurposing the design for a variety of system architectures.
Figure 5: Small Form Factor Digital Controller (2 inch x 3 inch)
The design provides an Altera Cyclone III FPGA, 400MHz DDR2 system memory, high
output system supplies, overvoltage, reverse supply, and transient input supply protection, a
large segmented high speed translation bus, temperature monitoring, and an USB to serial
interface for command and control.
Responsibilities for this design includes:
1. System architecture and design for a reconfigurable "stackable" system.
2. Schematic design (Cadence OrCad) including power supplies, FPGA (Cyclone 3),
USB, and other PCB features.
3. FPGA board support package (BSP) written in Verilog.
4. Custom NIOS II soft core processor implementation and integration.
5. Custom NIOS || board support package written in C.
6. Integration of custom signal processing algorithms based in Verilog.
7. Timing analysis and verification for the high speed sections.
8. Signal integrity analysis. Design for power supply impedance evaluation and
analysis.
9. DDR2 Memory with FPGA based soft core DDR controller implementation and timing
analysis.
10. Thermal evaluation (FLIR under stressed operating conditions).
11. Form and fit. Rapid-prototyping using Solidworks STL.
12. Product lead. Concept presentation, architecture, design documentation and
support.

PORTFOLIO EXAMPLE: Digital Video Processing System
The digital video processing system, illustrated in figure 6, is a platform developed to serve
as a test bed for the development of video processing algorithms.
Figure 6: Digital Video Processing System
The system provides DVI-I (digital and analog) decoded input, DVI-I encoded video output,
VGA video output, EDID interface, high speed A/D, High speed D/A output, SDRAM system
memory, an Altera Stratix II FPGA, a RapidIO interface bus, temperature monitor, a
tachometer based fan controller, and several additional expansion buses.
1. System architecture and design.
2. Schematic design (Cadence OrCad) including power supplies, FPGA, Video encoders
and decoder, and other PCB features.
4. Custom NIOS II soft core processor implementation and integration.
5. Custom NIOS || board support package written in C.
6. Integration of custom signal processing algorithms based in Verilog.
7. Timing analysis and verification for the high speed sections.
8. Signal integrity analysis. Design for power supply impedance evaluation and analysis.
9. Form and fit. Rapid-prototyping using Solidworks STL.
10. Product lead. Project management, design documentation, and presentation.

PORTFOLIO EXAMPLE: T1/E1 Telephony Processor
The T1/E1 Telephony Processor, illustrated in figure 7, consists of five configurable
T1/E1 telecom interface ports, a TI C6701 Digital Signal Processor, network clock
synchronization capability, SDRAM system memory, a Xilinx Virtex 2 FPGA, and a Xilinx
System ACE configuration controller.
Figure 7: Five Span T1/E1 Telephony Interface PCB
This board provides telecom audio multiplexing and de-multiplexing across 150 TDM
channels, International ISDN PRI call signaling, a 128 x 3 any-to-any audio conference
processor (FPGA), and audio signal processing for tone and call progress detection
(DSP). The multiplexed TDM channels are made available to a proprietary backplane
interface where an additional ten interface cards and a master system controller may be
available. With the backplane fully populated with T1/E1 interface cards, the system is
capable of real-time telecom switching and live call processing across 1500 channels per
chassis.
1. Schematic design (Mentor Viewdraw / DxDesigner) including power supplies, FPGA,
and other PCB features.
3. Custom FPGA GLU and conferencing support written in Verilog.
4. Board support package written in C.
5. Board bring-up and RTOS integration (TI DSP BIOS).
6. ISDN primary rate stack integration port written in C. Supporting International ISDN
modification to communication stack in C.
7. Signal integrity analysis. Designed for Class B EMI/EMC compliance.
8. Project lead, technical design documentation, and technical support.

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