EMBEDDED SYSTEM BASICS

EMBEDDED SYSTEM BASICS
POWERED BY
RANA ALI

Interface Analog voltage
• Interfacing ACS 712 current sensor
• Measuring current and give voltage output

ACS712 relation between Current on
Output voltage

Driving ACS 712 formula
Input current Output voltage ADC value
-30 A 0 V 0
0 A 2.5 V 512
+30 A 5 V 1023
Y = MX + B
And
M = (y2-y1) / (x2 – x1)
M = ( 1023 – 0 ) / (30 – (-30))
M = 1023 / 60
M = 17.05
Y = MX + B
Y = 17.05X + 512
X = (Y – 512) / 17.05

Difference between Microprocessor
and FPGA

FPGA SoC
Assignment: Write difference between the
following
• Hardcore FPGA
• Softcore FPGA

Protocol
• UART
• JTAG
• I2C
• SPI
• CAN

Serial vs Parallel Communication

Serial Communication in Arduino UNO
and Mega

Data Transmission Type
• (a) Simplex
• (b) Half Duplex
• (c) Full Duplex

JTAG
• JTAG is a Testing protocol
• It use to design and test board after
manufacturing
• It is on-chip instrument for digital Simulation
Joint Test Action Group

JTAG Pins
Daisy-chained JTAG (IEEE 1149.1)
The connector pins are
• TDI (Test Data In)
• TDO (Test Data Out)
• TCK (Test Clock)
• TMS (Test Mode Select)
• TRST (Test Reset) optional.
• Test reset signal is not shown in the image.

I2C Protocol
• I²C (Inter-Integrated Circuit) design by Phllips
• It is typically used for attaching lower-speed
peripheral ICs to processors
and microcontrollers in short-distance, intra-
board communication
• Some other vendor use same protocol by name
TWI (Two Wire Interface) or TWSI (Two-Wire
Serial Interface)

I2C Protocol
• I²C uses only two bidirectional open-
drain lines, Serial Data Line (SDA) and Serial
Clock Line (SCL), pulled up with resistors.
Typical voltages used are +5 V or +3.3 V
• It has adress space of 7-bit mean it interface
128 devices
• I²C bus speeds are the 100 kbit/s

SPI
(Serial Peripheral Interface)
• The Serial Peripheral Interface bus (SPI) is a
synchronous serial communication interface
specification used for short distance
communication.
• SPI devices communicate in full duplex mode.
• The interface was developed by Motorola.
• Typical applications include Secure Digital cards
and LCD.

SPI working
The SPI bus specifies five logic signals:
SCLK: Serial Clock (output from master)
MOSI: Master Output Slave Input, or
Master Out Slave In
(data output from master).
MISO: Master Input Slave Output, or
Master In Slave Out
(data output from slave).
SS: Slave Select
(often active low, output from master).

Independent slave configuration
• In the independent
slave configuration,
there is an
independent chip
select line for each
slave

Daisy chain configuration
• Only 4 wires are
user to interface
many device
• Sometime use in
place of JTAG

SPI Application
• Sensors: temperature, pressure, ADC, touch
screens, video game controllers
• Control devices: audio codecs, digital
potentiometers, DAC
• Camera lenses: Canon EF lens mount
• Communications: Ethernet
• Memory: flash and EEPROM
• Real-time clocks
• LCD, sometimes even for managing image data
• Any MMC or SD card (including SDIO variant[5])

SPI Example
• SCP1000 Barometric Pressure sensor

CAN Bus
• Controller Area Network (CAN bus)
• It is a vehicle bus standard designed to allow
microcontrollers and devices to communicate
with each other in applications without a host
computer

CAN
• The modern automobile may have as many as 70
Electronic Control Units (ECU)
• Typically the biggest processor is the Engine Control
Unit.
• Some of these form independent subsystems, but
communications among others are essential.
Transmission electric power steering
airbags audio systems
antilock power windows
Braking/ABS doors
cruise control mirror adjustment
battery and recharging systems for hybrid/electric cars

Before CAN Bus: Multi-wire Bus
•Electronic/engine Control Module (ECM)
• Body Control Module (BCM)

Comparing UART, I2C and SPI
• Data Transmission Type
Simplex, Half Duplex and Full Duplex
• Synchronous or Asynchronous
• Master/Slave or Independent
• Applications

Verilog Design Methodologies
Top-down Design Methodology
Bottom-up Design Methodology

Verilog Modules
A module is the basic building block in Verilog
Module Syntax
module <module_name> (<module_terminal_list>);
...
<module internals>
...
...
endmodule

Example
d Clk Q
0 0 Q0
0 1 0
1 0 Q0
1 1 1

Example

Verilog Simulation
Simulink programming
a = 0;
b = 0;
#100; //delay of 100 unit time
a = 0;
b = 1;
a = 1;
b = 0;
a = 1;
b = 1;

Verilog FPGA
Verilog is both a behavioral and a structural
Model(Switch level, Gate level and Dataflow ).
Internals of each module can be defined at four
levels of abstraction, depending on the needs of
the design
• Behavioral or algorithmic level
• Dataflow level
• Gate level
• Switch level

Switch level Modeling
Design using nmos and pmos logics
• pmos (out,data,control);
• cmos (w, datain, ncontrol, pcontrol);
• nmos (w, datain, ncontrol);
• pmos (w, datain, pcontrol);

Gate level Modeling
• Gates provide a much closer one to one mapping
between the actual circuit and the network
model
• Use in Small circuit design
• The and/or gates available in Verilog are shown
below.
and or xor nand nor xnor
• and a1(OUT, IN1, IN2);
• nand na1(OUT, IN1, IN2);
• or or1(OUT, IN1, IN2);
• nor nor1(OUT, IN1, IN2);

Dataflow Modeling
• assign out = in1 & in2;
• assign #10 out = in1 & in2;
// Delay in a continuous assign

Behavioral Modeling
• Design at this level resembles C programming more
than it resembles digital circuit design.
module clock_gen (output reg clock);
Initial //Initialize clock at time zero
clock = 1'b0;
always
#10 clock = ~clock; //Toggle clock every half-cycle
//time period = 20
initial
#1000 $finish; //Finish at 1000 unit clock
endmodule

Behavioral Modeling
• initial : initial blocks execute only once at time
zero (start execution at time zero).
• always : always blocks loop to execute over and
over again; in other words, as the name suggests,
it executes always.
module initial_example();
reg clk,reset,enable,data;
initial
begin
clk = 0;
reset = 0;
enable = 0;
data = 0;
end
endmodule
module always_example();
reg clk,reset,enable,q_in,data;
always @ (posedge clk)
if (reset)
begin
data <= 0;
end
else if (enable)
begin
data <= q_in;
end
endmodule

Blocking vs. Non-blocking
Assignments

Blocking vs. Non-blocking
Assignments Example

EMBEDDED SYSTEM BASICS

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