A high performance fir filter architecture for fixed and reconfigurable applications
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This paper presents a low-complexity MIMO detector for SC-FDMA systems, leveraging an initial MMSE estimate and refining it by identifying less reliable symbols. The high-throughput VLSI architecture demonstrates superior performance compared to conventional MMSE detectors with significantly lower complexity, achieving remarkable throughput rates. Additionally, a soft version of the detector tailored for coded systems is also proposed.
A high performance fir filter architecture for fixed and reconfigurable applications
- 1. A HIGH-THROUGHPUT VLSI ARCHITECTURE FOR HARD AND SOFT SC-FDMA MIMO DETECTORS ABSTRACT: This paper introduces a novel low-complexity multiple-input multiple-output (MIMO) detector tailored for single-carrier frequency division-multiple access (SC-FDMA) systems, suitable for efficient hardware mplementations. The proposed detector starts with an initial estimate of the transmittedsignal based on a minimum mean square error (MMSE) detector. Subsequently, it recognizes less reliable symbols for which morecandidates in the constellation are browsed to improve the initial estimate. An efficient high-throughput VLSI architecture is alsointroduced achieving a superior performance compared to the conventional MMSE detectors with less than 28% added complexity. The performance of the proposed design is close to the xisting maximum likelihood post-detection processing (ML-PDP) scheme, while resulting in a significantly lower complexity, i.e., 4.5*10^2and 7*10^4 times fewer Euclidean distance (ED) calculations in the 16-QAM and 64-QAM schemes, respectively. The proposed design for the 16-QAM schem is fabricated in a 0.13 um. CMOStechnology and fully tested, achieving a 1.332 Gbps throughput, reporting the first fabricated design for SC-FDMA MO detectors to-date. A soft version of the proposed architecture is also introduced, which is customized for coded systems.