Resume
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Md Imran Iqbal is seeking a position as a Memory Layout Design Engineer with 2.5 years of experience in VLSI layout development. He has worked on memory layouts including leafcell development, row decoders, sense amplifiers, and memory compilers. His skills include ICFB/Virtuoso layout tools, Calibre DRC/LVS, shell scripting, and Perl programming. Currently he is working on a row decoder layout and programming project for ST Microelectronics.
Resume
- 1. MD IMRAN IQBAL E-mail : [email protected] Mobile: (+91)-9540174833 Address : 4th floor H-50 Muradi Road , Batla House , Jamia Nagar , Okhla , New Delhi-110025. _____________________________________________________________ ___ Career Objective: To get absorbed in a competitive environment that offers opportunities to apply my technical knowledge blended with my skills while giving equal emphasis on leadership and teamwork and hence work towards mutual progress of self and enterprise. Work Experience : 2.5 year experience of memory layout design Memory Layout Design Engineer at Zia Semicondutor Pvt Ltd. Six months of training at Zia Semiconductor Pvt Ltd. Two and half years of industry experience (ST Microelectronics) in VLSI layout development as a memory layout design engineer having worked on multiple aspects of memory layout including Leafcell development and top level integration. Responsibilities: Memory layouts of I/O, Row-decoder, Control blocks. Sense Amplifier layout with consideration of all critical sense parameters. Memory instance level checks i.e DRC, LVS etc. Memory Compiler development. EM improvement. IR improvement. Compiler level checks i.e Layer summary, Antenna check, DFM, DRC, LVS etc. Tools used : ICFB/Virtuoso Layout design environment and layout/schematic editor. Calibre/Gemini DRC/LVS tools. Programming : Basic of Shell and Perl Current Project : BCD9S_SPULL(ST Microelectronics) Row Decoder layout and decoder programming. Cell Level DRC/LVS. Abutment checks. Top level checks DRC, DFM and LVS. EM IR checks and fixes.
- 2. Other Projects in ST MICROELECTRONICS • SPREG SRAM in 28nm FDSOI (ST MICROELECTRONICS) • Cell Level DRC/LVS. • Top Level Integration • DFM checks and Design changes. • EM IR check and fixes. • Top level DRC , LVS , DFM. • 28nm SOI_SRAM_SPHD_LOLEAK memory compiler for DFM updates DRC and DFM Checks. Design changes and compiler validation checks. • DRC/DFM/DK updates for following projects : ROM4T3ML_BCD6S SPGP_BCD9SL SPGP_BCD8SAUTO M40_DREG SOIBCD8S_SPULL SOIBCD8S_SPSMALL Training projects at Zia semiconductor : Floor planning Complete Bitcell array development considering critical bitcell layout Parameters(40nm), IO layout development including precharge mux and sense amplifier in Both 40nm and 28nm technology, Row-decoder layout development including via Programming(40nm),Compiler coding, Netlist development and Shell scripting. Academic Qualifications: Faculty of Engineering and Technology, Jamia Millia Islamia B.Tech in Electronics and Communication: C.P.I. of 7.6. Personal details: Permanent address : Churipatti Road Kishanganj Bihar 855107. Date of Birth : 27 DEC 1989.
- 3. Declaration: I certify that the above information is correct and complete to the best of my knowledge. Date : 04/07/2016 Place : New Delhi Md Imran Iqbal