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The document compares the radiation tolerance of different logic styles through simulations. It summarizes the critical charge values needed to induce soft errors like single event transients and soft delays in 45nm, 65nm and 90nm processes for common logic circuits implemented in CMOS, pass transistor logic and transmission gate styles. The results show transmission gates and pass transistor logic can tolerate higher critical charges than standard CMOS, making them more radiation tolerant for deep submicron technologies prone to soft errors from increased radiation sensitivity.
Thesis slides
- 1. A COMPARISON OF RADIATION TOLERANCE OF DIFFERENT LOGIC STYLES Thesis Defense May 2011 Parthivkumar Prajapati Thesis Advisor: Dr. Selahattin Sayil The Phillip M. Drayer Department of Electrical Engineering Lamar University Beaumont, TX 12/25/2012 Prajapati 1
- 2. Outline Introduction Different Logic Styles Simulations and Results Analysis Conclusion 12/25/2012 Prajapati 2
- 3. Introduction Motivation • With the continuous scaling of CMOS technologies, the device reliability and power dissipation become major issues. • Designers are now selecting different logic gate implementations to save the complexity of design and to minimize power issues. • The sensitivity of semiconductor devices can become a major cause of temporal or soft errors. 12/25/2012 Prajapati 3
- 4. Introduction Motivation • Soft error susceptibility can become cause of a system failure in deep submicron ICs. • Need to study the radiation sensitivity of different logic implementations and choose the better radiation tolerant design. • Need to find radiation sensitive nodes of different logic styles for reliable system design. 12/25/2012 Prajapati 4
- 5. Background Continues Downscaling Technologies Transistor Density increases, total power increases To reduce power consumption VDD are scaled down Charge to make a logic value at a circuit node decreases, noise margin decreases The systems are now susceptible to noise sources coming from radiation, cross talk, Power supply noise etc. 12/25/2012 Prajapati 5
- 6. Single Event Effects Single Event Hit on a Semiconductor Reference: Baumann R. “Soft Errors in Commercial Integration Integrated Circuits” 2004 12/25/2012 Prajapati 6
- 7. Single Event Effects SEE is generated due to a highly energetic particle strike to a sensitive node on a Semiconductor device. Main Sources: • High energy Neutrons • Alpha particles Higher SEEs as Technology advances due to smaller device sizes and lower noise margins with decreasing power supply voltage VDD. Single event phenomena can be classified into three effects • Single event upset (soft error) • Single event latchup (soft or hard error) • Single event burnout (hard failure) 12/25/2012 Prajapati 7
- 8. Single Event Effects Modeling of SE hit (The SE Current Pulse) Q t / t / I (t ) (e e ) • Q is the charge deposited by a particle strike, • τα is the charge collection time constant of the p-n junction, and • τβ is the ion-track establishment time constant. Reference: Baumann Double Exponential Current Pulse Model is R. “Soft Errors in Commercial Commonly used for Simulating Radiation Integration Integrated Effects Circuits” 2004 12/25/2012 Prajapati 8
- 9. Single Event Transient SET Generation in a CMOS Inverter • SET is a voltage glitch generated due to a particle strike at a semiconductor device. • It may be positive or negative depending on the input conditions. 12/25/2012 Prajapati 9
- 10. Single Event Soft Errors SET and SEU in a 6-stage Inverter 12/25/2012 Prajapati 10
- 11. Single Event Soft Errors SE Induced Soft Delay 12/25/2012 Prajapati 11
- 12. Single Event Soft Errors SE Induced Clock Jitter and Race 12/25/2012 Prajapati 12
- 13. Single Event Soft Errors SE Induced Crosstalk Noise (SECN) With the continuous shrinking in device sizes: • Device density is increasing rapidly in advanced ICs • Spacing between interconnecting metal wires is also constantly being reduced • Coupling capacitance between wires increases. The noise generated on the neighbor (victim) line from the affecting (aggressor) line switching is called Crosstalk Noise. 12/25/2012 Prajapati 13
- 14. Single Event Soft Errors SE Induced Crosstalk Delay (SECD) The delay generated in the victim signal caused by an SET at the aggressor line is called Single Event Crosstalk Delay (SECD). 12/25/2012 Prajapati 14
- 15. Different Logic Styles The high acceptance of low power VLSI integration added a crucial role to various design levels such as layout, circuit design, architecture, and fabrication technology. Designers are now selecting different logic gate implementations to save the complexity of design and to minimize power issues. Various Proposed logic styles are: • Complementary CMOS • Pass Transistor Logic • Transmission Gate • Gate Diffusion Input 12/25/2012 Prajapati 15
- 16. Complementary CMOS A complementary CMOS gate is a combination of two networks, called the pull-up network (PUN) and the pull-down network (PDN). Two networks of opposite type, in which the two conduction functions are complementary. Any logic function can be fully realized using NMOS as well as PMOS connecting between the Reference: Rabaey, J.M. Digital supply and the gate output. Integrated Circuits: A Design Perspective. 1994 12/25/2012 Prajapati 16
- 17. Complementary CMOS Advantages • Robustness against voltage and transistor scaling • High noise margin • Sufficient speed • Ease of Design Disadvantages • High input load • Weak output driving skill 12/25/2012 Prajapati 17
- 18. Pass Transistor Logic The basic difference of PTL compared to the CMOS logic style is that the source side of the logic transistor networks is connected to some input signals instead of the power lines. It consists of NMOS or PMOS pass transistor logic with CMOS output inverters Input inverters that buffer inputs and generates all signals for the pass transistor network 12/25/2012 Prajapati 18
- 19. Pass Transistor Logic The output buffers for speed improvement and voltage level restoration Many different pass-transistor logic styles have been proposed such as: • CPL • SRPL • DPL • LEAP • DPTL Reference: Reto Zimmermann and • EEPL Wolfgang Fichtner “Low-Power Logic • PPL Styles: CMOS Versus Pass-Transistor Logic” 1997 12/25/2012 Prajapati 19
- 20. Pass Transistor Logic Advantages • Compact layout • Reduces number of transistor count Disadvantages • Require inverter at the output for level restoration • Static power consumption 12/25/2012 Prajapati 20
- 21. Transmission Gate It builds on the complementary properties of NMOS and PMOS transistors: NMOS devices pass a strong 0 but a weak 1, while PMOS transistors pass a strong 1 but a weak 0. NMOS and PMOS logic networks are used in parallel and applied the complementary signals at the gate of each transistor. The control signal to the transmission gate is complementary 12/25/2012 Prajapati 21
- 22. Transmission Gate The transmission gate acts as a bidirectional switch controlled by the gate signal. Transmission gates can be used to build some complex gates very efficiently. 12/25/2012 Prajapati 22
- 23. Transmission Gate Advantages • Simple and efficient operation • Reduce voltage drop Disadvantages • Require more area • Require complement control signal • Increase transistor count 12/25/2012 Prajapati 23
- 24. Gate Diffusion Input The GDI basic cell seems like a CMOS inverter built in SOI or dual well CMOS process. The GDI cell contains three inputs: • G(common gate input of nMOS and pMOS) • P (input to the source/drain of pMOS) • N (input to the source/drain of nMOS) Bulks of both nMOS and pMOS are connected to N or P (respectively), so it can be arbitrarily biased at contrast with a CMOS inverter. 12/25/2012 Prajapati 24
- 25. Gate Diffusion Input Advantages • Reduce number of transistor count • Reduce supply voltage • Reduce Area, Power and Delay Disadvantages • Limitation with CMOS process • Increase manufacturing cost 12/25/2012 Prajapati 25
- 26. Gate Diffusion Input The all basic GDI logic gate functions cannot implement using the standard CMOS process. All GDI logic gate functions only possible in SOI or Twin well CMOS process 12/25/2012 Prajapati 26
- 27. Qualitative Comparisons Power Signal Logic Design Circuits Area (µm2) Consumptio Delay technique n (µW) (ps) CMOS 0.1521 2.283 39.66 C17 PTL 0.2028 18.17 81.32 TG 0.3042 5.146 51.82 CMOS 0.1901 4.894 53.43 C432 M2 PTL 0.2493 15.84 78.15 TG 0.3676 6.166 58.93 CMOS 0.2282 5.809 90.58 C6288 FA PTL 0.3042 20.61 168.00 TG 0.4563 12.32 118.8 12/25/2012 Prajapati 27
- 28. Simulations and Results Circuits used for Experiments: • NAND String • Random circuit • ISCAS-85 c17 • M2 module in ISCAS-85 c432 • Full Adder module in ISCAS-85 c6288 All these circuits were constructed using: • Standard CMOS, VDD =1.2V Software used: • Hspice, Custom Waveview Device Parameters: • 45nm,65 nm, and 90nm BSIM 4.0 model card, University of California Berkeley 12/25/2012 Prajapati 28
- 29. Simulations Radiation Sensitive nodes in TG NAND string When A=1 and B=1, Sensitive nodes are N1, N2 and OUT1 When A=1 and B=0, Sensitive nodes are N2 and OUT1 12/25/2012 Prajapati 29
- 30. Simulations 1.An example circuit (NAND String) is first constructed using a 45nm CMOS logic style 2. The value of A=1 B=1, and A=1 B=0 is considered, respectively for positive and negative critical charge calculation. 3. A energetic particle hit is applied at primary NAND gate sensitive node, O1. 4. The results of critical charges are obtained for a 45nm CMOS logic style. 5. Now, the same circuit is constructed using 65nm and 90nm CMOS logic style and results are obtained. 6. Steps 1-5 are repeated for logic style PTL and TG. 12/25/2012 Prajapati 30
- 31. 45nm 65nm 90nm Logic Sensitive Circuits Negative Positive Negative Positive Negative Positive Style node Qcrit Qcrit Qcrit Qcrit Qcrit Qcrit CMOS O1 14fc 5fc 17fc 7fc 21fc 9fc PTL O1 6fc 8fc 8fc 12fc 10fc 13fc NAND N1 N/A 14fc N/A 31fc N/A 33fc String TG N2 8fc 9fc 11fc 12fc 14fc 17fc O1 5fc 6fc 7fc 8fc 10fc 12fc CMOS OUT1 7fc 12fc 10fc 15fc 12fc 19fc Random PTL OUT1 8fc 13fc 10fc 16fc 12fc 20fc Circuit TG OUT1 7fc 12fc 10fc 16fc 14fc 19fc CMOS n7 8fc 6fc 10fc 7fc 12fc 9fc PTL n7 8fc 7fc 10fc 10fc 12fc 12fc C17 z3 N/A 14fc N/A 18fc N/A 27fc TG z4 8fc 9fc 11fc 12fc 14fc 15fc n7 5fc 6fc 7fc 8fc 9fc 11fc CMOS O1 8fc 9fc 10fc 11fc 12fc 13fc C432 M2 PTL O1 6fc 9fc 8fc 11fc 10fc 14fc TG O1 8fc 8fc 10fc 10fc 12fc 13fc CMOS n1 4fc 8fc 7fc 11fc 8fc 15fc z1 N/A 12fc N/A 13fc N/A 16fc PTL C6288 FA n1 7fc 9fc 9fc 11fc 12fc 14fc z2 9fc N/A 11fc N/A 15fc N/A TG n1 6fc 10fc 8fc 14fc 10fc 16fc 12/25/2012 Prajapati 31
- 32. Positive Charge for Soft Delay Sensitive Circuits Logic Style 200ps node 45nm 65nm 90nm CMOS O1 9.0fc 9.0fc 20.5fc PTL O1 12.0fc 13.0fc 17.5fc NAND String N1 42.0fc 52.0fc 62.0fc TG N2 21.0fc 25.7fc 28.0fc O1 16.0fc 20.5fc 24.0fc CMOS OUT1 23.5fc 28.0fc 30.0fc Random Circuit PTL OUT1 24.0fc 29.0fc 35.0fc TG OUT1 24.0fc 29.0fc 34.0fc CMOS n7 10.0fc 11.0fc 12.0fc PTL n7 11.0fc 13.5fc 17.0fc C17 z3 37.0fc 54.0fc 63.5fc TG z4 16.0fc 22.5fc 27.4fc n7 11.0fc 17.0fc 24.3fc CMOS O1 16.0fc 18.0fc 36.0fc C432 M2 PTL O1 25.0fc 31.0fc 35.0fc TG O1 24.0fc 29.0fc 34.3fc CMOS n1 20.4fc 24.0fc 26.0fc z1 29.0fc 36.5fc 39.0fc C6288 FA PTL n1 13.0fc 13.4fc 17.0fc TG n1 27.0fc 28.0fc 39.0fc 12/25/2012 Prajapati 32
- 33. Analysis Analysis Considerations are: • positive critical charge is assumed for SET generation in logic styles. • Lower critical charge node among the multiple sensitive nodes of logic style is considered. 12/25/2012 Prajapati 33
- 34. Critical Charge Comparisons in 90nm, 65 nm, and 45nm CMOS technologies 25 Critical Charge (fc) 20 15 10 CMOS 5 TG 0 PTL NAND Random c17 c432 M2 c6288 FA String Circuit 90nm 20 Critical Charge (fc) 15 10 5 CMOS 0 TG NAND Random c17 c432 M2 c6288 FA PTL String Circuit 65nm 12/25/2012 Prajapati 34
- 35. Critical Charge Comparisons in 90nm, 65 nm, and 45nm CMOS technologies 15 Critical Charge (fc) 10 5 CMOS 0 TG NAND Random c17 c432 M2 c6288 FA PTL String Circuit 45nm The value of critical charge (Qcrit) is least in CMOS logic style and highest in PTL logic style. 12/25/2012 Prajapati 35
- 36. Collected Charge comparisons for SD 200ps in 90nm, 65nm and 45nm CMOS technologies 50 Charge (fc) 40 30 20 CMOS 10 PTL 0 TG NAND Random c17 c432 M2 c6288 FA String Circuit 90nm 40 Charge (fc) 30 20 CMOS 10 PTL 0 TG NAND Random c17 c432 M2 c6288 FA String Circuit 65nm 12/25/2012 Prajapati 36
- 37. Collected Charge comparisons for SD 200ps in 90nm, 65nm and 45nm CMOS technologies 30 Charge (fc) 25 20 15 10 CMOS 5 PTL 0 TG NAND Random c17 c432 M2 c6288 FA String Circuit 45nm TG logic style requires more collected charges to generate the same value of SD than other logic styles. 12/25/2012 Prajapati 37
- 38. Conclusion PTL logic style is least sensitive to soft errors in comparison to Complementary CMOS and TG. TG implementation is the most radiation intolerant design among all other techniques considered. The logic gate implementations other than static CMOS technique have more than one sensitive node. 12/25/2012 Prajapati 38
- 39. Conclusion As transistor size decreases, combinational circuit becomes more susceptible to an energetic particle hit. TG logic style is less susceptible to Soft Delay Error. 12/25/2012 Prajapati 39
- 40. References • Rabaey, J.M. Digital Integrated Circuits: A Design Perspective. 1994 • Baumann R. “Soft Errors in Commercial Integration Integrated Circuits” 2004 • Reto Zimmermann and Wolfgang Fichtner “Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic” 1997 • Morgenshtein, A., A. Fish, and I.A. Wagner "Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits." 2002. • http://radhome.gsfc.nasa.gov/radhome/see.htm 12/25/2012 Prajapati 40
- 41. Questions and Comments 12/25/2012 Prajapati 41
- 42. Extras (a) (b) (c) (a) Electron hole path created by charged particle (b) Example of three different particle strike paths and (c) Experimental result of collected charges at different particle strike paths (Karnik, Hazucha and Patel 2004) 12/25/2012 Prajapati 42
- 43. Extras 12/25/2012 Prajapati 43
- 44. Thank You..!!! 12/25/2012 Prajapati 44
- 45. A COMPARISON OF RADIATION TOLERANCE OF DIFFERENT LOGIC STYLES 12/25/2012 Prajapati 45
Editor's Notes
- #7: After the generation of a dense track of free electron-hole pairs in the semiconductor due to a particle strike (a), carriers are rapidly collected by the electric field. Thus, the collected charge compensates the charge stored at the junction. The non-equilibrium charge distribution outside the depletion region produces a temporary funnel-shaped potential distortion along the track, which further increases charge collection by the drift (b). The funnel starts collapsing and charge collection continues due to the diffusion (c) until all excess carriers have been collected, recombined or diffused away from the junction area. Hence, the transient charge collected from a particle hit produces a current pulse at the junction area
- #34: 45nm
- #35: 45nm
- #37: 45nm
- #38: 45nm