05 internal memory
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1. The document discusses different types of semiconductor memory including RAM, ROM, PROM, EPROM, EEPROM, and flash memory. 2. It describes the operation and structure of both dynamic RAM (DRAM) and static RAM (SRAM). DRAM uses capacitors to store bits and requires refreshing, while SRAM uses flip-flops and does not require refreshing. 3. The document also covers various RAM technologies including synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Rambus DRAM (RDRAM), error correction codes, and cache DRAM.
05 internal memory
- 1. William Stallings Computer Organization and Architecture 8th Edition Chapter 5 Internal Memory
- 2. Semiconductor Memory Types Memory Type Category Erasure Write Mechanism Volatility Random-access memory (RAM) Read-write memory Electrically, byte-level Electrically Volatile Read-only memory (ROM) Read-only memory Not possible Masks Nonvolatile Programmable ROM (PROM) Electrically Erasable PROM (EPROM) Read-mostly memory UV light, chip-level Electrically Erasable PROM (EEPROM) Electrically, byte-level Flash memory Electrically, block-level
- 3. Semiconductor Memory ⢠RAM âMisnamed as all semiconductor memory is random access âRead/Write âVolatile âTemporary storage âStatic or dynamic
- 5. Dynamic RAM ⢠Bits stored as charge in capacitors ⢠Charges leak ⢠Need refreshing even when powered ⢠Simpler construction ⢠Smaller per bit ⢠Less expensive ⢠Need refresh circuits ⢠Slower ⢠Main memory ⢠Essentially analogue âLevel of charge determines value
- 7. DRAM Operation ⢠Address line active when bit read or written âTransistor switch closed (current flows) ⢠Write âVoltage to bit line â High for 1 low for 0 âThen signal address line â Transfers charge to capacitor ⢠Read âAddress line selected â transistor turns on âCharge from capacitor fed via bit line to sense amplifier â Compares with reference value to determine 0 or 1 âCapacitor charge must be restored
- 8. Static RAM ⢠Bits stored as on/off switches ⢠No charges to leak ⢠No refreshing needed when powered ⢠More complex construction ⢠Larger per bit ⢠More expensive ⢠Does not need refresh circuits ⢠Faster ⢠Cache ⢠Digital âUses flip-flops
- 10. Static RAM Operation ⢠Transistor arrangement gives stable logic state ⢠State 1 âC1 high, C2 low âT1 T4 off, T2 T3 on ⢠State 0 âC2 high, C1 low âT2 T3 off, T1 T4 on ⢠Address line transistors T5 T6 is switch ⢠Write â apply value to B & compliment to B ⢠Read â value is on line B
- 11. SRAM v DRAM ⢠Both volatile âPower needed to preserve data ⢠Dynamic cell âSimpler to build, smaller âMore dense âLess expensive âNeeds refresh âLarger memory units ⢠Static âFaster âCache
- 12. Read Only Memory (ROM) ⢠Permanent storage âNonvolatile ⢠Microprogramming (see later) ⢠Library subroutines ⢠Systems programs (BIOS) ⢠Function tables
- 13. Types of ROM ⢠Written during manufacture âVery expensive for small runs ⢠Programmable (once) âPROM âNeeds special equipment to program ⢠Read âmostlyâ âErasable Programmable (EPROM) â Erased by UV âElectrically Erasable (EEPROM) â Takes much longer to write than read âFlash memory â Erase whole memory electrically
- 14. Organisation in detail ⢠A 16Mbit chip can be organised as 1M of 16 bit words ⢠A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on ⢠A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array âReduces number of address pins â Multiplex row address and column address â 11 pins to address (211 =2048) â Adding one more pin doubles range of values so x4 capacity
- 15. Refreshing ⢠Refresh circuit included on chip ⢠Disable chip ⢠Count through rows ⢠Read & Write back ⢠Takes time ⢠Slows down apparent performance
- 16. Typical 16 Mb DRAM (4M x 4)
- 17. Packaging
- 20. Interleaved Memory ⢠Collection of DRAM chips ⢠Grouped into memory bank ⢠Banks independently service read or write requests ⢠K banks can service k requests simultaneously
- 21. Error Correction ⢠Hard Failure âPermanent defect ⢠Soft Error âRandom, non-destructive âNo permanent damage to memory ⢠Detected using Hamming error correcting code
- 22. Error Correcting Code Function
- 23. Advanced DRAM Organization ⢠Basic DRAM same since first RAM chips ⢠Enhanced DRAM âContains small SRAM as well âSRAM holds last line read (c.f. Cache!) ⢠Cache DRAM âLarger SRAM component âUse as cache or serial buffer
- 24. Synchronous DRAM (SDRAM) ⢠Access is synchronized with an external clock ⢠Address is presented to RAM ⢠RAM finds data (CPU waits in conventional DRAM) ⢠Since SDRAM moves data in time with system clock, CPU knows when data will be ready ⢠CPU does not have to wait, it can do something else ⢠Burst mode allows SDRAM to set up stream of data and fire it out in block ⢠DDR-SDRAM sends data twice per clock cycle (leading & trailing edge)
- 25. SDRAM
- 27. RAMBUS ⢠Adopted by Intel for Pentium & Itanium ⢠Main competitor to SDRAM ⢠Vertical package â all pins on one side ⢠Data exchange over 28 wires < cm long ⢠Bus addresses up to 320 RDRAM chips at 1.6Gbps ⢠Asynchronous block protocol â480ns access time âThen 1.6 Gbps
- 28. RAMBUS Diagram
- 29. DDR SDRAM ⢠SDRAM can only send data once per clock ⢠Double-data-rate SDRAM can send data twice per clock cycle âRising edge and falling edge
- 31. Simplified DRAM Read Timing
- 32. Cache DRAM ⢠Mitsubishi ⢠Integrates small SRAM cache (16 kb) onto generic DRAM chip ⢠Used as true cache â64-bit lines âEffective for ordinary random access ⢠To support serial access of block of data âE.g. refresh bit-mapped screen â CDRAM can prefetch data from DRAM into SRAM buffer â Subsequent accesses solely to SRAM
- 33. Reading ⢠The RAM Guide ⢠RDRAM