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Unit-1
Microcontroller
490
What is
Microcontroller?
Micro Controller
491
Very
Small
A mechanism that
controls the operation of a
machine
⌘ CPU for Computers
⌘ No RAM, ROM, I/O on CPU chip
itself
⌘ Example: Intel's x86, Motorola’s 680x0
492
⌘ A smaller computer
⌘ On-chip RAM, ROM, I/O
⌘poErtxsa..m.ple: Motorola’s 6811, Intel’s 8051,
Zilog’s Z8 and PIC
493
494
Microprocessor
⌘ CPU is stand-alone,
RAM, ROM, I/O, timer
are separate
⌘ Designer can decide on the
amount of ROM, RAM and
I/O ports.
⌘ Expansive
⌘ General-purpose
Microcontroller
⌘ CPU, RAM, ROM, I/O and
timer are all on a single chip
⌘ Fix amount of on-chip ROM,
RAM, I/O ports
⌘ For applications in which cost,
power and space are critical
⌘ Not Expansive
⌘ Single-purpose
495
⌘
Home
※ Appliances, intercom, telephones, security systems, garage
openers, answering machines, fax machines, home
computers, cable TV tuner, VCR, camcorder,
remote controls, video
door
TVs,
games,
cellular phones, musical instruments, sewing machines, lighting
equipment
control, paging, camera, pinball machines, toys, exercise
etc.
microwave,
Office
※ Telephones, computers, security systems, fax machines,
copier, laser printer, color printer, paging etc.
⌘ Auto
※ Trip computer, engine control, air bag, ABS, instrumentation, security
system, transmission control, entertainment, climate control,
cellular phone, keyless entry
496
497
UNIT 4 Syllabus
• Architecture of 8051
• Special Function Registers(SFRs)
• I/O Pins Ports and Circuits {Pin
Diagram}
• Instruction set
• Addressing modes
• Assembly language
programming
• PIC and ARM
499
⌘ The 8051 is a subset of the
8052
⌘ The 8031 is a ROM-less 8051
※ Add external ROM to it
※ You lose two ports, and leave only 2 ports for I/O
operations
500
501
year
⌘ Intel introduced 8051,developed in the
1981.
⌘ The 8051 is an 8-bit controller.
※ D0-D7
※
A0-A15
DATA LINES
ADDRESS LINES
502
Interrupt
Control
4K
RO
M
256 B
RAM
8bit
CP
U
OS
C
Bus
Control
4 I/O Ports
Serial
Port
Timer 1
Timer 0
TXD
RXD
P0 P1 P2 P3
503
General Block Diagram of
8051
External Interrupts
Counter
Inputs
⌘ 8 bit CPU
⌘ On-chip clock oscillator
⌘ 4K bytes of on-chip Program Memory-ROM
⌘ 128 bytes of on-chip Data RAM
⌘ 64KB Program Memory address space
⌘ 64KB Data Memory address space
⌘ 32 bidirectional I/0 lines (Port
0,1,2,3) Port 0 { P0.0-P0.7 } – 8
pins
Port 1 { P1.0-P1.7 } – 8 pins
Port 2 { P2.0-P2.7 } – 8 pins
Port 3 { P3.0-P3.7 } – 8 pins
504
⌘ Two 16-bit timer/counters(Timer 1,Timer 0)
⌘ One serial port
UART(Universal Asynchronous Receiver Transmitter)
⌘ 6-source interrupt structure
1. External interrupt INT0
2. Timer interrupt T0
3. External interrupt INT1
4. Timer interrupt T1
5. Serial communication interrupt
6. Timer Interrupt T2
※ 4 Register Banks (Bank 0, Bank 1, Bank 2, Bank
3) each bank has R0-R7 registers
505
Pin
Description
of the 8051
or
IO
506
507
EA/VPP
• EA, “external access’’
• EA = 0, 8051 microcontroller
access from external program memory
(ROM) only.
• EA = 1, then it access internal and external
program memories (ROMS).
508
I/O Port Pins
• The four 8-bit I/O ports
Port 0 { P0.0-P0.7 } – 8 pins
Port 1 { P1.0-P1.7 } – 8 pins
Port 2 { P2.0-P2.7 } – 8 pins
Port 3 { P3.0-P3.7 } – 8 pins
509
Port 3
• Port 3 can be used as input or output.
• Port 3 has the additional function of
providing some extremely important
signals
510
Pin Description Summary
PIN TYPE NAME AND FUNCTION
Vss I Ground: 0 V reference.
Vcc I Power Supply + 5V.
P0.0 - P0.7
I/O Port 0: Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data
memory.
P1.0 - P1.7
I/O Port 1: Port 1 is an 8-bit bi-directional simple I/O port.
P2.0 - P2.7
I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the
high order address byte
P3.0 - P3.7
I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also
serves special features as explained.
511
Pin Description Summary
PIN TYPE NAME AND FUNCTION
RST I Reset: resets the device.
ALE O Address Latch Enable:
When ALE=0, it provides data D0-D7
When ALE=1, it has address A0-A7
PSEN* O Program Store Enable:
For External Code Memory, PSEN = 0
For External Data Memory, PSEN = 1
EA*/VPP I External Access Enable/Programming Supply Voltage:
EA = 0, 8051 microcontroller
access from external program memory
(ROM) only.
EA = 1, then it access internal and
external program memories (ROMS).
512
Architecture
of 8051
microcontroll
er
513
514
515
Program Counter(PC) : The program
counter always points to the address of
the next instruction to be executed.
Stack Pointer Register (SP) :It is an 8-bit
register which stores the address of the
stack top.
ALU: perform arithmetic & logical
operations Flags : Carry(C),Auxiliary
Carry(AC),
Overflow(O) & Parity(P)
516
⌘ Timing & Control: Timing and control
unit synchronises all microcontroller
operations with clock & generates control
signals.
⌘ DPTR: (Data Pointer) - 16 bit
✡ DPH-Data Pointer High – 8 bit
✡ DPL-Data Pointer Low – 8 bit
DPTR Register is usually used for storing data and
intermediate results.
517
8051
Program Memory,
Data Memory
structure 518
8051 Memory Structure
External
EXT INT
128
SFR
External
Data Memory
64K 64K
EA = 0 EA = 1
Program Memory
4K
60K
519
Special
Function
Registers
[SFR] 520
521
• A Register (Accumulator)
• B Register
• Program Status Word (PSW) Register
• Data Pointer Register (DPTR)
– DPH (Data Pointer High) , DPL(Data Pointer Low)
•
•
•
•
Stack Pointer (SP) Register
P0, P1, P2, P3 - Input/output port Registers
Timer T0 - TH0 & TL0
Timer T1 – TH1 & TL1
• Timer Control (TCON) Register
• Serial Port Control (SCON) Register
• Serial Buffer Control (SBUF) Register
• IP Register (Interrupt Priority)
• IE Register (Interrupt Enable)
8051 Register Bank
Structure 4
MEMORY BANKS
Bank
3
Bank
2
Bank
1
Bank
0
R0 R1 R2 R3 R4 R5 R6 R7
R0 R1 R2 R3 R4 R5 R6 R7
R0 R1 R2 R3 R4 R5 R6 R7
R0 R1 R2 R3 R4 R5 R6 R7
522
Program Status Word
[PSW]
C AC F0 RS1 RS0 OV F1
P
Register Bank Select
Carry
Auxiliary Carry
User Flag 0
Parity
User Flag 1
Overflow
1. Bank 0
2. Bank 1
10 Bank 2
11 Bank 3
523
Data Pointer Register
It con
(s
Dist
Ps o
Tf
Rtw
)o
separate
registers:
DPH (Data Pointer High) &
DPL (Data Pointer Low).
524
Stack Pointer (SP)
Register
8 bit
P0, P1, P2, P3 – Input / Output Registers
8 bit
8 bit
8 bit
8 bit
525
526
INSTRUCTION
SET OF
8051
8051 Instruction Set
527
• The instructions are grouped into 5 groups
– Arithmetic
– Logic
– Data Transfer
– Boolean
– Branching
1. Arithmetic Instructions
528
• ADD A, source
A ← A + <operand>.
• ADDC
• SUBB
A, source
A ← A + <operand> + CY.
A, source
A ← A - <operand> -
CY{borrow}.
• INC
– Increment the operand by one. Ex: INC
DPTR
• DEC
– Decrement the operand by one. Ex: DEC B
• MUL AB
529
• DIV AB
Multiplication
A*B
Result
8 byte * 8 byte A=low byte,
B=high byte
Division
A/B
Quotient Remainder
8 byte /8 byte
A B
Multiplication of Numbers
MUL AB ; A × B, place 16-bit result in B and A
A=07 , B=02
MUL AB ;07 * 02 = 000E where B = 00 and A = 0E
Division of Numbers
DIV AB ; A / B , 8-bit Quotient result in
A & 8-bit Remainder
A=07 , B=02
DIV AB
530
result in B
;07 / 02 = Quotient 03(A) Remainder01 (B)
2. Logical
instructions
531
• ANL D,S
-Performs logical AND of destination & source
-Eg: ANL A,#0FH ANL A,R5
• ORL D,S
-Performs logical OR of destination & source
-Eg: ORL A,#28H ORL A,@R0
•XRL D,S
-Performs logical XOR of destination & source
-Eg: XRL A,#28H XRL A,@R0
532
• CPL A
-Compliment accumulator
-gives 1’s compliment of accumulator data
• RL A
-Rotate data of accumulator towards left without carry
• RLC A
- Rotate data of accumulator towards left with carry
• RR A
-Rotate data of accumulator towards right without carry
• RRC A
-Rotate data of accumulator towards right with carry
533
3. Data
Transfer
Instructions
534
MOV Instruction
535
• MOV destination, source
;
copy source to destination.
• MOV ;load value 55H into reg. A
A,#55H MOV ;copy contents of A into R0
R0,A ;(now A=R0=55H)
MOV ;copy contents of A into R1
R1,A ;(now A=R0=R1=55H)
MOV
R2,A
;copy contents of A into R2
;(now A=R0=R1=R2=55H)
MOV R3,#95H ;load value 95H into
R3
MOV ;;c(onpoywcRon3t=e9n5tsHo
)f R3 into A
A,R3 ;now A=R3=95H
• MOVX
– Data transfer between the accumulator and
a byte from external data memory.
536
•MOVX
•MOVX
A,
@DPTR
@DPTR,
A
• PUSH / POP
–Push and Pop a data byte onto the
stack.
•PUSH DPL
•POP 40H
537
• XCH
– Exchange accumulator and a byte
variable
538
•XCH
•XCH
•XCH
A, Rn
A, direct
A, @Ri
4.Boolean variable
instructions
539
CLR
:• The operation clears the specified bit indicated in
the instruction
540
• Ex: CLR C clear the carry
SETB:
• The operation sets the specified bit to 1.
CPL:
• The operation complements the specified bit
indicated in the instruction
• ANL C,<Source-bit>
-Performs AND bit addressed with the carry bit.
-Eg: ANL C,P2.7 AND carry flag with bit 7 of
P2
• ORL C,<Source-bit>
-Performs OR bit addressed with the carry bit.
-Eg: ORL C,P2.1 OR carry flag with bit 1 of
P2
541
• XORL
C,<Source-bit>
-Performs XOR bit addressed with the carry bit.
- Eg: XOL C,P2.1 OR carry flag with bit 1 of
P2
•MOV P2.3,C
•MOV C,P3.3
•MOV P2.0,C
542
5. Branching
instructions
543
Jump Instructions
544
• LJMP (long jump):
– Original 8051 has only 4KB on-chip ROM
• SJMP (short jump):
– 1-byte relative address: -128 to +127
Call Instructions
545
• LCALL (long call):
– Target address within 64K-byte range
• ACALL (absolute call):
– Target address within 2K-byte range
• 2 forms for the return instruction:
–Return from subroutine – RET
–Return from ISR – RETI
546
547
8051
Addressing
8051 Addressing Modes
549
• The CPU can access data in various ways, which are
called addressing modes
1. Immediate
2. Register
3. Direct
4. Indirect
5. Relative
6. Absolute
7. Long
8. Indexed
1. Immediate Addressing Mode
• The immediate data sign, “#”
• Data is provided as a part of instruction.
550
2. Register Addressing Mode
• In the Register Addressing mode, the instruction involves
transfer of information between registers.
551
3. Direct Addressing Mode
• This mode allows you to specify the operand by giving its
actual memory address
552
4. Indirect Addressing Mode
• A register is used as a pointer to the data.
• Only register R0 and R1 are used for this purpose.
• R2 – R7 cannot be used to hold the address
of an operand located in RAM.
• When R0 and R1 hold the addresses of RAM locations,
they must be preceded by the “@” sign.
MOVX
553
A,@DPTR
5. Relative Addressing
554
• This mode of addressing is used with some type of jump
instructions, like SJMP (short jump) and conditional
jumps like JNZ
Loop : DEC A
JNZ
Loop
;Decrement A
;If A is not zero, Loop
6. Absolute Addressing
555
• In Absolute Addressing mode, the absolute
address, to which the control is transferred, is
specified by a label.
• Two instructions associated with this mode
of addressing are ACALL and
AJMP
instructions.
• These are 2-byte instructions
7. Long Addressing
556
• This mode of addressing is used with the
LCALL and LJMP instructions.
• It is a 3-byte instruction
• It allows use of the full 64K code
space.
8. Indexed Addressing
• The Indexed addressing is useful when there is a
need to retrieve data from a look-up table (LUT).
557
558
8051
Assembly
Language
Programming(ALP
)
After execution: 559
ADDITION OF TWO 8 bit Numbers
ADDRESS LABEL MNEMONICS
9100: MOVA,#05
MOVB,#03
ADD A,B
MOVDPTR,#9200
MOVX @DPTR,A
HERE SJMP HERE
After execution: 560
SUBTRACTION OF TWO 8 bit
NumADbDRe
ErSSs
LABEL MNEMONICS
9100: CLR C
MOVA,#05
MOVB,#03
SUBB A,B
MOVDPTR,#9200
MOVX @DPTR,A
HERE SJMP HERE
MULTIPLICATION OF
TWO
bit Numbers
8
Address Label Mnemonics
9000 START MOV A,#05
MOV B,#03
MUL AB
MOV DPTR,#9200
MOVX @ DPTR,A
INC DPTR
MOV A,B
MOVX @DPTR,A
HERE SJMP HERE
Address Label Mnemonics
9000 START MOV A,#05
MOV B,#03
DIV AB
MOV DPTR,#9200
MOVX @ DPTR,A
INC DPTR
MOV A,B
MOVX @DPTR,A
HERE SJMP HERE
DIVISION OF TWO 8 bit
Numbers
After execution: A=0F , After execution: A=01 ,
MOV 40H, #02H store 1st number in location
40H
store 1 st number address 40H in
R0 store the count {N=05} in R5
store the count {N=05} in B
Clear Acc
LOOP:
Save the quotient in location 55H
HERE
MOV 41H, #04H
MOV 42H, #06H
MOV 43H, #08H
MOV 44H, #01H
MOV R0, #40H
MOV R5, #05H
MOV B,R5
CLR A
ADD A,@R0
INC R0
DJNZ R5,LOOP
DIV AB
MOV 55H,A
SJMP HERE
Average of N (N=5) 8 bit
Number
s
Answer:
SUM = 15 H
(quotient)
02+04+06+08+01 = 21(decimal) = 15 (Hexa)
Average = 21(decimal) / 5 = 04 (remainder) , 01

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1st unit - microcontroller architechture and pin diagram

  • 2. What is Microcontroller? Micro Controller 491 Very Small A mechanism that controls the operation of a machine
  • 3. ⌘ CPU for Computers ⌘ No RAM, ROM, I/O on CPU chip itself ⌘ Example: Intel's x86, Motorola’s 680x0 492
  • 4. ⌘ A smaller computer ⌘ On-chip RAM, ROM, I/O ⌘poErtxsa..m.ple: Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 493
  • 5. 494
  • 6. Microprocessor ⌘ CPU is stand-alone, RAM, ROM, I/O, timer are separate ⌘ Designer can decide on the amount of ROM, RAM and I/O ports. ⌘ Expansive ⌘ General-purpose Microcontroller ⌘ CPU, RAM, ROM, I/O and timer are all on a single chip ⌘ Fix amount of on-chip ROM, RAM, I/O ports ⌘ For applications in which cost, power and space are critical ⌘ Not Expansive ⌘ Single-purpose 495
  • 7. ⌘ Home ※ Appliances, intercom, telephones, security systems, garage openers, answering machines, fax machines, home computers, cable TV tuner, VCR, camcorder, remote controls, video door TVs, games, cellular phones, musical instruments, sewing machines, lighting equipment control, paging, camera, pinball machines, toys, exercise etc. microwave, Office ※ Telephones, computers, security systems, fax machines, copier, laser printer, color printer, paging etc. ⌘ Auto ※ Trip computer, engine control, air bag, ABS, instrumentation, security system, transmission control, entertainment, climate control, cellular phone, keyless entry 496
  • 8. 497
  • 9. UNIT 4 Syllabus • Architecture of 8051 • Special Function Registers(SFRs) • I/O Pins Ports and Circuits {Pin Diagram} • Instruction set • Addressing modes • Assembly language programming • PIC and ARM 499
  • 10. ⌘ The 8051 is a subset of the 8052 ⌘ The 8031 is a ROM-less 8051 ※ Add external ROM to it ※ You lose two ports, and leave only 2 ports for I/O operations 500
  • 11. 501
  • 12. year ⌘ Intel introduced 8051,developed in the 1981. ⌘ The 8051 is an 8-bit controller. ※ D0-D7 ※ A0-A15 DATA LINES ADDRESS LINES 502
  • 13. Interrupt Control 4K RO M 256 B RAM 8bit CP U OS C Bus Control 4 I/O Ports Serial Port Timer 1 Timer 0 TXD RXD P0 P1 P2 P3 503 General Block Diagram of 8051 External Interrupts Counter Inputs
  • 14. ⌘ 8 bit CPU ⌘ On-chip clock oscillator ⌘ 4K bytes of on-chip Program Memory-ROM ⌘ 128 bytes of on-chip Data RAM ⌘ 64KB Program Memory address space ⌘ 64KB Data Memory address space ⌘ 32 bidirectional I/0 lines (Port 0,1,2,3) Port 0 { P0.0-P0.7 } – 8 pins Port 1 { P1.0-P1.7 } – 8 pins Port 2 { P2.0-P2.7 } – 8 pins Port 3 { P3.0-P3.7 } – 8 pins 504
  • 15. ⌘ Two 16-bit timer/counters(Timer 1,Timer 0) ⌘ One serial port UART(Universal Asynchronous Receiver Transmitter) ⌘ 6-source interrupt structure 1. External interrupt INT0 2. Timer interrupt T0 3. External interrupt INT1 4. Timer interrupt T1 5. Serial communication interrupt 6. Timer Interrupt T2 ※ 4 Register Banks (Bank 0, Bank 1, Bank 2, Bank 3) each bank has R0-R7 registers 505
  • 17. 507
  • 18. EA/VPP • EA, “external access’’ • EA = 0, 8051 microcontroller access from external program memory (ROM) only. • EA = 1, then it access internal and external program memories (ROMS). 508
  • 19. I/O Port Pins • The four 8-bit I/O ports Port 0 { P0.0-P0.7 } – 8 pins Port 1 { P1.0-P1.7 } – 8 pins Port 2 { P2.0-P2.7 } – 8 pins Port 3 { P3.0-P3.7 } – 8 pins 509
  • 20. Port 3 • Port 3 can be used as input or output. • Port 3 has the additional function of providing some extremely important signals 510
  • 21. Pin Description Summary PIN TYPE NAME AND FUNCTION Vss I Ground: 0 V reference. Vcc I Power Supply + 5V. P0.0 - P0.7 I/O Port 0: Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. P1.0 - P1.7 I/O Port 1: Port 1 is an 8-bit bi-directional simple I/O port. P2.0 - P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the high order address byte P3.0 - P3.7 I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also serves special features as explained. 511
  • 22. Pin Description Summary PIN TYPE NAME AND FUNCTION RST I Reset: resets the device. ALE O Address Latch Enable: When ALE=0, it provides data D0-D7 When ALE=1, it has address A0-A7 PSEN* O Program Store Enable: For External Code Memory, PSEN = 0 For External Data Memory, PSEN = 1 EA*/VPP I External Access Enable/Programming Supply Voltage: EA = 0, 8051 microcontroller access from external program memory (ROM) only. EA = 1, then it access internal and external program memories (ROMS). 512
  • 24. 514
  • 25. 515
  • 26. Program Counter(PC) : The program counter always points to the address of the next instruction to be executed. Stack Pointer Register (SP) :It is an 8-bit register which stores the address of the stack top. ALU: perform arithmetic & logical operations Flags : Carry(C),Auxiliary Carry(AC), Overflow(O) & Parity(P) 516
  • 27. ⌘ Timing & Control: Timing and control unit synchronises all microcontroller operations with clock & generates control signals. ⌘ DPTR: (Data Pointer) - 16 bit ✡ DPH-Data Pointer High – 8 bit ✡ DPL-Data Pointer Low – 8 bit DPTR Register is usually used for storing data and intermediate results. 517
  • 29. 8051 Memory Structure External EXT INT 128 SFR External Data Memory 64K 64K EA = 0 EA = 1 Program Memory 4K 60K 519
  • 31. 521 • A Register (Accumulator) • B Register • Program Status Word (PSW) Register • Data Pointer Register (DPTR) – DPH (Data Pointer High) , DPL(Data Pointer Low) • • • • Stack Pointer (SP) Register P0, P1, P2, P3 - Input/output port Registers Timer T0 - TH0 & TL0 Timer T1 – TH1 & TL1 • Timer Control (TCON) Register • Serial Port Control (SCON) Register • Serial Buffer Control (SBUF) Register • IP Register (Interrupt Priority) • IE Register (Interrupt Enable)
  • 32. 8051 Register Bank Structure 4 MEMORY BANKS Bank 3 Bank 2 Bank 1 Bank 0 R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R4 R5 R6 R7 522
  • 33. Program Status Word [PSW] C AC F0 RS1 RS0 OV F1 P Register Bank Select Carry Auxiliary Carry User Flag 0 Parity User Flag 1 Overflow 1. Bank 0 2. Bank 1 10 Bank 2 11 Bank 3 523
  • 34. Data Pointer Register It con (s Dist Ps o Tf Rtw )o separate registers: DPH (Data Pointer High) & DPL (Data Pointer Low). 524
  • 35. Stack Pointer (SP) Register 8 bit P0, P1, P2, P3 – Input / Output Registers 8 bit 8 bit 8 bit 8 bit 525
  • 37. 8051 Instruction Set 527 • The instructions are grouped into 5 groups – Arithmetic – Logic – Data Transfer – Boolean – Branching
  • 38. 1. Arithmetic Instructions 528 • ADD A, source A ← A + <operand>. • ADDC • SUBB A, source A ← A + <operand> + CY. A, source A ← A - <operand> - CY{borrow}.
  • 39. • INC – Increment the operand by one. Ex: INC DPTR • DEC – Decrement the operand by one. Ex: DEC B • MUL AB 529 • DIV AB Multiplication A*B Result 8 byte * 8 byte A=low byte, B=high byte Division A/B Quotient Remainder 8 byte /8 byte A B
  • 40. Multiplication of Numbers MUL AB ; A × B, place 16-bit result in B and A A=07 , B=02 MUL AB ;07 * 02 = 000E where B = 00 and A = 0E Division of Numbers DIV AB ; A / B , 8-bit Quotient result in A & 8-bit Remainder A=07 , B=02 DIV AB 530 result in B ;07 / 02 = Quotient 03(A) Remainder01 (B)
  • 42. • ANL D,S -Performs logical AND of destination & source -Eg: ANL A,#0FH ANL A,R5 • ORL D,S -Performs logical OR of destination & source -Eg: ORL A,#28H ORL A,@R0 •XRL D,S -Performs logical XOR of destination & source -Eg: XRL A,#28H XRL A,@R0 532
  • 43. • CPL A -Compliment accumulator -gives 1’s compliment of accumulator data • RL A -Rotate data of accumulator towards left without carry • RLC A - Rotate data of accumulator towards left with carry • RR A -Rotate data of accumulator towards right without carry • RRC A -Rotate data of accumulator towards right with carry 533
  • 45. MOV Instruction 535 • MOV destination, source ; copy source to destination. • MOV ;load value 55H into reg. A A,#55H MOV ;copy contents of A into R0 R0,A ;(now A=R0=55H) MOV ;copy contents of A into R1 R1,A ;(now A=R0=R1=55H) MOV R2,A ;copy contents of A into R2 ;(now A=R0=R1=R2=55H) MOV R3,#95H ;load value 95H into R3 MOV ;;c(onpoywcRon3t=e9n5tsHo )f R3 into A A,R3 ;now A=R3=95H
  • 46. • MOVX – Data transfer between the accumulator and a byte from external data memory. 536 •MOVX •MOVX A, @DPTR @DPTR, A
  • 47. • PUSH / POP –Push and Pop a data byte onto the stack. •PUSH DPL •POP 40H 537
  • 48. • XCH – Exchange accumulator and a byte variable 538 •XCH •XCH •XCH A, Rn A, direct A, @Ri
  • 50. CLR :• The operation clears the specified bit indicated in the instruction 540 • Ex: CLR C clear the carry SETB: • The operation sets the specified bit to 1. CPL: • The operation complements the specified bit indicated in the instruction
  • 51. • ANL C,<Source-bit> -Performs AND bit addressed with the carry bit. -Eg: ANL C,P2.7 AND carry flag with bit 7 of P2 • ORL C,<Source-bit> -Performs OR bit addressed with the carry bit. -Eg: ORL C,P2.1 OR carry flag with bit 1 of P2 541
  • 52. • XORL C,<Source-bit> -Performs XOR bit addressed with the carry bit. - Eg: XOL C,P2.1 OR carry flag with bit 1 of P2 •MOV P2.3,C •MOV C,P3.3 •MOV P2.0,C 542
  • 54. Jump Instructions 544 • LJMP (long jump): – Original 8051 has only 4KB on-chip ROM • SJMP (short jump): – 1-byte relative address: -128 to +127
  • 55. Call Instructions 545 • LCALL (long call): – Target address within 64K-byte range • ACALL (absolute call): – Target address within 2K-byte range
  • 56. • 2 forms for the return instruction: –Return from subroutine – RET –Return from ISR – RETI 546
  • 57. 547
  • 59. 8051 Addressing Modes 549 • The CPU can access data in various ways, which are called addressing modes 1. Immediate 2. Register 3. Direct 4. Indirect 5. Relative 6. Absolute 7. Long 8. Indexed
  • 60. 1. Immediate Addressing Mode • The immediate data sign, “#” • Data is provided as a part of instruction. 550
  • 61. 2. Register Addressing Mode • In the Register Addressing mode, the instruction involves transfer of information between registers. 551
  • 62. 3. Direct Addressing Mode • This mode allows you to specify the operand by giving its actual memory address 552
  • 63. 4. Indirect Addressing Mode • A register is used as a pointer to the data. • Only register R0 and R1 are used for this purpose. • R2 – R7 cannot be used to hold the address of an operand located in RAM. • When R0 and R1 hold the addresses of RAM locations, they must be preceded by the “@” sign. MOVX 553 A,@DPTR
  • 64. 5. Relative Addressing 554 • This mode of addressing is used with some type of jump instructions, like SJMP (short jump) and conditional jumps like JNZ Loop : DEC A JNZ Loop ;Decrement A ;If A is not zero, Loop
  • 65. 6. Absolute Addressing 555 • In Absolute Addressing mode, the absolute address, to which the control is transferred, is specified by a label. • Two instructions associated with this mode of addressing are ACALL and AJMP instructions. • These are 2-byte instructions
  • 66. 7. Long Addressing 556 • This mode of addressing is used with the LCALL and LJMP instructions. • It is a 3-byte instruction • It allows use of the full 64K code space.
  • 67. 8. Indexed Addressing • The Indexed addressing is useful when there is a need to retrieve data from a look-up table (LUT). 557
  • 69. After execution: 559 ADDITION OF TWO 8 bit Numbers ADDRESS LABEL MNEMONICS 9100: MOVA,#05 MOVB,#03 ADD A,B MOVDPTR,#9200 MOVX @DPTR,A HERE SJMP HERE
  • 70. After execution: 560 SUBTRACTION OF TWO 8 bit NumADbDRe ErSSs LABEL MNEMONICS 9100: CLR C MOVA,#05 MOVB,#03 SUBB A,B MOVDPTR,#9200 MOVX @DPTR,A HERE SJMP HERE
  • 71. MULTIPLICATION OF TWO bit Numbers 8 Address Label Mnemonics 9000 START MOV A,#05 MOV B,#03 MUL AB MOV DPTR,#9200 MOVX @ DPTR,A INC DPTR MOV A,B MOVX @DPTR,A HERE SJMP HERE Address Label Mnemonics 9000 START MOV A,#05 MOV B,#03 DIV AB MOV DPTR,#9200 MOVX @ DPTR,A INC DPTR MOV A,B MOVX @DPTR,A HERE SJMP HERE DIVISION OF TWO 8 bit Numbers After execution: A=0F , After execution: A=01 ,
  • 72. MOV 40H, #02H store 1st number in location 40H store 1 st number address 40H in R0 store the count {N=05} in R5 store the count {N=05} in B Clear Acc LOOP: Save the quotient in location 55H HERE MOV 41H, #04H MOV 42H, #06H MOV 43H, #08H MOV 44H, #01H MOV R0, #40H MOV R5, #05H MOV B,R5 CLR A ADD A,@R0 INC R0 DJNZ R5,LOOP DIV AB MOV 55H,A SJMP HERE Average of N (N=5) 8 bit Number s Answer: SUM = 15 H (quotient) 02+04+06+08+01 = 21(decimal) = 15 (Hexa) Average = 21(decimal) / 5 = 04 (remainder) , 01