2. 8085-Microprocessor.pptx

1
Introduction to 8085
Microprocessor

Introduction to 8085 MP
 8-bit general purpose µp
 Has 40 pins
 Requires +5 v power supply
 8-bit data bus
 16-bit address bus, which can address up to 64KB
 A 16-bit program counter
 A 16-bit stack pointer
 Six 8-bit registers arranged in pairs: BC, DE, HL
 Can operate with 3 MHz clock

Data flow between memory and MPU
 First of all the 16-bit address is placed on the address bus from the
program counter.
 Let say the address is 2005H where the data is placed.
 The higher order address i.e. 20H is placed on the address bus A8-
A15 while the lower order address i.e. 05H is placed on the
multiplexed address and data bus ADO-AD7.
 The lower order address continues to remain on this address bus
so long as ALE (Address Latch Enable) remains positive. Once ALE
goes low it carries data.
 The control unit sends the signal to indicate what type of
operation is to be performed. Since the data is to be read from the
memory therefore it sends to enable the memory chip

 The byte from the memory location is then placed on the data bus
i.e. 4F saved in location 2005H is placed on the data bus and sent
to the instruction decoder.
 The instruction is decoded and accordingly the task is performed
by the ALU i.e. Arithmetic and logic unit.

8085 Programming Model
7
Accumulator A (8)
B (8)
D (8) E (8)
C (8)
H (8) L (8)
Stack Pointer (SP) (16)
Program Counter (PC) (16)
Address Bus
Data Bus
8
Bidirectional
16
Unidirectional
Flag Register
General
Purpose
Registers

General Purpose Registers
 6 general purpose registers to store 8-bit data B, C, D, E, H & L.
 Can be combined as fixed register pairs – BC, DE, HL to perform
16 bit operations.
 Used to store or copy data using data copy instructions.
8
B (8)
D (8) E (8)
C (8)
H (8) L (8)

9
Accumulator A (8)
B (8)
D (8) E (8)
C (8)
H (8) L (8)
Address Bus
Data Bus
8
Bidirectional
16
Unidirectional
Flag Register

Accumulator
 8-bit register, identified as A
 Part of ALU
 Used to store 8-bit data to perform arithmetic & logical
operations.
 Result of operation is stored in
10
Accumulator A (8)

11
Accumulator A (8)
B (8)
D (8) E (8)
C (8)
H (8) L (8)
Address Bus
Data Bus
8
Bidirectional
16
Unidirectional
Flag Register

Flag Register
S Z  AC  P  CY
12
D7 D6 D5 D4 D3 D2 D1 D0
S -Sign Flag
Set (1) if 7th bit of result is 1;
otherwise reset (0)
Z -Zero Flag
Set (1) when result is zero;
otherwise reset(0)
AC -Auxiliary Carry Flag
Set (1) when carry bit is
generated by 3rd bit &
passed to bit 4th bit.
P -Parity Flag
Set (1) if result has even no. of 1’s &
Reset(0) if result has odd no. of 1’s
CY -Carry Flag
Set (1) if arithmetic
operation results in
carry;
otherwise reset(0)
1 1 1
0 0 1 0 1 0 1 0
+ 0 1 1 0 1 0 0 1
1 0 0 1 0 0 1 1
AC = 1
1 0 1 0 1 0 1 0
S = 1
1 0 1 0
- 1 0 1 0
0 0 0 0
Z = 1
1 0 0 1 0 0 1 1
P = 1
:Undefined
1 1 1
1 0 1 0 1 0 1 0
+ 0 1 1 0 1 0 0 1
1 0 0 0 1 0 0 1 1
CY = 1

Flag Register
 5 Flag Register for set/reset operations.
 Helpful in decision making.
 Conditions are tested through software instructions.
Example:
JC (Jump On Carry) is implemented to change the sequence of
program when CY(Carry Flag) is set(1).
13
S Z  AC  P  CY
D7 D6 D5 D4 D3 D2 D1 D0

14
Accumulator A (8)
B (8)
D (8) E (8)
C (8)
H (8) L (8)
Address Bus
Data Bus
8
Bidirectional
16
Unidirectional
Flag Register

Stack Pointer
Stack Pointer(SP)
 Used as memory pointer.
 Points to the memory location in
R/W memory called Stack.
 Beginning of stack is defined by
loading a 16-bit address in the
stack pointer.
15

16
Accumulator A (8)
B (8)
D (8) E (8)
C (8)
H (8) L (8)
Address Bus
Data Bus
8
Bidirectional
16
Unidirectional
Flag Register

Stack Pointer & Program Counter
Program Counter(PC)
 Sequence the execution of an instructions.
17
Address Memory
0003H Instruction 4
0002H Instruction 3
0001H Instruction 2
0000H Instruction 1
PC
IR
CPU
0000H Instruction 1
0001H Instruction 2
0002H

20
8085
pin
diagram • 8-bit general purpose
microprocessor.
• Capable of addressing 64K
of memory.
• It has 40 pins.
• Requires +5V single power
supply.

8085 pin diagram
Signals are classified into 6 groups:
1. Address bus
2. Multiplexed address/data bus
3. Control & status signals
4. Power supply & frequency signals
5. Externally initiated signals
6. Serial I/O ports
21

8085 pin diagram: Address Bus
 16 signal lines are used as address
bus.
 However these lines are split into
two segments: A15 - A8 and AD7 - AD0
 A15 - A8 are unidirectional and used
to carry high-order address of 16-bit
address.
 AD7 - AD0 are used for dual purpose.
22

8085 pin diagram: Multiplexed Address/Data Bus
 Signal lines AD7-AD0 are
bidirectional and serve dual
purpose.
 They are used as low-order address
bus as well as data bus.
 The low-order address bus can be
separated from these signals by
using a latch (ALE).
23

8085 pin diagram: Control & Status Signals
To identify nature of operation
 Two Control Signals
1. RD(Read)
2. WR(Write)
 Three Status Signals
1. S1
2. S0
3. IO/M
 To indicate beginning of operation
1. ALE(Address Latch Enable)
ALE  1, then Address bus
ALE  0, then Data bus
24

ALE: Pin 30
 This is positive going pulse
generated every time the 8085
begins an operation (machine
cycle).
 It indicates that the bits on AD7-AD0
are address bits.
 This signal is used primarily to latch
the low-address from multiplexed
bus & generate a separate set of
address lines A7-A0.
25

RD(Read): Pin 32
 This is a read control signal (active
low)
 This signal indicates that the
selected I/O or Memory device is
to be read & data is available on
data bus.
26

WR (Write): Pin 31
 This is a write control signal (active
low)
 This signal indicates that the
selected I/O or Memory device is
to be write & data is available on
data bus.
27

IO/M: Pin 34
 This is a status signal used to
differentiate I/O and memory
operation.
 When signal is
high  I/O operation
low  Memory operation
 This signal is combined with RD and
WR to generate I/O & memory
control signals.
28

S1 (Pin 33) & S0 (Pin 29)
 These status signals can identify
various operations.
29
S1 S0 Mode
0 0 HLT
0 1 WRITE
1 1 OPCODE FETCH
1 0 READ

8085 pin diagram
30
I0/M RD WR Operation
0 0 1 MEMR
0 1 0 MEMW
0 1 1 Opcode
Fetch
1 0 1 IOR
1 1 0 IOW
1 1 1 NOP
0 0 0 HLT
1 0 0 HLT

8085 Pin Diagram: Power Supply & Frequency Signal
 Vcc  Pin 40, +5V Supply.
 Vss  Pin 20, Ground Reference
31

 X1, X2  Pin 1 & 2, Crystal
Oscillator is connected at these
two pins.
 The frequency is internally divided
by two;
therefore, to operate a system at
3MHz, the crystal oscillator should
have a frequency of 6MHz.
32

 CLK (OUT)  Clock output
 Pin 37: This signal is used as system
clock for other I/O devices for
synchronization with Microprocessor.
33

8085 Pin Diagram: Externally Initiated Signals
 INTR(Input)  Interrupt Request
It is used for general purpose
interrupt.
 INTA(Output)  Interrupt
Acknowledge.
34

 RST7.5, RST6.5, RST5.5 (Input) 
Restart Interrupts.
 These are vector interrupts that
transfer the program control to
specific memory locations.
 RST7.5, RST6.5, RST5.5 have higher
priorities than INTR interrupt.
 Among these 3 interrupts, the
priority order (higher to lower) is
RST7.5, RST6.5, RST5.5
respectively.
35

 TRAP(Input)  This is a non
maskable interrupt & has the
highest priority.
36

 HOLD(Input)  This signal indicates
that a peripheral such as DMA
Controller is requesting the use of
address & data buses.
 HLDA(Output)  Hold Acknowledge
This signal acknowledges the HOLD
request.
37

 READY(Input)  This signal is used
to delay the microprocessor read or
write cycles until low-responding
peripheral is ready to send or accept
data.
 When the signal goes low, the
microprocessor waits for an integral
no. of clock cycles until READY signal
goes high.
38

 RESET IN (Input)  When the
signal on this pin goes low, the
Program Counter is set to zero,
the buses are tri-stated &
microprocessor is reset.
 RESET OUT (Output)  This
signal indicates that
microprocessor is being reset. The
signal is also used to reset other
devices.
39

8085 Pin Diagram: Serial I/O Ports
Two pins for serial transmission
1. SID (Serial Input Data)
2. SOD (Serial Output Data)
 In serial transmission, data bits
are sent over a single line, one bit
at a time.
40

42
8085 Architecture/Block Diagram
42

INTA
44
B (8)
Reg.
C (8)
Reg.
D (8)
Reg.
E (8)
Reg.
H (8)
Reg.
L (8)
Reg.
Accumulator (8)
W (8)
Temp. Reg.
Z (8)
Temp. Reg.
Stack Pointer (16)
Program Counter (16)
Increment/Decrement
Address Latch (16)
Register
Select
Multiplexer
Arithmetic
Logic Unit
(ALU) (8)
Flag (5)
Flip-Flops
Temp. Reg. (8)
Instruction
Reg. (8)
Instruction
Decoder
and
Machine
Cycle
Encoding
Address Buffer
(8)
Data/Address Buffer
(8)
A15 - A8
Address
Bus
AD7 – AD0
Address/Data
Bus
Interrupt Control
INTR RST5.5
TRAP
RST7.5
RST6.5
Serial I/O Control
SID SOD
Timing and Control
X1
X2
CLK
GEN
CLK
OUT
READY
WR
RD
ALE HOLD
HLDA
RESET IN
RESET OUT
S0 S1
Control Status DMA
Reset
Power
Supply
+5 V
8-Bit Internal Data Bus
GND
IO/M

INTA
45
B (8)
Reg.
C (8)
Reg.
D (8)
Reg.
E (8)
Reg.
H (8)
Reg.
L (8)
Reg.
Accumulator (8)
W (8)
Temp. Reg.
Z (8)
Temp. Reg.
Stack Pointer (16)
Increment/Decrement
Address Latch (16)
Register
Select
Multiplexer
Arithmetic
Logic Unit
(ALU) (8)
Flag (5)
Flip-Flops
Temp. Reg. (8)
Instruction
Reg. (8)
Instruction
Decoder
and
Machine
Cycle
Encoding
Address Buffer
(8)
Data/Address Buffer
(8)
A15 - A8
Address
Bus
AD7 – AD0
Address/Data
Bus
Interrupt Control
INTR RST5.5
TRAP
RST7.5
RST6.5
Serial I/O Control
SID SOD
Timing and Control
X1 CLK
GEN
CLK
OUT
READY
WR
RD
ALE HOLD
HLDA
RESET IN
RESET OUT
S0 S1
Control Status DMA
Reset
• Used to store 8-bit data to perform arithmetic & logical operations.
• Result of operation is stored in Accumulator.
Used to hold data (i.e. temporary
data) during ALU operation.
S Z AC P CY
When Instruction is fetched from
memory, it is loaded in the
Instruction Registor (IR).
Instruction decoder decodes
the information present in the
Instruction register.
• Performs Computing Functions.
• Accumulator, Temporary Register
and Flag Registers are part of ALU.

INTA
46
B (8)
Reg.
C (8)
Reg.
D (8)
Reg.
E (8)
Reg.
H (8)
Reg.
L (8)
Reg.
Accumulator (8)
W (8)
Temp. Reg.
Z (8)
Temp. Reg.
Stack Pointer (16)
Increment/Decrement
Address Latch (16)
Register
Select
Multiplexer
Arithmetic
Logic Unit
(ALU) (8)
Flag (5)
Flip-Flops
Temp. Reg. (8)
Instruction
Reg. (8)
Instruction
Decoder
and
Machine
Cycle
Encoding
Address Buffer
(8)
Data/Address Buffer
(8)
A15 - A8
Address
Bus
AD7 – AD0
Address/Data
Bus
Interrupt Control
INTR RST5.5
TRAP
RST7.5
RST6.5
Serial I/O Control
SID SOD
Timing and Control
X1 CLK
GEN
CLK
OUT
READY
WR
RD
ALE HOLD
HLDA
RESET IN
RESET OUT
S0 S1
Control Status DMA
Reset
• Each register can hold 8-bit data.
• These registers can work in pair to hold 16-
bit data and their pairing combination is
like B-C, D-E & H-L.
• Two additional 8-bit register, which holds
the temporary data during execution of
some instructions.
• They are used internally, so they are not
available to the programmer.
It is a 16-bit register works like stack, which is
always incremented/decremented by 2 during
push & pop operations.
16-bit register used to store the memory
address location of the next instruction to be
executed.
A multiplexer pulls out the right group
of bits, depending on the instruction.
It increments the program counter as
instructions execute, increments and
decrements the stack pointer as needed, and
supports the 16-bit increment and decrement
instructions.
• The content stored in the SP and PC is
loaded into the Address Buffer and
Data/Address Buffer.
• The memory and I/O chips are connected
to these buses that can exchange the
data.

INTA
47
B (8)
Reg.
C (8)
Reg.
D (8)
Reg.
E (8)
Reg.
H (8)
Reg.
L (8)
Reg.
Accumulator (8)
W (8)
Temp. Reg.
Z (8)
Temp. Reg.
Stack Pointer (16)
Increment/Decrement
Address Latch (16)
Register
Select
Multiplexer
Arithmetic
Logic Unit
(ALU) (8)
Flag (5)
Flip-Flops
Temp. Reg. (8)
Instruction
Reg. (8)
Instruction
Decoder
and
Machine
Cycle
Encoding
Address Buffer
(8)
Data/Address Buffer
(8)
A15 - A8
Address
Bus
AD7 – AD0
Address/Data
Bus
Interrupt Control
INTR RST5.5
TRAP
RST7.5
RST6.5
Serial I/O Control
SID SOD
Timing and Control
X1 CLK
GEN
CLK
OUT
READY
WR
RD
ALE HOLD
HLDA
RESET IN
RESET OUT
S0 S1
Control Status DMA
Reset
• Each register can hold 8-bit data.
• These registers can work in pair to hold 16-
bit data and their pairing combination is
like B-C, D-E & H-L.
• Two additional 8-bit register, which holds
the temporary data during execution of
some instructions.
• They are used internally, so they are not
available to the programmer.
It is a 16-bit register works like stack, which is
always incremented/decremented by 2 during
push & pop operations.
16-bit register used to store the memory
address location of the next instruction to be
executed.
A multiplexer pulls out the right group
of bits, depending on the instruction.
It increments the program counter as
instructions execute, increments and
decrements the stack pointer as needed, and
supports the 16-bit increment and decrement
instructions.
• The content stored in the SP and PC is
loaded into the Address Buffer and
Data/Address Buffer.
• The memory and I/O chips are connected
to these buses that can exchange the
data.

X2
INTA
48
B (8)
Reg.
C (8)
Reg.
D (8)
Reg.
E (8)
Reg.
H (8)
Reg.
L (8)
Reg.
Accumulator (8)
W (8)
Temp. Reg.
Z (8)
Temp. Reg.
Stack Pointer (16)
Increment/Decrement
Address Latch (16)
Register
Select
Multiplexer
Arithmetic
Logic Unit
(ALU) (8)
Flag (5)
Flip-Flops
Temp. Reg. (8)
Instruction
Reg. (8)
Instruction
Decoder
and
Machine
Cycle
Encoding
Address Buffer
(8)
Data/Address Buffer
(8)
A15 - A8
Address
Bus
AD7 – AD0
Address/Data
Bus
Interrupt Control
INTR RST5.5
TRAP
RST7.5
RST6.5
Serial I/O Control
SID SOD
Timing and Control
X1 CLK
GEN
CLK
OUT
READY
WR
RD
ALE HOLD
HLDA
RESET IN
RESET OUT
S0 S1
Control Status DMA
Reset
This unit synchronizes all the microprocessor operations with the
clock and generates control signal necessary for communication
between microprocessor & peripheral.
Frequency Control Signals
Perform synchronization
with peripheral device.
Input signal to synchronize microprocessor
with peripheral device.
Read/write either to/from memory or peripherals.
Address Latch Enable control signal
Shows read/write status to/from memory or I/O.
DMA control signal
Signal to RESET microprocessor
and other devices connected to
it.

X2
INTA
49
B (8)
Reg.
C (8)
Reg.
D (8)
Reg.
E (8)
Reg.
H (8)
Reg.
L (8)
Reg.
Accumulator (8)
W (8)
Temp. Reg.
Z (8)
Temp. Reg.
Stack Pointer (16)
Increment/Decrement
Address Latch (16)
Register
Select
Multiplexer
Arithmetic
Logic Unit
(ALU) (8)
Flag (5)
Flip-Flops
Temp. Reg. (8)
Instruction
Reg. (8)
Instruction
Decoder
and
Machine
Cycle
Encoding
Address Buffer
(8)
Data/Address Buffer
(8)
A15 - A8
Address
Bus
AD7 – AD0
Address/Data
Bus
Interrupt Control
INTR RST5.5
TRAP
RST7.5
RST6.5
Serial I/O Control
SID SOD
Timing and Control
X1 CLK
GEN
CLK
OUT
READY
WR
RD
ALE HOLD
HLDA
RESET IN
RESET OUT
S0 S1
Control Status DMA
Reset

X2
INTA
50
B (8)
Reg.
C (8)
Reg.
D (8)
Reg.
E (8)
Reg.
H (8)
Reg.
L (8)
Reg.
Accumulator (8)
W (8)
Temp. Reg.
Z (8)
Temp. Reg.
Stack Pointer (16)
Increment/Decrement
Address Latch (16)
Register
Select
Multiplexer
Arithmetic
Logic Unit
(ALU) (8)
Flag (5)
Flip-Flops
Temp. Reg. (8)
Instruction
Reg. (8)
Instruction
Decoder
and
Machine
Cycle
Encoding
Address Buffer
(8)
Data/Address Buffer
(8)
A15 - A8
Address
Bus
AD7 – AD0
Address/Data
Bus
Interrupt Control
INTR RST5.5
TRAP
RST7.5
RST6.5
Serial I/O Control
SID SOD
Timing and Control
X1 CLK
GEN
CLK
OUT
READY
WR
RD
ALE HOLD
HLDA
RESET IN
RESET OUT
S0 S1
Control Status DMA
Reset
• It controls the interrupts during a process.
• There are 5 interrupt signals in 8085 microprocessor:
TRAP, RST 7.5, RST 6.5, RST 5.5, INTR.
It controls the serial data communication by
using two instructions:
i. SID (Serial input data)
ii. SOD (Serial output data)

INTA
51
B (8)
Reg.
C (8)
Reg.
D (8)
Reg.
E (8)
Reg.
H (8)
Reg.
L (8)
Reg.
Accumulator (8)
W (8)
Temp. Reg.
Z (8)
Temp. Reg.
Stack Pointer (16)
Increment/Decrement
Address Latch (16)
Register
Select
Multiplexer
Arithmetic
Logic Unit
(ALU) (8)
Flag (5)
Flip-Flops
Temp. Reg. (8)
Instruction
Reg. (8)
Instruction
Decoder
and
Machine
Cycle
Encoding
Address Buffer
(8)
Data/Address Buffer
(8)
A15 - A8
Address
Bus
AD7 – AD0
Address/Data
Bus
Interrupt Control
INTR RST5.5
TRAP
RST7.5
RST6.5
Serial I/O Control
SID SOD
Timing and Control
X1
X2
CLK
GEN
CLK
OUT
READY
WR
RD
ALE HOLD
HLDA
RESET IN
RESET OUT
S0 S1
Control Status DMA
Reset
Power
Supply
+5 V
GND
IO/M

Components of 8085 MP
1. Address Bus and Data Bus:
 The 8085 has 16 signal lines that are used as the address bus;
however, these lines are split into two segments A15-A8 and AD7-
AD0. The eight signals A15-A8 are unidirectional and used as high
order bus.
 The signal lines AD7- AD0 are bidirectional, they serve a dual
purpose. They are used as the low order address bus as well as
data bus.

2. Control and Status Signals:
 ALE – It is an Address Latch Enable signal. It goes high during first T
state of a machine cycle and enables the lower 8-bits of the address, if
its value is 1 otherwise data bus is activated.
 IO/M’ – It is a status signal which determines whether the address is
for input-output or memory. When it is high(1) the address on the
address bus is for input-output devices. When it is low(0) the address
on the address bus is for the memory.
 SO, S1 – These are status signals. They distinguish the various types of
operations such as halt, reading, instruction fetching or writing.

 RD’ – It is a signal to control READ operation. When it is low the
selected memory or input-output device is read.
 WR’ – It is a signal to control WRITE operation. When it goes low
the data on the data bus is written into the selected memory or
I/O location.
 READY – It senses whether a peripheral is ready to transfer data or
not. If READY is high(1) the peripheral is ready. If it is low(0) the
microprocessor waits till it goes high. It is useful for interfacing low
speed devices.

3. Power Supply and Clock Frequency:
 Vcc – +5v power supply
 Vss – Ground Reference
 XI, X2 – A crystal is connected at these two pins. The frequency is
internally divided by two, therefore, to operate a system at 3MHZ
the crystal should have frequency of 6MHZ.
 CLK (OUT) – This signal can be used as the system clock for other
devices.

4. Interrupts and Peripheral Initiated Signals:
 The 8085 has five interrupt signals that can be used to interrupt a program
execution.
 (i) INTR
(ii) RST 7.5
(iii) RST 6.5
(iv) RST 5.5
(v) TRAP
 The microprocessor acknowledges Interrupt Request by INTA’ signal. In addition to
Interrupts, there are three externally initiated signals namely RESET, HOLD and
READY. To respond to HOLD request, it has one signal called HLDA.
 INTR – It is an interrupt request signal.
 INTA’ – It is an interrupt acknowledgment sent by the microprocessor after INTR is
received.

5. Reset Signals:
 RESET IN’ – When the signal on this pin is low(0), the program-
counter is set to zero, the buses are tristated and the
microprocessor unit is reset.
 RESET OUT – This signal indicates that the MPU is being reset. The
signal can be used to reset other devices.
6. Serial I/O Ports:
Serial transmission in 8085 is implemented by the two signals,
 SID and SOD – SID is a data line for serial input where as SOD is a
data line for serial output.

7. DMA Signals:
 HOLD – It indicates that another device is requesting the use of
the address and data bus. Having received HOLD request the
microprocessor relinquishes the use of the buses as soon as the
current machine cycle is completed. Internal processing may
continue. After the removal of the HOLD signal the processor
regains the bus.
 HLDA – It is a signal which indicates that the hold request has
been received after the removal of a HOLD request, the HLDA
goes low.

Assignment
 Introduction to 8086 Microprocessor
 Features of 8085 & 8086 Microprocessor
 Difference between 8085 & 8086 Microprocessor

2. 8085-Microprocessor.pptx

More Related Content

What's hot (20)

Similar to 2. 8085-Microprocessor.pptx (20)

More from ISMT College (18)

Recently uploaded (20)

2. 8085-Microprocessor.pptx

Editor's Notes