20-ARM Design Philosophy, Overview of ARM architecture-10-04-2025.ppt
- 2. ARM history • 1983 developed by Acorn computers – To replace 6502 in BBC computers – 4-man VLSI design team – Its simplicity comes from the inexperience team – Match the needs for generalized SoC for reasonable power, performance and die size – The first commercial RISC implemenation • 1990 ARM (Advanced RISC Machine), owned by Acorn, Apple and VLSI
- 3. ARM Ltd Design and license ARM core design but not fabricate
- 4. Why ARM? • One of the most licensed and thus widespread processor cores in the world – Used in PDA, cell phones, multimedia players, handheld game console, digital TV and cameras – ARM7: GBA, iPod – ARM9: NDS, PSP, Sony Ericsson, BenQ – ARM11: Apple iPhone, Nokia N93, N800 – 75% of 32-bit embedded processors • Used especially in portable devices due to its low power consumption and reasonable performance
- 6. ARM processors • A simple but powerful design • A whole family of designs sharing similar design principles and a common instruction set
- 7. Naming ARM • ARMxyzTDMIEJFS – x: series – y: MMU(Memory Management Unit) – z: cache – T: Thumb – D: debugger – M: Multiplier – I: EmbeddedICE (built-in debugger hardware) – E: Enhanced instruction – J: Jazelle (JVM) – F: Floating-point – S: Synthesizible version (source code version for EDA tools)
- 8. Popular ARM architectures • ARM7TDMI – 3 pipeline stages (fetch/decode/execute) – High code density/low power consumption – One of the most used ARM-version (for low-end systems) – All ARM cores after ARM7TDMI include TDMI even if they do not include TDMI in their labels • ARM9TDMI – Compatible with ARM7 – 5 stages (fetch/decode/execute/memory/write) – Separate instruction and data cache • ARM11
- 9. ARM family comparison year 1995 1997 1999 2003
- 10. The RISC Design Philosophy • RISC is characterized by limited number of instructions • A complex instruction is obtained as a sequence of simple instructions. • So, in RISC processor, software is complex but the processor architecture is simple. • Large number of registers are required. • Pipelined instruction execution. • Ex : ARM, ATMEL AVR, MIPS, Power PC etc
- 11. The CISC Design Philosophy • CISC is characterized by large instruction set. • The aim of designing CISC processors is to reduce software complexity by increasing the complexity of processor architecture. • Very small number of registers are available. • Ex : Intel X86 family, Motorola 68000 series.
- 13. ARM is a RISC • RISC: simple but powerful instructions that execute within a single cycle at high clock speed. • Four major design rules: – Instructions: reduced set/single cycle/fixed length – Pipeline: decode in one stage/no need for microcode – Registers: a large set of general-purpose registers – Load/store architecture: data processing instructions apply to registers only; load/store to transfer data from memory • Results in simple design and fast clock rate • The distinction blurs because CISC implements RISC concepts
- 14. RISC –4 major design rules 1. Instructions • Reduced Number of Instructions • Execute in a single cycle • The compiler synthesizes complicated operations • Each instruction is a fixed length
- 15. 2. Pipelines • The processing of instructions is broken down into smaller units that can be executed in parallel by pipelines
- 16. 3. Registers • Have a large general purpose register set • Any register can contain either data or address
- 17. 4. Load –Store Architecture • Separate load and store instructions transfers data between the register bank and external memory. • Memory accesses are costly, so separating memory access from data processing provides an advantage, because you can use data items held in register banks multiple times without needing multiple memory accesses.
- 18. Load/Store Architecture • Memory accesses slow a processor down. • There are times when the processor is doing nothing, while waiting for memory accesses to complete. • So, we define a new architecture. In this new load/store architecture, the addressing mode for every operand is fixed. (So, there are no bytes for addressing mode information.) • And, for arithmetic/logical type instructions, the addressing mode for all operands will be register mode. • We make sure that there are enough registers, because everything ends up in registers. • To get stuff to/from memory and into/out of registers, we have explicit instructions that move data. • Load instructions read data from memory and copy it to a register. Store instructions write data from a register to memory.
- 19. ARM features • Different from pure RISC in several ways: – Variable cycle execution for certain instructions: multiple-register load/store (faster/higher code density) – Inline barrel shifter leading to more complex instructions: improves performance and code density – Thumb 16-bit instruction set: 30% code density improvement – Conditional execution: improve performance and code density by reducing branch – Enhanced instructions: DSP instructions
- 20. ARM architecture Data Flow Model
- 24. ARM architecture • Load/store architecture • A large array of uniform registers • Fixed-length 32-bit instructions • 3-address instructions
- 25. Registers Register file contains in all 37 registers • 20 registers are hidden from program at different times. These registers are called banked registers • Banked registers are available only when the processor is in a particular mode General purpose registers hold either data or address All registers are of 32 bits In user mode 16 data registers and 2 status registers are visible
- 26. Registers contd.. Data registers: r0 to r15 • Three registers r13, r14 and r15 perform special functions • r13: stack pointer • r14: link register (where return address is stored whenever a subroutine is called) • r15: program counter Depending upon context r13 and r14 can also be used as GPR In addition, there are two status registers o CPSR: Current Program Status Register o SPSR: Saved Program Status Register
- 28. General-purpose registers 0 8 7 16 15 24 23 31 8-bit Byte 16-bit Half word 32-bit word • 6 data types (signed/unsigned) • All ARM operations are 32-bit. Shorter data types are only supported by data transfer operations.
- 29. Program counter • Store the address of the instruction to be executed • All instructions are 32-bit wide and word- aligned • Thus, the last two bits of pc are undefined.
- 30. Current Program status register (CPSR) mode bits overflow carry/borrow zero negative Thumb state FIQ disable IRQ disable Saturation
- 32. J - Jazelle Third execution state that allows some ARM processors to execute Java bytecode in hardware.
- 35. Processor modes Processor modes determine • Which registers are active and • Access rights to CPSR register itself Each processor mode is either • Privileged: full read-write access to the CPSR • Non-privileged: only read access to the control field of the CPSR but read-write access to the condition flags
- 36. Processor modes
- 40. Pipeline ARM7 In execution, pc always 8 bytes ahead
- 43. • ARM 9 - Five Stage Pipeline
- 45. Pipeline • Execution of a branch or direct modification of pc causes ARM core to flush its pipeline • ARM10 starts to use branch prediction • An instruction in the execution stage will complete even though an interrupt has been raised. Other instructions in the pipeline are abondond.
- 47. Interrupts
- 48. References