2nd Semester M Tech: VLSI Design and Embedded System (June-2016) Question Papers

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USN I4EYEzI
(06 Marks)
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Time: 3 hrs. Max. Marks:100
Note: Answer any FIV'E.full questions.
a. Derive the expression for drain current of enhancement NIVIOSFET operating in saturation.
(08 Marks)
b. What is channel length modulation? Plot V-l characteristics of enhancement MOSFET
showing effect of it. If the length of MOSFET is doubled, plot V-I characteristics clearly
a. Derive the expression for voltage gain of common source amplifier with diode connected
NMOS load. (08 Marks)
b. Obtain the expression for output impedance of the source follower. (06 Marks)
c. For circuit shown in Fig. Q2 (c), calculate the voltage gain using small signal equivalent
circuit. Assume 1" : 0. (06 Marks)
Vbo
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Fie. Q2 (c)
circuit,, derive expression
showing the change in slope.
c. Consider process technology for which Lmin : 0.4 Fffi , tox :
and V, :0.7Y
i) Find C.,* and Ki .
ii) For a MosFET with I - ^tl*L O.Bprm
Calculate Vcs and Vns,,,i,, with dc current [,, = l00pA .
Using high frequency equivalent
circuit shown in Fig. Q3 (a).
v v r...-h
Fig. Q3 (a)
b. Using superposition principle, derive the expression for small
coupled differential amplifier with resistive load.
c. With help of basic differential pair with resistive load derive
Gilbert cell and describe the same.
signal voltage gain of source
(06 Marks)
the schematic design for
(08 Marks)
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4a.
b.
a.
b.
I4E.YEzI
Derive the expression for voltage gain of the active current mirror circuit with differential
pair. (10 Marks)
Through relevant circuit diagram, explain how gain boosting and boosting of output
impedance is achieved in cascade stage. (10 Marks)
Sketch the circuit of three stage ring oscillator. Determine individual stage gain andpoles of
the system. (10 Marks)
Derive the mathematical model of VCO. Describe the performance parameters of VCO.
(I0 Marks)
a. Explain the principle of simple Pn-L with relevant block diagram and waveform. (06Marks)
b. With neat diagram, explain charge-pump PLL. (08 Marks)
c. Explain how PTAT currents are generated, discuss the various schematic designs used to
generate the PTAT currents. (06 Marks)
Explain temperature independent references. Find the expression for positive temperature7a.
b.
coefficient (TC) voltage and negative TC voltage.
Explain ADC specification with relevant diagrams and examples.
(10 Marks)
(10 Marks)
a. Describe the R-2R ladder DAC architecture for 4 bit DAC. Find the analog output using R-
2R ladder DAC rnethod for the input digital words 1000, 1100 and 1010. Assume Vng: 8
VandRp:2R (08 Marks)
For 6 bit charge scaling DAC using split capacitance, find the DAC output for digital input
i) 010000 and ii) 000100. Also write the equivalent circuit. Assume Vnrp: 5 V. ios rvruir.r)
Draw the block diagram of the successive approximation ADC architecture and also explain
the algorithm used to find digital output. (04 Marks)
b.
c.
8***8

USN t{HVE22
Low Power VLSI Design
Time: 3 hrs. M ax. M arks: 1 00
Note: Answer any FIVE full qwestions"
a. Explain the need for Low Power VLSI design. (08 Marks)
b. With usual notations show that dynamic power dissipation in an inverter is given by
Pa: C. V'f The chip size of a CPU is 15mm x 25mm with clock frequency of 300 MHz
operating at3.3V. The length of the clock routing is estirnated to be twice the circumference
of the chip. Assume that the clock signal is routed on a metal layer with a width of 1.2pm
and the parasitic capacitance of the metal layer is I fFitrrm2. What is the power dissipation of
the clock signal? (12 Marks)
a. Explain with neat diagram, the structure of MIS diode. f)raw the energy band diagram of
unbiased MIS diode. (08 Marks)
b. Explain the advantages and lirnitations of SPICE Power Analysis Method. (06 Marks)
c. Derive an expression for number of samples 'N' required for stopping criteria in Monte
Carlo Sirnulation. (06 Marks)
Compute the transition density and static probability of Y : ab + c. Given P(a) : 0.2 ,
P(b):0.3 , F(c):0.4 , D(a): 1 , D(b) :2 and D(c):3. (t0Marks)
Define Signal Entropy. Explain power estimation of combinational logic using entropy
analysis. (I0 Martrs)
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a. Derive relation between Conditional probability and Frequency.
b. For combinational circuit, rvrite the algorithm horv Transition density
analysis at gate level.
c. Briefly explain the characterization of logic signals.
What are Glitches? What is
minimized?
Explain bnefly the itrliowing :
their effect on power consumption?
i) Latches ii) Flip flops.
(07 Marks)
is used for power
(07 Marks)
(06 Marks)
How can they be
(10 Marks)
(10 Marks)
8a.
b.
a. Discuss sources of Power dissipation in SRAM and DRAM.
b. How do you optimize power consumption for design case like FIR filter?
Explain the power analysis and estimation technique at the algorithrn ievel.
Write short notes on :
i) 8 - bit Wallace multiplier.
ii) Low power digital cell library.
What is Gate Reorgani'zation? Briefiy explain different power saving techniques through
Gate reorganization, Signal gating and Logic encoding techniques. (12 Marks)
What is Precotnputation Logic? E,xplain the precompr-rtation logic for an n - bit comparator.
(08 Marks)
(10 Marks)
(10 Marks)
(I0 Marks)
(10 Marks)

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Time: 3 hrs.
VL$t TestEurg and Verification
M ax. M arks: I 00
14EVE23
2&16
(10 Marks)
(05 Marks)
(05 ${arks)
(04 Mar*si
(06 Marks)
(10 Marks)
(10 Marks)
(05 Marks)
(05 NIarks)
role in deep
(10 Marks)
(05 Marks)
(05 Marks)
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What is path sensitization? Explain with example. (0S &{arks}
Give D-aigorithm using cubical algorithrn for autornatic test pattern generator. (10 Marks)
Using PODEM algorithnt derive tests for the circuits girren in Fig.Q2(c).
r lg.'21(c) (05 iViarks)
Explain with circuit diagrarn, hor.r, clouble-latch and single-iatch LSSD techniques to
improve testability. (tS Marks)
Expiain boundary scan method aiong with test access pat (TAP) architecture. (10 Marks)
a. Explain in detaii about syndrome driver counter and LFSR./SR methods for pseudoexaustive
pattern generator. (10 Marks)
b. Explain with ciiagrarn syncirorne checking and signature analysis compression techniques
used in a BIST environment. (tr8 M*rks)
Note: Answev any FtrVE fwll questions.
a. Why VLSI testing? Discuss in detail about testing philosophy.
b. Explain how lauits are rtrocleled in digital circuits.
c. What are ternporary laults'? Also expiain horv they are detected.
a. Give comparison betrveen testing and verification.
b. Give three different approaches for functional verification.
c. Differentiate between equivalence checking and model checking.
a. What is sintulators'/ Also cxplain cycle based sirnulation and co-simulators.
b. Explain path coverage and expression coverage tools.
c. Explain with diagrarn verification tool wavefbnn viewer.
a. Explain with clear reason how noise in signal integrity plays important
submicron technologies.
b. What are the limitations of static tiniing analysis (STAX
c. What are design checks'? E,xplain electrical and layout rule checks.
Write notes on the following:
a. AS IC verification
b. Partiai scan technique f,or testability '
c. BILBO based BIST architecture
d. Cross talk glitch analysis
f
a.
b.
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(20 Marks)

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Begree Exaxmimwtion, .Fe.:lme/-Iuly 2SI 6
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Note: Answer eny FIVE full cJuestions.
a. Define SOC. Compare SOC, SIP and SOB. (04 Marks)
b. Whai is the significance ofl'reusable macros' (lP) rn the designing of SOC? Explain various
types of,reusable rnacros (IP) used in SOC. (08 &farks)
c. Define the terrn'design nroductivity gan'. Also discuss the eflbct of this ontime to market.
(#E &,Ierks)
a- What is the importance of using specifications in SOC d"esign? Explain the types of
specification used in detail. (Is Marksi
b. With the help cf neat diagranr. explain the principle of waterfall ctesign flcw used in SOC.
{18 &farksi
Write notes crn :
a. ESL Design Flow
b. Constant Field Scaling
c. Timing Closure Probier:l
a. Discuss the challenges associated with the design of'MpSoC.
b, What is XTMP model? Explain the steps required to design an XTMP model.
a- Compare the characteristics between NOR and NAND flash rnemory. With neat diagrarn,
Explain the rvorking of NoR Flaslr menlor)/. (18 Marks)
b. Explain the various mapping techniques used in Cache rnemory architectrire. (10 Marks)
a. Discuss the limitatiotts of Bus based architecture used in neiwork on chip (NOC). (10 Marks)
b. Discuss abcut the various routing techniques used in NOC. {10 h{arks)
a. With tile help of timing diagrarn, explain the riifferent rjata transfer moctes used in tsus based
NOC. (15 &IarEts)
b. Explain the worm hole switching in Soc. {05 &,[*rks]
a. What is TIE Language? Wrtte a program in TIE Langllage to adri a new register file and a
new instruction to the Xtensa processor. (0S &derks)
b. Explain the energy aware on-chlp communication system design. (trs iVflarks)
a***r<

2nd Semester M Tech: VLSI Design and Embedded System (June-2016) Question Papers

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2nd Semester M Tech: VLSI Design and Embedded System (June-2016) Question Papers