3-UNIT3_BOOLEAN ALGEBRA.pptx
- 5. COMMUTATIVE LAW: VERIFICATION OF A+B=B+A A B A+B B+A 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1
- 6. COMMUTATIVE LAW: VERIFICATION OF A.B=B.A A B A.B B.A 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1
- 8. ASSOCIATIVE LAW: VERIFICATION OF A+(B+C)=(A+B)+C A B C B+C A+(B+C) (A+B) (A+B)+C 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
- 9. ASSOCIATIVE LAW: VERIFICATION OF A.(B.C)=(A.B).C A B C (A.B) (B.C) A.(B.C) (A.B).C 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 1 1 1
- 12. DISTRIBUTIVE LAW: VERIFICATION OF A.(B+C)=(A.B)+(A.C) A B C B+C (A.B) (A.C) A.(B+C ) (A.B)+(A.C) 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1
- 13. DISTRIBUTIVE LAW: VERIFICATION OF A+(B.C)=(A+B).(A+C) A B C B.C (A+B) (A+C) A+(B.C ) (A+B).(A+C ) 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
- 17. 1. COMPLEMENT OF SUM OF TWO QUANTITIES IS EQUAL TO PRODUCT OF THEIR INDIVIDUAL COMPLEMENTS.
- 18. 2. COMPLEMENT OF PRODUCT OF TWO QUANTITIES IS EQUAL TO SUM OF THEIR INDIVIDUAL COMPLEMENTS.
- 19. SIMPLIFICATION OF EXPRESSIONS USING BOOLEAN LAWS
- 36. K MAP FOR 2 VARIABLES
- 37. K MAP FOR 3 VARIABLES
- 38. K MAP FOR 4 VARIABLES W X Y Z MIN TERMS 0 0 0 0 m0 0 0 0 1 m1 0 0 1 0 m2 0 0 1 1 m3 0 1 0 0 m4 0 1 0 1 m5 0 1 1 0 m6 0 1 1 1 m7 1 0 0 0 m8 1 0 0 1 m9 1 0 1 0 m10 1 0 1 1 m11 1 1 0 0 m12 1 1 0 1 m13 1 1 1 0 m14 1 1 1 1 m15
- 42. RULES FOR K-MAP SIMPLIFICATION 1. Group must contain only those cells that contain 1.(for SOP) 2. Groups may be horizontal/vertical but not diagonal. 3. Group must contain 1,2,4,8 or in general 2n cells. 4. Each group should be as large as possible. 5. Group may overlap to form a large group. 6. Each cell containing a 1 must be in atleast one group.
- 43. 7. Groups may wrap around the table. Leftmost cell may be grouped with rightmost cell and top cell may be grouped with bottom cell. 8. Fold up the corners of map below like it’s a napkin/paper to make 4 cells physically adjacent. 9. There can be more than one minimized solution. 10. There should be few groups as possible.
- 57. MULTIPLEXER MULTIPLEXER: Multiplexer means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input lines and n selection lines whose bit combination determine which input is selected. A multiplexer is also called as a Data Selector as it selects one of the inputs and passes it in the output based on the values of select input sequence.
- 58. 2:1 MULTIPLEXER A 2:1 multiplexer consists two data input lines as I0 and I 1, only one select lines as S0 and a single output line Y. The select lines S0 select one of the two input lines to connect the output line. The particular input combination on select lines selects one of input (I0 and I 1) to the output. The figure below shows the block diagram of a 2:1 multiplexer in which the multiplexer decodes the input through select line.
- 59. LOGIC DIAGRAM OF 2:1 MULTIPLEXER
- 60. The truth table of a 2:1 multiplexer is shown below in which two input combinations 0 and 1 on the select lines respectively switches the inputs I0 and I1 the output. That means when S0 =0, the output at Y is I0, similarly Y is I1 if the select inputs S0 =1 and so on. From the above truth table, we can write the output expressions as If S0 =0, then Y = I0 If S0 =1 then Y = I3 EN’ S0 Y 1 X 0 0 0 I0 0 1 I1 INPUTS OUTPUT
- 61. WORKING: When select inputs areS0 =0, then the output Y = I0 When select inputs areS0 =1 , then the output Y = I 1
- 62. 4:1 MULTIPLEXER A 4:1 multiplexer consists four data input lines as I0 ,I 1 ,I 2 and I 3, two select lines as S0 and S 1 and a single output line Y. The select lines S0 and S 1 select one of the four input lines to connect the output line. The particular input combination on select lines selects one of input (I0 ,I 1 ,I 2 and I 3) to the output. The figure below shows the block diagram of a 4:1 multiplexer in which the multiplexer decodes the input through select line.
- 63. The truth table of a 4:1 multiplexer is shown below in which four input combinations 00, 10, 01 and 11 on the select lines respectively switches the inputs I0 ,I1 ,I2 and I3 to the output. That means when S0 =0 and S1 =0 , the output at Y is I0, similarly Y is I1 if the select inputs S0 =0 and S1 =1 and so on. From the above truth table, we can write the output expressions as If S0 =0 and S1 =0 , then Y = I0 If S0 =0 and S1 =1 , then Y = I1 If S0 =1 and S1 =0 , then Y = I2 If S0 =1 and S1 =1 , then Y = I3 EN’ S1 S0 Y 1 X X 0 0 0 0 I0 0 0 1 I1 0 1 0 I2 0 1 1 I3 INPUTS OUTPUT
- 64. From the expressions of the truth table, a 4:1 multiplexer can be implemented by using basic logic gates. The below figure shows the logic circuit of 4:1 MUX:
- 65. WORKING: WhenS0 =0 and S1 =0 , then Y = I0 When S0 =0 and S1 =1 , then Y = I1 WhenS0 =1 and S1 =0 , then Y = I2 WhenS0 =1 and S1 =1 , then Y = I3
- 66. 8:1 MULTIPLEXER An 8:1 multiplexer consists eight data input lines as I0 ,I 1 ,I 2, I 3 ,I4 ,I5,I6 and I7;three select lines as S0 S 1 and S 2 and a single output line Y. The select lines S0 S 1 and S 2 select one of the eight input lines to connect the output line. The particular input combination on select lines selects one of input (I0 ,I 1 ,I 2, I 3 ,I4 ,I5,I6 and I7) to the output. The figure below shows the block diagram of a 8:1 multiplexer in which the multiplexer decodes the input through select line.
- 67. The truth table of a 8:1 multiplexer is shown below in which eight input combinations 000, 001,010,011,100,101,110 and 111 on the select lines respectively switches the inputs I0 ,I1 ,I2, I3 ,I4 ,I5,I6 and I7 to the output. That means when S0 =0,S1 =0 and S2 =0 the output at Y is I0, similarly Y is I1 if the select inputs S0 =0,S1 =0 and S2 =1 and so on. From the truth table, we can write the output expressions as If S2 =0,S1 =0 and S0 =0 , then Y = I0 If S2 =0,S1 =0 and S0 =1, then Y = I1 If S2 =0,S1 =1 and S0 =0, then Y = I2 If S2 =0,S1 =1 and S0 =1 , then Y = I3 If S2 =1,S1 =0 and S0 =0 , then Y = I4 If S2 =1,S1 =0 and S0 =1 , then Y = I5 If S2 =1,S1 =1 and S0 =0 , then Y = I6 If S2 =1,S1 =1 and S0 =1 , then Y = I7 EN’ S2 S1 S0 Y 1 X X X 0 0 0 0 0 I0 0 0 0 1 I1 0 0 1 0 I2 0 0 1 1 I3 0 1 0 0 I4 0 1 0 1 I5 0 1 1 0 I6 0 1 1 1 I7 INPUTS OUTPUT
- 68. From the expressions of the truth table, a 8:1 multiplexer can be implemented by using basic logic gates. The below figure shows the logic circuit of 8:1 MUX:
- 69. WORKING: when S 2 =0,S1 =0 and S 0=0 , then Y = I0 when S 2 =0,S1 =0 and S 0=1, then Y = I1 when S 2 =0,S1 =1 and S 0=0, then Y = I2 when S 2 =0,S1 =1 and S 0=1 , then Y = I3 when S 2 =1,S1 =0 and S 0=0 , then Y = I4 when S 2 =1,S1 =0 and S 0=1 , then Y = I5 when S 2 =1,S1 =1 and S 0=0 , then Y = I6 when S 2 =1,S1 =1 and S 0=1 , then Y = I7
- 70. 16:1 MULTIPLEXER An 16:1 multiplexer consists sixteen data input lines as I0 ,I 1 ,I 2, I 3 ….I 15, four select lines as S0 S 1 S 2 and S3 and a single output line Y. The select lines S0 S 1 S 2 and S3 select one of the sixteen input lines to connect the output line. The particular input combination on select lines selects one of input (I0 ,I 1 ,I 2, I 3 ….I 15) to the output. The figure below shows the block diagram of a 16:1 multiplexer in which the multiplexer decodes the input through select line.
- 71. The truth table of a 16:1 multiplexer is shown below in which sixteen input combinations 0000, 0001,0010,0011,0100,0101,0110,0111, 1001,1010,1011,1100,1101,1110,1111 on the select lines respectively switches the inputs I0 ,I1 ,I2, I3, ….I14 ,I15,to the output. That means when S3 =0,S2 =0, S1 =0 and S2 =0 , the output at Y is I0 , Similarly Y is I1 if the select inputs S3=0, S2=0, S1=0 and S0=1. EN’ S3 S2 S1 S0 Y 1 X X X X 0 0 0 0 0 0 I0 0 0 0 0 1 I1 0 0 0 1 0 I2 0 0 0 1 1 I3 0 0 1 0 0 I4 0 0 1 0 1 I5 0 0 1 1 0 I6 0 0 1 1 1 I7 0 1 0 0 0 I8 0 1 0 0 1 I9 0 1 0 1 0 I10 0 1 0 1 1 I11 0 1 1 0 0 I12 0 1 1 0 1 I13 0 1 1 1 0 I14 0 1 1 1 1 I15 INPUTS OUTPUT
- 72. LOGIC DIAGRAM OF 16:1 MULTIPLEXER
- 73. WORKING: when S3 =0,S 2 =0, S1 =0 and S 0=0 then Y = I0 when S3 =0,S 2 =0, S1 =0 and S 0=1 , then Y = I1 when S3 =0,S 2 =0, S1 =1 and S 0=0 , then Y = I2 when S3 =0,S 2 =0, S1 =1 and S 0=1 , then Y = I3 when S3 =0,S 2 =1, S1 =0 and S 0=0 , then Y = I4 when S3 =0,S 2 =1, S1 =0 and S 0=1 , then Y = I5 when S3 =0,S 2 =1, S1 =1 and S 0=0 , then Y = I6 when S3 =0,S 2 =1, S1 =1 and S 0=1 , then Y = I7 when S3 =1,S 2 =0, S1 =0 and S 0=0 , then Y = I 8 when S3 =1,S 2 =0, S1 =0 and S 0=1 , then Y = I 9 when S3 =1,S 2 =0, S1 =1 and S 0=0 , then Y = I 10 when S3 =1,S 2 =0, S1 =1 and S 0=1 , then Y = I 11 when S3 =1,S 2 =1, S1 =0 and S 0=0 , then Y = I 12 when S3 =1,S 2 =1, S1 =0 and S 0=1 , then Y = I 13 when S3 =1,S 2 =1, S1 =1 and S 0=0 , then Y = I 14 when S3 =1,S 2 =1, S1 =1 and S 0=1 , then Y = I 15
- 74. DEMULTIPLEXER A demultiplexer (or demux) is a device that takes a single input line and routes it to one of several digital output lines. A demultiplexer of 2n outputs has n select lines, which are used to select which output line to send the input. A demultiplexer is also called a data distributor.
- 76. DESCRIPTION OF 1:4 DEMUX The 1:4 Demultiplexer consists of 1 input signal, 2 select input signals and 4 output signals. The number of the output signal is always decided by the number of the control signal and vice versa. There are 2 NOT gates through which select inputs are passed, and 4 NAND gates, which decides or control the output. The combination of the input signal along with control signals will decide that the output through which input signal will pass through.
- 77. The truth table of a 1:4 demultiplexer is shown below in which four input combinations 00, 10, 01 and 11 on the select lines switches the input I at the terminals Y0 ,Y1 ,Y2 and Y3 output in complement form. That means when S1 =0 and S0 =0 , the output at Y is Y0 in complement form, similarly Y is Y1 if the select inputs S1 =0 and S0 =1 and so on. From the above truth table, I is available in complement form at Y0 ,Y1 ,Y2 and Y3 ,we can write the output expressions as If S1 =0 and S0 =0 , then Y = Y0 (in complement form) If S1 =0 and S0 =1 , then Y = Y1(in complement form) If S1 =1 and S0 =0 , then Y = Y2(in complement form) If S1 =1 and S0 =1 , then Y = Y3(in complement form) S1 S0 Y 0 0 Y0 0 1 Y1 1 0 Y2 1 1 Y3 SELECT INPUTS OUTPUT ‘I’ available in complement form
- 78. LOGIC DIAGRAM OF 1:4 DEMULTIPLEXER
- 80. DESCRIPTION OF 1:8 DEMUX The 1:8 Demultiplexer consists of 1 input signal, 3 select signals and 8 output signals. The number of the output signal is always decided by the number of the control signal and vice versa. There are 3 NOT gates through which select inputs are passed, and 8 NAND gates, which decides or control the output. The combination of the input signal along with control signals will decide that the output through which input signal will pass through.
- 81. The truth table of a 1:8 demultiplexer is shown below in which eight input combinations 000,001,010,011,100,101,110 and 111 on the select lines switches the input I at the terminals Y0 ,Y1 ,Y2 ,Y3 , Y4 ,Y5 , Y6 and Y7 output in complement form. That means when S2 =0 ,S1 =0 and S0 =0 , the output at Y0 in complement form of I , similarly output is Y1 if the select inputs S2 =0 ,S1 =0 and S0 =1 and so on. S2 S1 S0 Y 0 0 0 Y0 0 0 1 Y1 0 1 0 Y2 0 1 1 Y3 1 0 0 Y4 1 0 1 Y5 1 1 0 Y6 1 1 1 Y7 SELECT INPUTS OUTPUT ‘I’ available in complement form
- 82. WORKING OF 1:8 DEMUX From the above truth table, I is available in complement form at Y0 ,Y1 ,Y2 and Y3 ,we can write the output expressions as If S 2=0 ,S1 =0, S0 =0 , then Y = Y0 (in complement form) If S 2=0 ,S 1=0 and S0=1 , then Y = Y1 (in complement form) If S 2=0 ,S1 =1and S0 =0 , then Y = Y2 (in complement form) If S 2=0 ,S1 =1and S0 =1 , then Y = Y3 (in complement form) If S 2=1 ,S1 =0, S0 =0 , then Y = Y 4 (in complement form) If S 2=1 ,S 1=0 and S0=1 , then Y = Y 5 (in complement form) If S 2=1 ,S1 =1and S0 =0 , then Y = Y 6 (in complement form) If S 2=1 ,S1 =1and S0 =1 , then Y = Y 7 (in complement form)
- 83. LOGIC DIAGRAM OF 1:8 DEMULTIPLEXER
- 85. DESCRIPTION OF 1:16 DEMUX The 1:16 Demultiplexer consists of 1 input signal, 4 select signals and 16 output signals. The number of the output signal is always decided by the number of the control signal and vice versa. There are 4 NOT gates through which select inputs are passed, and 16 NAND gates, which decides or control the output. The combination of the input signal along with control signals will decide that the output through which input signal will pass through. The truth table of a 1:16 demultiplexer is shows sixteen input combinations 0000,0001,…..,1110 and 1111 on the select lines switches the input I at the terminals Y0 ,Y1 ,Y2 ,.. , Y14 and Y15 output in complement form. That means when S3 =0 ,S2 =0 ,S1 =0 and S0 =0 , the output at Y0 in complement form of I , similarly output is at Y1 if the select inputs S3 =0 ,S2 =0 ,S1 =0 and S0 =1 and so on.
- 86. S3 S2 S1 S0 Y 0 0 0 0 Y0 0 0 0 1 Y1 0 0 1 0 Y2 0 0 1 1 Y3 0 1 0 0 Y4 0 1 0 0 Y5 0 1 1 0 Y6 0 1 1 1 Y7 1 0 0 0 Y8 1 0 0 1 Y9 1 0 1 0 Y10 1 0 1 1 Y11 1 1 0 0 Y12 1 1 0 1 Y13 1 1 1 0 Y14 1 1 1 1 Y15 SELECT INPUTS O/P ‘I’ available in complement form
- 87. WORKING OF 1:16 DEMUX From the above truth table, I is available in complement form at Y0 ,Y1 ,Y2…..Y15 ,we can write the output expressions as: If S3 =0, S2 =0 ,S1 =0, S0 =0 , then Y = Y0 (in comp form) If S3 =0 ,S2 =0 ,S1 =0 and S0=1 , then Y = Y1 (in comp form) If S3 =0 ,S2 =0 ,S1 =1 and S0 =0 , then Y = Y2 (in comp form) If S3 =0 ,S2 =0 ,S1 =1 and S0 =1 , then Y = Y3 (in comp form) If S3 =0 ,S2 =1 ,S1 =0, S0 =0 , then Y = Y4 (in comp form) If S3 =0 , S2 =1 ,S1 =0 and S0=1 , then Y = Y5 (in comp form) If S3 =0 ,S2 =1 ,S1 =1 and S0 =0 , then Y = Y6 (in comp form) If S3 =0 ,S2 =1 ,S1 =1 and S0 =1 , then Y = Y7 (in comp form) If S3 =1, S2 =0 ,S1 =0, S0 =0 , then Y = Y8 (in comp form) If S3 =1 ,S2 =0 ,S1 =0 and S0=1 , then Y = Y9 (in comp form) If S3 =1 ,S2 =0 ,S1 =1 and S0 =0 , then Y = Y10 (in comp form) If S3 =1 ,S2 =0 ,S1 =1 and S0 =1 , then Y = Y11 (in comp form) If S3 =1 ,S2 =1 ,S1 =0, S0 =0 , then Y = Y12 (in comp form) If S3 =1 ,S2 =1 ,S1 =0 and S0=1 , then Y = Y13 (in comp form) If S3 =1 ,S2 =1 ,S1 =1 and S0 =0 , then Y = Y14 (in comp form) If S3 =1 ,S2 =1 ,S1 =1 and S0 =1 , then Y = Y15 (in comp form)
- 88. LOGIC DIAGRAM OF 1:16 DEMULTIPLEXER
- 89. COMPARISON OF MULTIPLEXER & DEMULTIPLEXER MULTIPLEXER DEMULTIPLEXER Multiplexer has many input signals and only one output. Demultiplexer has many input signals and only one output. Multiplexer is also called as Data Selector. Demultiplexer is also called as Data Distributor. It is called MUX. It is called DEMUX. MUX receives many inputs and passes only one of those in the output. DEMUX receives one input and distributes it in the output. MUX is used in parallel to serial conversion. DEMUX is used in serial to parallel conversion. No additional gates are needed while designing MUX. Additional gates are needed while designing DEMUX. MUX is used Multiplexing where more than one signals are combined into one signal that travels on a medium. DEMUX is used in demultiplexing where a multiplexed signal is decomposed in individual signals. Enable signal is required while implementing MUX. Enable signal is not required while implementing DEMUX. Ex: 4:1 , 8:1 , 16:1 Ex: 1:4 , 1:8 , 1:16