5. Latches and flip-flop do it fasrt f.pdf

CSE 215
Sequential Circuit:
Latches & Flip-Flop
Sanath kumar Das, Lecturer, SoSET, EDU
Note: Go through the text books for better understanding

In sequential circuit, output not only depends on current input, but also depends on previous state of the system.
Latches and flip-flops are different types of sequential circuit. They are used as a memory element in the
sequential circuit. They can change or retain the output value based on the input signals.
Remember, to predict the output for, you have to consider both the current input and past output.
Output => present input + past output
To implement the memory element of above diagram, we need a circuit, that can hold previous output
and also can change the output based on the input.

NOR Gate and Nand Gate
Revise
If any input is 1, Output will be 0
If any input is 0, Output will be 1

 2 NOR gates, cross-coupled
 Two output: Qa, Qb indicate state of the circuit
 R(Reset) and S(Set) control the circuit state
 S=0,R=0 (states are maintained)[No change in Qa, Qb]
It remembers its state when both the S and R inputs are
0.
 S=0,R=1 (Reset)Qa=0, Qb=1
 S=1,R=0 (Set)Qa=1, Qb=0
 S=1,R=1 (Invalid Control Inputs). Qa=0, Qb=0
 For the timing diagram, no delay is assumed
 Avoid transition from S=1,R=1 to S=0,R=0 as it causes Qa,
Qb to oscillate between 0,0 and 1,1.
[at t9 and t10 point in Fig 5.4(c)]
 SR latch also can be built by NAND gate
 The SR latch [build by NOR gate], the memory mode
works in when both S and R is set to 0. If SR latch is built
by NAND gate, the memory mode works when both inputs
are set to 1
In the normal operation of the latch, the outputs (Qa,Qb)
will be complements of each other. Avoid S=1, R=1 input
state.
## For easy analysis of SR latch, at first consider
S=1, R=0 or R=1, S=0 condition
Invalid
Memory
Reset
Set

P1. Draw the output waveform (Qa and Qb) the NOR SR latch
S
R
Two Types of SR latch

Complete the truth table for NOR SR latch
Solution
Draw the timing diagram of output (Qa Qb) for NOR SR latch
Solution:

Unlike the NOR-based version, the NAND-
based SR latch uses active-low inputs,
meaning:
•To Set the latch, S = 0 and R = 1
•To Reset the latch, S = 1 and R = 0
•If both S = 1 and R = 1 → No change
(memory state)
•If both S = 0 and R = 0 → Invalid state
Active Low SR latch (This topic is taken from Floyd’s book)
This SR latch is called Active-Low because, Set function works when S = 0 and reset function works when R = 0.
Which is different from Active High SR latch.
Avoid S=0 and R= 0 state in Active Low SR latch.
Memory mode occurs in when S=1, R= 1.

5. Latches and flip-flop do it fasrt f.pdf

SR Latch changes its output immediately based on the inputs S (Set) and R (Reset). It has no control input, so its
output may change any time by the inputs.
Gated SR Latch adds an Enable (EN) input. [In your book, it is called clk(clock) also]. This latch only responds to
S and R when EN is active (or 1), allowing controlled updating of the output. This makes it more stable and suitable
for synchronous systems.  Use 2 AND gates with 2 NOR gates, a
Clk (clock signal) with R and S
 Clk works like an enable signal (it
changes its value from 0 to 1 or 1 to 0
at well defined intervals).
 If Clk =0, S and R don’t matter,
S’=0,R’=0, No change in Q and Q’.
 If Clk =1, it works like a basic latch.
R(Reset) and S(Set) control the
circuit state
 Transition from S=1, R=1 to S=0,R=0
causes Qa, Qb to oscillate between
0,0 and 1,1. So avoid the S=1,R=1
mode.
Note: Clock (CLK) is a square wave-timing signal used in sequential circuits to control when data is stored
or transferred. It acts like a heartbeat, telling flip-flops or latches when to update their output based on
input. You may find the clock frequency of your mobile phone, in the products website.
0 Invalid
R2
S2

Timing Diagram
Try Yourself first!

A gated SR latch [using NAND gates] requires an enable input, clk.
The logic diagram and logic symbol for a gated S-R latch are shown in
Figure 5.6. The S and R inputs control the state to which the latch will
go when a HIGH level is applied to the clk input. The latch will not
change until clk is HIGH; but as long as it remains HIGH, the output
is con-trolled by the state of the S and R inputs.
The gated SR latch (NAND) is a level-sensitive device. In this circuit,
the invalid state occurs when both S and R are simultaneously HIGH
and EN is also HIGH. Memory mode works, when S =0,
R=0.[Slightly different to NAND SR Latch]
𝑺 [𝐼𝑓 𝑐𝑙𝑘 = 1]
Clk S R Q(t+1) 𝑸(𝒕 + 𝟏)
0 x x Q(t) Q(t)
1 0 0 Q(t) Q(t)
1 1 0 1 0
1 0 1 0 1
1 1 1 1 1
Memory
Memory
Set
Reset
Invalid
𝑹 [𝐼𝑓 𝑐𝑙𝑘 = 1]
Truth Table

Clk S R Q(t+1) 𝑸(𝒕 + 𝟏)
0 x x Q(t) Q(t)
1 0 0 Q(t) Q(t)
1 1 0 1 0
1 0 1 0 1
1 1 1 0 0

Gated D latch has single data input, called D, and it stores the value on this input, under the control of a clock
signal. It acts as a memory device. That is, it stores one bit of data.
It avoids invalid states that occur in basic SR latches and ensures only one input (D) controls the output, making the
circuit simpler and safer. When clk = 1, the output Q follows D. When clk = 0, the latch holds its previous state.
No change
Reset
Set
 Single data input D (S and R combined into D)
 If D =1, S=1 R=0, [Set][ if clk = 1]
 If D =0, S=0 R=1, [Reset] [ if clk = 1]
 State of circuit (Q and 𝑄) is changed only when Clk=1
 Impossible to have S=1, R=1 (invalid combination is not
achieved)
 If Clk =1, Q follows the state of D
 If Clk =0, Q does not change its state [Memory Operation]
 The output of the gated D latch is controlled by the level of
the clock input(either 0 or 1), the latch is said to be level
sensitive.

Timing Diagram of Gated D latch

P3. Draw the output waveform (Q) the Gated D latch.
Soln.
See, D latch is a level sensitive device. When clock(clk) signal has High level ( or 1), the output Q, follows the input D.
As long as clk =1, and if input varies within this time, the output D will also change.
In many digital applications, however, it is desirable to limit the responsiveness of a latch circuit to a very short
period of time instead of the entire duration that the clk signal is activated. This is where flip-flops come in.
Flip-flops are edge-triggered devices. They sample the input only at the rising or falling edge of the clock, ensuring stable
and predictable operation. This makes them essential for synchronous sequential circuits like registers and counters.

What is a Clock?
A clock is a signal that oscillates between a high and a low state. It is used to coordinate the actions of a digital circuit.
The transition of a signal from LOW to HIGH or from HIGH to LOW is called an edge. A LOW to HIGH transition is a rising
edge and a HIGH to LOW transition is a falling edge.
Types of Triggering
•There are two types of triggering a)Edge triggering b)Level triggering
•Level triggering: A level-triggered circuit will become active when the clock pulse is at a certain level. Based on which level
(HIGH / LOW ) the circuit is activated level triggering is again classified as negative level triggering circuits and positive level
triggering. In positive edge triggering the circuit become active when the clock pulse is high (e.g. D latch).
Edge triggering: An edge-triggered circuit will become active at a positive or negative edge of the clock signal. When a clock
signal goes from low to high, it is called a rising edge (positive edge). A positive edge-triggered circuit will update its state on
the rising edge of the clock signal. Similarly, when a clock signal goes from high to low, it is called a falling edge (negative
edge). A negative edge-triggered circuit will update its state on the falling edge of the clock signal.

Four Types of Triggering and The Symbol

Propagation Delay of logic circuit
All logic gates need a very short propagation delay. Propagation delay is the time it takes for a signal to travel from
the input to the output of a logic gate or circuit meaning the time it takes for a change in the input to be reflected
at the output.

In the level-sensitive latches, the state of the latch keeps changing according to the values of input signals during
the period when the clock signal is active (equal to 1 in our examples). There is also a need for storage elements
that can change their states no more than once during one clock cycle.
Flip-flops are storage elements that can change their states no more than once during one clock cycle. Flip-Flops
are called also “Synchronous circuit”.
Fig. Master- Slave D Flip-Flop
 Two gated D latches (One master, One Slave)
 It is typically built with 8 NAND gates (4 for each latch)
 Master changes state when Clock = 1, Slave changes state
when Clock =0
 While Clock = 1, Qm follows any change in D at that time Qs
does not change. As its receive, clk = 0 [due to NOT gate].
 While Clock = 0, Qm does not change at that time, Qs changes
and follow Qm. As its receive, clk = 1
 Thus, the slave can undergo at most one change of state
during a full clock cycle.
 As, the final output is connected to the output of the
slave stage, the master-slave circuit. Regardless of the
number of changes in the D input to the master stage
during one clock cycle, Qs signal will change only once
that corresponds to the D input at the negative edge of
the clock.
 Also, both Master and Slave work as level sensitive
device, but effectively overall circuit works as Edge
Triggering device.
(Negative Edge triggered D Flip-Flop)

Master Slave
Fig. Logic Circuit Diagram of Master Slave D flip Flop
Note that, the Not gate is absent in “Slave” D latch. As always two outputs of “ Master” D latch will be complementary
of each other.

Example of timing diagram for Master Slave Flip-Flop
P4. Draw the timing diagram for Master-Slave Flip flop
Use the Truth table of D latch[slide 14]
to calculate Qm.
To calculate the output of Qs just
consider the negative level of clock and
input Qm (input of slave)

Positive Edge
triggered D flip
Flop
Negative Edge
triggered D flip
Flop
Level triggered D Latch
Qa changes more than once during a clock cycle.
Qb and Qc changes only changes only once during a clock cycle.
Pos. edge triggered Flip Flop will follow D at pos. edge of clock
Neg. edge triggered Flip Flop will follow D at neg. edge of clock

(Positive Edge Triggered D flip Flop)
Previously, we saw how can we make a Negative edge triggered D flip flop, which updates the data only at the negative edge
of clock signal. Here, we will analyze the circuit diagram of positive edge triggered D flip flop.

When clock=0, P1 = 1, P2 = 1. Which indicates “memory” operation
of Q and 𝑄.
As P2 = 1, P4 = 1. 𝐷 = 𝐷,
As P1 = 1,P3 = 1. 𝐷 = 𝐷
When clock becomes 1,
P1 = 1. 𝑃3 = 1. 𝐷 = 𝐷…………………(1)
P2 = 1. 𝑃4. 𝑃1 = 1. 𝐷. 𝐷 = 𝐷 … … … … … … . (2)
So, if D = 0, P1 = 1 and P2 = 0. So, Q = 0 and 𝑄 = 1.
if D = 1, P1 = 0 and P2 = 1. So, Q = 1 and 𝑄 = 0.
That is , Q is following the D.
Now, we will check, if there is any change in Q, when D changes and
Q remains HIGH(1)
According to eqn (1)
Once D = 0, P2 = 0 and P4 = 1. After that, any further changes in D
will not affect the P4. [NAND gate becomes 1, when at least one
input is 0]. Hence, P4 will not effect the overall state.
According to eqn (2)
Once D = 1, P1 = 0 => P3 = 1 and P2 = 1. As clock = 1 and P3 =1, So,
P1 = 0 forever. As P1 = 0, P2 = 1 forever. That is, the Q 𝑎𝑛𝑑 𝑄 will
not change anymore if D changes.
D can change P4, P4 can change P2 and P3.
Working Principle

Preset means setting the D latch at a pre-specified value [not by D] [Forces the output Q = 1, and 𝑄 = 0]
Clear means clearing the output value of D latch or set it as 0. [Forces to make the output Q = 0 and 𝑄 = 1]
Preset works only when the preset_n = 0.
And clear works only when clear_n = 0. That is why, there is a complementary sign (Fig.a) or bubble (Fig. b).
If Preset or clear becomes 1, they have no effect on NAND gates. Hence, no effect on Q and 𝑄. [ As 𝐴. 1 = 𝐴̅]
Remember, preset and clear become active when their value is 0. [Active Low Input]
They do not disturb the flip-flop when they are equal to 1. Avoid, making the value of both clear and preset pin 0.
(a) (b)

If Clear_n = 0 then the flip-flop goes into the state Q = 0 immediately, regardless of the value of the clock signal.
In such a circuit, where the Clear_n signal is used to clear a flip-flop without regard to the clock signal, we
say that the flip-flop has an asynchronous clear. In practice, it is often preferable to clear the flip-flops on the
active edge of the clock. Such synchronous clear can be accomplished as shown in following Figure.
** Add an AND gate to combine the Clear signal with the D input to achieve Synchronous Clear. As Clear
depends on clock, it is called synchronous clear
Similarly, Preset and clear functionality can be incorporated in positive edge triggered flip-flop.
•If Clr=1, D’= D , usual flip-flop operation
•If Clr=0, D’= 0, regardless of D, flip-flop output (Q) will
be zero on next Clk edge

 T stands for Toggle
 D = T𝑄 + 𝑇𝑄 = T ⊕ Q
 so, actually an XOR gate is connected to input D
 At the positive edge of the clock:
 If T =0, D=Q [ 0 ⊕ A = A, ⊕ means XOR operation]
 So, Q(t+1) = Q(t) [No change]
 If T = 1, D = 𝑄, [1 ⊕ A = 𝐴̅]
 Q(t+1) = 𝑄(𝑡) [Toggle Operation]
 At the negative edge of the clock,
 No change, as it is a positive edge triggered Flipp-Flop
That is , T flip Flop toggle its output (Reverses its present
output) when T=1. It retains its output, if T = 0.
 Very useful in counter device.
NC
Toggle

 It has two inputs (J and K)
 Here, D = J 𝑄 + 𝐾Q
At the positive edge of the clock:
 When J = K = 0, D = Q, So, Q(t+1) = Q(t) [No change]
 If J = 0, K =1, D = 0. So, D = 0. So, Q = 0.
 If J = 1, K = 0, D = 1. So, D = Q + 𝑄 = 1. So, Q = 1.
 If J = K = 1, D = 𝑄. So, Q = 𝑄. [ Toggle Operation]
[ Similar to T flip flop]
 For JK = 00,01,10, it behaves like a SR flip-flop.
Like S= 1, R = 0 [ Set][here, JK = 10]
S= 0, R = 1 [ Reset][here, JK = 01]
S= 0, R = 0 [ Memory][here, JK = 00]
 For JK=11, it behaves like a T flip-flop
 Like JK = 00 No change [ T = 0]
But toggles, when JK =11.[ T =1]
 Thus, it combines the behavior of SR flip-flop
(like J=S, K =R )and T flip-flop.
 The JK flip-flop is a versatile circuit. It can be used for straight
storage purposes, just like the D and SR flip-flops. But it can
also serve as a T flip-flop by connecting the J and K inputs
together.
No changes occur at negative edge. As D flip flop is
used inside

Example Theoretical Problems
1. Explain the working principle of Active HIGH SR latch with Truth table and circuit.
2. Explain the working principle of Active LOW SR latch with truth table and circuit.
3. Explain the working principle of Gated NAND SR latch with truth table and circuit.
4. Explain the working principle of Gated D latch with truth table and circuit.
5. Make a short comparison between edge-sensitive and level-sensitive device.
6. Make a short comparison between latches and flip-flops.
7. Explain the working principle of Master slave D flip-flop with truth table and circuit.
8. Explain the working principle of Master slave D flip-flop with clear and preset
functionality.
9. Explain the working principle of T flop-flop with truth table and circuit.
10.Explain the working principle of JK flop-flop with truth table and circuit.
11. Draw a timing for the circuit of left figure.
12. How can you convert a D flipflop into a T flipflop [Slide 29].
13. How can you convert a D flipflop into a JK flipflop [Slide 31].

Example Mathematical problems
1. Complete the timing diagram for the following circuit
Clk
D
Q1
Q2

2. Complete the timing diagram from Qa, Qb and Qc
Solution

Analysis the output Q for the following circuit configuration
[ Both circuit do the same functions]

The clk waveform is given. Draw the waveform for QA and QB
By connecting flip-flops in this
way, a ‘frequency division’ can
be achieved.
Frequency division is the process of
generating an output signal whose
frequency is a fraction (1/n) of the
clock signal's frequency.
See, The frequency of QA is half of
CLK.
The frequency of QB is one-fourth
of CLK.

[Solution is provided in next slide]

5. Latches and flip-flop do it fasrt f.pdf

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