80386_AKRay.pdf study computer programme
- 1. 80386-32-bit Processor • 80386 has 32-bit Address Bus and 32-bit data bus • 16-byte prefetch queue • Very large address space • 4GB physical memory • 64TB virtual memory • 4GB maximum segment size • Integrated MMU supported by paging and segmentation • 132-pin grid array
- 2. Architecture of 80386 • The Internal Architecture of 80386 is divided into 6 units – Memory management unit (MMU) 1.Segment unit 2.Paging unit 3.Bus interface unit (BIU) – Central processing (CPU) 4. Execution unit 5. Instruction decode unit 6.Code prefetch unit
- 4. • The Memory management unit consists of – a Segmentation unit and a Paging unit. • Segmentation unit: – allows the use of two address components, viz. segment and offset for relocability and sharing of code and data. – allows segments of size 4Gbytes at max. – The Segmentation unit provides a 4 level protection mechanism for protecting and isolating the system code and data from those of the application program. Next page Memory management unit
- 5. • The Paging unit : – organizes the physical memory in terms of pages of 4kbytes size each. – works under the control of the segmentation unit, i.e. each segment is further divided into pages. – The virtual memory is also organizes in terms of segments and pages by the memory management unit. – Paging unit converts linear addresses into physical addresses. • The control and attribute PLA checks the privileges at the page level. Each of the pages maintains the paging information of the task. The limit and attribute PLA checks segment limits and attributes at segment level to avoid invalid accesses to code and data in the memory segments.
- 6. • The Bus interface unit has a prioritizer to resolve the priority of the various bus requests. • This controls the access of the bus. The address driver drives the bus enable and address signal A0 – A31. • The pipeline and dynamic bus sizing unit handle the related control signals. • The data buffers interface the internal data bus with the system bus. Bus interface unit
- 7. GENERAL DATA AND ADDRESS REGISTERS INSTRUCTION POINTER AND FLAG REGISTER SEGMENT SELECTOR REGISTERS CODE SEGMENT DATA SEGMENT CS SS DS ES FS GS EIP EFLAGS IP FLAGS 0 16 31 15 ESP EBP EDI ESI EDX ECX EBX EAX SP BP DI SI DX CX BX AX 0 16 31 15 STACK SEGMENT Register Organization
- 8. Register Organization • The 80386 has eight 32 - bit general purpose registers which may be used as either 8 bit or 16 bit registers. • A 32 - bit register known as an extended register, is represented by the register name with prefix E. • Example : A 32 bit register corresponding to AX is EAX, similarly BX is EBX etc. • The 16 bit registers BP, SP, SI and DI in 8086 are now available with their extended size of 32 bit and are names as EBP,ESP,ESI and EDI. • AX represents the lower 16 bit of the 32 bit register EAX. • Upper 16-bits are neither use nor changed. • BP, SP, SI, DI represents the lower 16 bit of their 32 bit counterparts, and can be used as independent 16 bit registers.
- 9. • The six segment registers available in 80386 are – CS, SS, DS, ES, FS and GS. • The CS and SS are the code and the stack segment registers respectively, • while DS, ES, FS, GS are 4 data segment registers. • A 16 bit instruction pointer IP is available along with 32 bit counterpart EIP. • Flag Register of 80386: – The Flag register of 80386 is a 32 bit register. – Out of the 32 bits, Intel has reserved bits D18 to D31, D5 and D3, while D1 is always set at 1. – Two extra new flags are added to the 80286 flag to derive the flag register of 80386. They are VM and RF flags. Next page
- 10. CF VM RF 0 NT IOPL OF IF TF SF ZF 0 AF 0 PF 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DF 16 17 18 31 RESERVED FOR INTEL FLAGS FLAG REGISTER OF 80386 F L A G S
- 11. • VM - Virtual Mode Flag: If this flag is set, the 80386 enters the virtual 8086 mode within the protection mode. This is to be set only when the 80386 is in protected mode. In this mode, if any privileged instruction is executed an exception 13 is generated. This bit can be set using IRET instruction or any task switch operation only in the protected mode. • RF- Resume Flag: This flag is used with the debug register breakpoints. It is checked at the starting of every instruction cycle and if it is set, any debug fault is ignored during the instruction cycle. The RF is automatically reset after successful execution of every instruction, except for IRET and POPF instructions. • Also, it is not automatically cleared after the successful execution of JMP, CALL and INT instruction causing a task switch. These instruction are used to set the RF to the value specified by the memory data available at the stack. Next page
- 12. Segment Descriptor Registers: – This registers are not available for programmers, rather they are internally used to store the descriptor information, like attributes, limit and base addresses of segments. – The six segment registers have corresponding six 73 bit descriptor registers. – Each of them contains 32 bit base address, 32 bit base limit and 9 bit attributes. – These are automatically loaded when the corresponding segments are loaded with selectors. Next page
- 13. • System Address Registers: Four special registers are defined to refer to the descriptor tables supported by 80386. • The 80386 supports four types of descriptor table: – global descriptor table Register (GDTR), – interrupt descriptor table Register(IDTR), – local descriptor table Register(LDTR) and – task state segment descriptor Register (TSSR).
- 14. GDTR There can be at most 8K local and 8K global descriptor per task total=16K(214) Each selector can address a segment of size 64K Thus total virtual memory is 64K*16K =(230)= 1GB for 80286 4GB segment size in 80386 What will be maximum virtual memory for 80386?
- 15. LDTR Unlike 6 bytes of GDTR contains base address and limits LDTR contains only 16-bit selector number that points to an LDT descriptors in GDT Whenever the selector is loaded in to LDTR the corresponding descriptor is read from GDT ad loadled in to LDT invisible or cache register The 32- bit base address in LDTR identifies the starting address of LDT in physical memory and 16-bit limit determines the size of LDT Every time new selector is is loaded into LDTR,a local descriptors table descriptor is cached and new LDT is activated
- 17. Interrupt Descriptor Table IDT is used to store interrupt gates and trap gates, task gates IDT has 24-bit base address and 16-bit limit register in the CPU (in 80286) 32-bit base address in 80386 LIDT instruction is used to Load Interrupt Descriptor table. IDT able to handle up to 256 interrupt So that total number of descriptor=256 Each descriptor is of 8 bytes So, maximum number of location required for IDT=256*8=2048 = 2K 09/15/14 28
- 19. • Control Registers: The 80386 has three 32 bit control registers CR0, CR2 and CR3 to hold global machine status independent of the executed task. Load and store instructions are available to access these registers. • Lower 16-bits in CR0 is present in the 80286 called as MSW • Debug and Test Registers: Intel has provide a set of 8 debug registers for hardware debugging. Out of these eight registers DR0 to DR7, two registers DR4 and DR5 are Intel reserved. • The initial four registers DR0 to DR3 store four program controllable breakpoints addresses, while DR6 and DR7 respectively hold break point status and break-point control information. • Two more test register are provided by 80386 for page caching namely test control and test status register.
- 20. Real Address Mode of 80386 • After reset, the 80386 starts from memory location FFFFFFF0H under the real address mode. In the real mode, 80386 works as a fast 8086 with 32-bit registers and data types. • In real mode, the default operand size is 16 bit but 32- bit operands and addressing modes may be used with the help of override prefixes. • The segment size in real mode is 64k, hence the 32-bit effective addressing must be less than 0000FFFFFH. The real mode initializes the 80386 and prepares it for protected mode. Next page
- 21. Next page OFFSET c c c c c SEGMENT SELECTOR 0000 MEMORY OPERAND SEGMENT BASE MAX LIMIT FIXED AT 64 K IN REAL MODE 64 K BYTES 0 19 0 15 SELECTED SEGMENT Physical Address Formation In Real Mode Of 80386 +
- 22. • Memory Addressing in Real Mode: In the real mode, the 80386 can address at the most 1Mbytes of physical memory using address lines A0-A19. • Paging unit is disabled in real addressing mode, and hence the real addresses are the same as the physical addresses. • The segment in 80386 real mode can be read, write or executed, i.e. no protection is available. • Any fetch or access past the end of the segment limit generate exception 13 in real address mode. • The segments in 80386 real mode may be overlapped or non- overlapped. • The interrupt vector table of 80386 has been allocated 1Kbyte space starting from 00000H to 003FFH.
- 23. Protected Mode of 80386 • All the capabilities of 80386 are available for utilization in its protected mode of operation. • The 80386 in protected mode support all the software written for 80286 and 8086 to be executed under the control of memory management and protection abilities of 80386. • The protected mode allows the use of additional instruction, addressing modes and capabilities of 80386. • ADDRESSING IN PROTECTED MODE: In this mode, the contents of segment registers are used as selectors to address descriptors which contain the segment limit, base address and access rights byte of the segment. Next page
- 24. c c c c SELECTOR OFFSET MEMORY OPERAND SEGMENT BASE ADDRESS SEGMENT LIMIT UP TO 4 GB SELECTED SEGMENT Protected Mode Addressing Without Paging Unit 48/32–BIT POINTER c c 0 31 / 15 47 / 31 SELECTOR OFFSET ACCESS RIGHT LIMIT BASE ADDRESS SEGMENT DESCRIPTOR +
- 25. • The effective address (offset) is added with segment base address to calculate linear address. This linear address is further used as physical address, if the paging unit is disabled, otherwise the paging unit converts the linear address into physical address. • The paging unit is a memory management unit enabled only in protected mode. The paging mechanism allows handling of large segments of memory in terms of pages of 4Kbyte size. • The paging unit operates under the control of segmentation unit. The paging unit if enabled converts linear addresses into physical address, in protected mode.
- 26. Segmentation • DESCRIPTOR TABLES: These descriptor tables and registers are manipulated by the operating system to ensure the correct operation of the processor, and hence the correct execution of the program. • Three types of the 80386 descriptor tables are listed as follows: • GLOBAL DESCRIPTOR TABLE ( GDT ) • LOCAL DESCRIPTOR TABLE ( LDT ) • INTERRUPT DESCRIPTOR TABLE ( IDT ) Next page
- 27. Segmentation • DESCRIPTOR TABLES: These descriptor tables and registers are manipulated by the operating system to ensure the correct operation of the processor, and hence the correct execution of the program. • Three types of the 80386 descriptor tables are listed as follows: • GLOBAL DESCRIPTOR TABLE ( GDT ) • LOCAL DESCRIPTOR TABLE ( LDT ) • INTERRUPT DESCRIPTOR TABLE ( IDT ) Next page
- 28. • DESCRIPTORS: The 80386 descriptors have a 20-bit segment limit and 32-bit segment address. The descriptor of 80386 are 8-byte quantities access right or attribute bits along with the base and limit of the segments. • Descriptor Attribute Bits: The A (accessed) attributed bit indicates whether the segment has been accessed by the CPU or not. • The TYPE field decides the descriptor type and hence the segment type. • The S bit decides whether it is a system descriptor (S=0) or code/data segment descriptor ( S=1). Next page
- 32. Paging • PAGING OPERATION: Paging is one of the memory management techniques used for virtual memory multitasking operating system. • The segmentation scheme may divide the physical memory into a variable size segments but the paging divides the memory into a fixed size pages. • The segments are supposed to be the logical segments of the program, but the pages do not have any logical relation with the program. • The pages are just fixed size portions of the program module or data. Next page
- 33. Paging • PAGING OPERATION: Paging is one of the memory management techniques used for virtual memory multitasking operating system. • The segmentation scheme may divide the physical memory into a variable size segments but the paging divides the memory into a fixed size pages. • The segments are supposed to be the logical segments of the program, but the pages do not have any logical relation with the program. • The pages are just fixed size portions of the program module or data. Next page
- 34. • The advantage of paging scheme is that the complete segment of a task need not be in the physical memory at any time. • Only a few pages of the segments, which are required currently for the execution need to be available in the physical memory. Thus the memory requirement of the task is substantially reduced, relinquishing the available memory for other tasks. • Whenever the other pages of task are required for execution, they may be fetched from the secondary storage. • The previous page which are executed, need not be available in the memory, and hence the space occupied by them may be relinquished for other tasks. Next page
- 35. • Thus paging mechanism provides an effective technique to manage the physical memory for multitasking systems. • Paging Unit: The paging unit of 80386 uses a two level table mechanism to convert a linear address provided by segmentation unit into physical addresses. • The paging unit converts the complete map of a task into pages, each of size 4K. The task is further handled in terms of its page, rather than segments. • The paging unit handles every task in terms of three components namely page directory, page tables and page itself. Next page
- 36. • Paging Descriptor Base Register: The control register CR2 is used to store the 32-bit linear address at which the previous page fault was detected. • The CR3 is used as page directory physical base address register, to store the physical starting address of the page directory. • The lower 12 bit of the CR3 are always zero to ensure the page size aligned directory. A move operation to CR3 automatically loads the page table entry caches and a task switch operation, to load CR0 suitably. Next page
- 37. • Page Directory : This is at the most 4Kbytes in size. Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a directory. • The upper 10 bits of the linear address are used as an index to the corresponding page directory entry. The page directory entries point to page tables. • Page Tables: Each page table is of 4Kbytes in size and many contain a maximum of 1024 entries. The page table entries contain the starting address of the page and the statistical information about the page. Next page
- 38. Next page P R - W U - S OS RESERVED PAGE TABLE ADDRESS 31….12 A 0 0 0 0 D P R - W U - S OS RESERVED PAGE FRAME ADDRESS 31… .12 A 0 0 0 0 D PAGE DIRECTORY ENTRY PAGE TABLE ENTRY
- 39. Next page U - S R - W PERMITTED FOR LEVEL3 PERMITTED FOR LEVEL2 ,1 OR 0 0 0 1 1 0 1 0 1 NONE READ ONLY READ - WRITE READ / WRITE NONE READ / WRITE READ / WRITE READ / WRITE
- 40. • The upper 20 bit page frame address is combined with the lower 12 bit of the linear address. The address bits A12- A21 are used to select the 1024 page table entries. The page table can be shared between the tasks. • The P bit of the above entries indicate, if the entry can be used in address translation. • If P=1, the entry can be used in address translation, otherwise it cannot be used. • The P bit of the currently executed page is always high. • The accessed bit A is set by 80386 before any access to the page. If A=1, the page is accessed, else unaccessed. Next page
- 41. Next page + + + USER MEMORY PAGE TABLE DIRECTORY CONTROL REGISTERS OFFSET TABLE DIRECTORY INSIDE 80386 IN THE MEMORY 0 31 0 12 22 31 0 31 12 10 10 DBA Physical directory base address DBA CR 0 CR1 CR 3 CR 2 0 31
- 42. • The D bit ( Dirty bit) is set before a write operation to the page is carried out. The D-bit is undefined for page director entries. • The OS reserved bits are defined by the operating system software. • The User / Supervisor (U/S) bit and read/write bit are used to provide protection. These bits are decoded to provide protection under the 4 level protection model. • The level 0 is supposed to have the highest privilege, while the level 3 is supposed to have the least privilege. • This protection provide by the paging unit is transparent to the segmentation unit.
- 43. Virtual 8086 Mode • In its protected mode of operation, 80386DX provides a virtual 8086 operating environment to execute the 8086 programs. • The real mode can also used to execute the 8086 programs along with the capabilities of 80386, like protection and a few additional instructions. • Once the 80386 enters the protected mode from the real mode, it cannot return back to the real mode without a reset operation. • Thus, the virtual 8086 mode of operation of 80386, offers an advantage of executing 8086 programs while in protected mode. Next page
- 44. • The address forming mechanism in virtual 8086 mode is exactly identical with that of 8086 real mode. • In virtual mode, 8086 can address 1Mbytes of physical memory that may be anywhere in the 4Gbytes address space of the protected mode of 80386. • Like 80386 real mode, the addresses in virtual 8086 mode lie within 1Mbytes of memory. • In virtual mode, the paging mechanism and protection capabilities are available at the service of the programmers. • The 80386 supports multiprogramming, hence more than one programmer may be use the CPU at a time. Next page
- 45. Next page AVAILABLE PHYSICAL MEMORY 020000000 H ` Memory Management In Virtual 8086 Mode 000000000 H PAGE N 8086 OS EMPTY TASK 2PAGE TABLE VIRTUAL MODE 8086 TASK PAGE DIRECTOR TASK 2 PAGE N PAGE 1 8086 OS PAGE DIRECTORY ROOT EMPTY TASK 1PAGE TABLE PAGE DIRECTORY TASK 1 VIRTUAL MODE 8086 TASK TASK 1 MEMORY 8086 OS MEMORY TASK 1 MEMORY TASK 2 MEMORY TASK 2 MEMORY TASK 1 MEMORY 386 DX CPU OS MEMORY TASK 2 MEMORY
- 46. • Paging unit may not be necessarily enable in virtual mode, but may be needed to run the 8086 programs which require more than 1Mbyts of memory for memory management function. • In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size. • Each of the pages may be located anywhere in the maximum 4Gbytes physical memory. The virtual mode allows the multiprogramming of 8086 applications. • The virtual 8086 mode executes all the programs at privilege level 3.Any of the other programmes may deny access to the virtual mode programs or data. Next page
- 47. • However, the real mode programs are executed at the highest privilege level, i.e. level 0. • The virtual mode may be entered using an IRET instruction at CPL=0 or a task switch at any CPL, executing any task whose TSS is having a flag image with VM flag set to 1. • The IRET instruction may be used to set the VM flag and consequently enter the virtual mode. • The PUSHF and POPF instructions are unable to read or set the VM bit, as they do not access it. • Even in the virtual mode, all the interrupts and exceptions are handled by the protected mode interrupt handler. Next page
- 48. • To return to the protected mode from the virtual mode, any interrupt or execution may be used. • As a part of interrupt service routine, the VM bit may be reset to zero to pull back the 80386 into protected mode.
- 49. Features of 80386 • This 80386 is a 32bit processor that supports, 8bit/32bit data operands. • The 80386 instruction set is upward compatible with all its predecessors. • The 80386 can run 8086 applications under protected mode in its virtual 8086 mode of operation. • With the 32 bit address bus, the 80386 can address upto 4Gbytes of physical memory. The physical memory is organised in terms of segments of 4Gbytes at maximum. • The 80386 CPU supports 16K number of segments and thus the total virtual space of 4Gbytes * 16K = 64 Terrabytes. Next page
- 50. • The memory management section of 80386 supports the virtual memory, paging and four levels of protection, maintaining full compatibility with 80286. • The 80386 offers a set of 8 debug registers DR0-DR7 for hardware debugging and control. The 80386 has on-chip address translation cache. • The concept of paging is introduced in 80386 that enables it to organise the available physical memory in terms of pages of size 4Kbytes each, under the segmented memory. • The 80386 can be supported by 80387 for mathematical data processing.