8086 microprocessor introduction
Download as PPT, PDF6 likes2,660 views
The document discusses the architecture and features of the 8086 microprocessor. It describes the various components of the 8086 including the Bus Interface Unit (BIU) which handles communication with external memory and I/O devices, the segment registers, instruction pointer, address generation circuit, and execution unit. It also covers the flag register, memory segmentation using segments and offsets, and memory banking using the BHE and A0 pins.
8086 microprocessor introduction
- 1. BY: AKASH UGALE 8086 Microprocessor
- 2. Important Features Of 8086 Buses:-Address ,Data ,Control 8086 supports Pipelining. 8086 has 2 Operating Modes. 8086 provides Memory Banks. 8086 supports Memory Segmentation. 8086 supports 256 interrupts. 8086 has 16-bit IO address.
- 4. Bus Interface Unit(BIU) Provide interface of 8086 to external memory & IO devices. Operates w.r.t Bus cycle It generates 20-bit physical address. Fetches Instruction from memory. Transfer data to or from the memory and IO. Supports Pipelining using the 6-byte instruction queue.
- 5. Segment Registers CS Register DS Register SS Register ES Register
- 6. Instruction Pointer It is a 16-bit register. It holds offset of the next instruction in the code segment. Address of the next instruction is calculated as CS * 10H+IP. IP is incremented after every instruction byte is fetched. IP gets a new value whenever a branch occurs.
- 7. Address Generation Circuit BIU has Physical Address Generation Circuit. It generates 20-bit Physical address using the formula: PA=Segment Address*10H + Offset AddressPA=Segment Address*10H + Offset Address Eg:- Segment Address:-1234H(0001 0010 0011 0100) Offset Address:-0005H(0000 0000 000 0101) PA=1234*10H+0005=12345H =0001 0010 0011 0100 0000 +0001 0010 0011 0101 = 0001 0010 0011 0100 0101 =12345H
- 8. 6-Byte Pre-Fetch Queue It is a 6-byte FIFO RAM use to implement Pipelining. BIU Fetches the next “six instruction-bytes” from CS and store it in Queue. EU removes instruction from the queue and execute them. Queue is refilled atleast 2 byte are empty. As soon as 8086 detects a branch operation ,it clears/discard the entire queue.
- 9. Execution Unit(EU) It fetches instruction from the queue in BIU,decodes and execute them. It performs Arithmatic,logic and internal data transfer operation within the mup. It sends Signal to the BIU to access the external module. It operates w.r.t.T-States.
- 10. Execution Unit Contd……. General Purpose Registers:-AX,BX,CX,DX Special Purpose Registers:-SP,BP,SI,DI ALU Operand Register Instruction Register and Instruction Decoder
- 11. Flag Register(16-Bits) It has 9 flags. These flags of two types : 6-satus (condition) flags and 3-control flags. Status Flags:-OF,SF,ZF,AF,PF,CF Control Flags:-DF,IF,TF X X X X OF DF IF TF SF ZF X AF X PF X CF
- 12. Memory Segmentation Dividing the memory into logically different parts called segments. 20-bit Address bus hence total 1MB memory. 4 Segments:-CS,DS,SS,ES Max size of segment 64KB. 8086 can access only 4 segment at time. Four 16-bit register to hold base address. Four 16-bit register to hold offset address.
- 13. Memory Segmentation Contd….. Advantages of Segmentation: It permits the programmer to access 1mb using only 16-bit address. Its divides the memory logically to store instruction,data and stack separately. Segmentation is very useful for multiuser environment Disadvantages of Segmentation: Although the total memory is 16*64KB ,at time only 4*64KB memory can be accessed.
- 14. Memory Banking Odd bank Even bank Also called as “higher bank” Also called as “lower bank” Address range: Address range: 0001H 0000H 0003H 0002H 0005H 0006H . . . . FFFFH FFFEH Selected when BHE=0 Selected when A0=0 512KB 512KB 1MB
- 15. Memory Banking Contd…. BHE A0 Operation 0 0 R/W 16-bit from both banks 0 1 R/W 8-bit from higher bank 1 0 R/W 8-bit from lower bank 1 1 No Operation(Idle)