ICECS-08

This document discusses a phase locked loop (PLL) circuit that can recover a clock signal from USB data without using a crystal oscillator as a reference. It begins by outlining the USB specification and challenges of clock recovery from USB data. It then introduces an adaptive PLL architecture that can control its loop bandwidth to enhance locking performance. The circuit implementation is described, using a Hogge phase detector to extract the clock signal from the non-return-to-zero (NRZI) encoded USB data. Simulation results show the circuit can recover the 48MHz clock within 10 seconds, meeting USB specifications.