A low quiescent current low dropout voltage regulator with self-compensation

Bulletin of Electrical Engineering and Informatics
Vol. 8, No. 1, March 2019, pp. 65~73
ISSN: 2302-9285, DOI: 10.11591/eei.v8i1.1385  65
Journal homepage: http://beei.org/index.php/EEI
A low quiescent current low dropout voltage regulator with
self-compensation
Chu-Liang Lee1
, Roslina Mohd Sidek2
, Nasri Sulaiman3
, Fakhrul Zaman Rokhani4
1
Multimedia University, Jalan Multimedia, 61300 Cyberjaya, Selangor, Malaysia
1,2.3,4
University Putra Malaysia, 43400 UPM Serdang, Selangor, Malaysia
Article Info ABSTRACT
Article history:
Received Oct 24, 2018
Revised Nov 30, 2018
Accepted Dec 28, 2018
This paper proposed a low quiescent current low-dropout voltage regulator
(LDO) with self-compensation loop stability. This LDO is designed for
Silicon-on-Chip (SoC) application without off-chip compensation capacitor.
Worst case loop stability phenomenon happen when LDO output load current
(Iload) is zero. The second pole frequency decreased tremendously towards
unity-gain frequency (UGF) and compromise loop stability. To prevent this,
additional current is needed to keep the output in low impedance in order to
maintain second pole frequency. As Iload slowly increases, the unneeded
additional current can be further reduced. This paper presents a circuit which
performed self-reduction on this current by sensing the Iload. On top of that, a
self-compensation circuit technique is proposed where loop stability is self-
attained when Iload reduced below 100μA. In this technique, unity-gain
frequency (UGF) will be decreaed and move away from second pole in order
to attain loop stability. The decreased of UGF is done by reducing the total
gain while maintaining the dominant pole frequency. This technique has also
further reduced the total quiescent current and improved the LDO’s
efficiency. The proposed LDO exhibits low quiescent current 9.4μA and
17.7μA, at Iload zero and full load 100mA respectively. The supply voltage
for this LDO is 1.2V with 200mV drop-out voltage. The design is validated
using 0.13μm CMOS process technology.
Keywords:
LDO
Low dropout regulator
Quiescent current
Self-compensation
Copyright © 2019 Institute of Advanced Engineering and Science.
All rights reserved.
Corresponding Author:
Chu-Liang Lee,
Faculty of Engineering,
Multimedia University,
Jalan Multimedia, 61300, Cyberjaya, Selangor, Malaysia.
Email: cllee@mmu.edu.my
1. INTRODUCTION
In recent years, the technology trend in biomedical engineering have tremendously increased the
market demand for portable, wearable and implantable devices [1-3]. The requirement on complete
functional integration semiconductor chip such as Silicon-on-Chip (SoC) in low power environment has
becoming more important [4]. The advanced in transistor process technology that continuously required for a
lower supply voltage with limited power consumption budget has put circuit designer into formidable
challenges, especially the power management module [5, 6]. Low dropout linear regulator (LDO) is one of
the most important unit in the power management module which has a clean supply but lower power
efficiency compare switching regulator. LDO is suitable to regulate sensitive circuitries such as analog or RF
modules [7]. The requirement of low power SoC had put LDO circuit design into challenge because the high
capacitance external off-chip capacitor which is used for stability compensation had to be removed [8, 9].
Figure 1 shows a conceptual LDO design for SoC application.
There are many reported LDO design to resolve the stability issue of integrated LDO in SoC. Jacob
Day and Donald Y.C.Lie suggested to use NMOS transistor instead of PMOS to implement a source follower

 ISSN: 2302-9285
Bulletin of Electr Eng and Inf, Vol. 8, No. 1, March 2019 : 65 – 73
70
in order to obtain low output impedance at the output of LDO [10]. This method sustain low impedance at
output node and keep this pole at higher frequency. However the trade-off is the higher dropout voltage is
required by NMOS pass transistor, thus lower efficiency is obtained. An additional low-impedance loading
network at output node of LDO has also been suggested [11]. This method is able to maintain a competitive
low dropout voltage using PMOS as output stage and sustain low impedance at the output node. However,
excessive amount of current is needed by this circuit to sustain the output in low impedance. Thus, the higher
quiescent current has resulting a lower efficiency LDO design.
Figure 1. Conceptual LDO design for SoC application
To attain the issue of high quiescent current in LDO, there are research studies had been done, such
as reduced the dropout voltage or reduce the low quiescent current during operation mode [12, 13]. However
not many researches were being done to reduce quiescent current particularly during very small output load
current, which means during its idle state. According to the statistic, electronics devices are under stand-by or
idle mode at most of the time. Analog circuitries particularly LDOs are the major modules that constantly
consuming current even in its idle state in order to keep the power supply working for the rest of the
circuities. Therefore, this compromises the efficiency performance since the stand-by quiescent current
carries a higher weight in efficiency. The efficiency percentage is given by
( )
(1)
where is quiescent current and is the output load current. Therefore reducing quiescent current to
maintain a higher efficiency at very small or zero output load current is deemed to be important. Prior to this,
this paper is focus on reducing the LDO’s quiescent current even during output load current is near to zero, A
method had been suggested by using self-reduction quiescent current circuitry [14]. This circuitry uses
minimum quiescent current during high output loading current in order to obtain a better efficiency. It only
allows adequate amount of additional current to be supplied to attain LDO stability during very low output
load current. An improved version of such circuitry design is proposed in this paper. In this work, a sense and
control circuit with low-impedance circuit is introduced. The circuit enables a self-adjusted minimum
quiescent current to sustain the low output impedance during output load current is very small. At the same
time, a self-compensation method is used to sustain the stability. This self-compensation mechanism has also
contributed to the further reduction of total quiescent current.
2. PROPOSED LDO CIRCUIT DESIGN
2.1. Schematic and circuit implementation
The schematic of the proposed LDO circuit design is shown in Figure 2 and Figure 3. The proposed
circuit is mainly consists of biasing circuit, transconductance amplifier (OTA), pass transistor power PMOS
(MP), low-impedance circuit, sensing and control (SAC) circuit, and feedback network (resistors R1 and R2).
As shown in Figure 2, the biasing circuit is formed by transistor Mb1, Mb2 and resistor Rb that supply bias
current to the rest of the circuitry. The OTA amplifier consists of an input differential amplifier (M1~M5) and

Bulletin of Electr Eng and Inf ISSN: 2302-9285 
A low quiescent current low dropout voltage regulator with self-compensation (Chu-Liang Lee)
71
a gain stage amplifier (M7~M10). Transistor M6 is biased from the SAC circuit to control an auxiliary current
for the differential amplifier. The output of the gain stage forms a push-pull stage to charge and discharge the
gate capacitance of the power PMOS, MP. The gate capacitance of MP is large due to the huge transistor size
of this power PMOS to regulate the tremendous amount of current to the output load circuit. MP output
impedance, is given by (2), where is the channel length modulation.
(2)
Figure 2. Proposed LDO circuit design (op-amp)
As shown in Figure 3, the low-impedance circuit consists of M18~M21. The source of PMOS
transistor, M21 is connected to the output node of the LDO to provide a low impedance node. The total output
impedance at VOUT node, is given by (3), where is the output impedance of M21, and is the
output load resistance. The current from M12 is mirrored to M21 through current mirror M14, M18 and M20.
Transistor M19 is used to keep transistor M20 in vigilant to maintain a fast response if M18 is turn off.
( ) (3)
Figure 3. Proposed LDO circuit design

 ISSN: 2302-9285
70
The sensing and control (SAC) circuit consists of sensing circuit (MPT, Rt1 and Rt2) and a differential
circuit (M11~M15). The size of sensing transistor, MPT is scaled to a ratio of 100 times smaller than MP.
Changes on output load current, that flow through MP will reflected to MPT with 100 times smaller
scale. Voltage level VPT is scaled by the resistor divider Rt1 and Rt2 to be compared with a fixed reference
voltage, Vth. If reduces below , it reflects to VPT, and start the differential mode
comparison operation.
2.2. Stability analysis and circuit operation
Figure 4 shows the open-loop domain configuration of the proposed LDO. It shows total three
amplifier stages, which is the differential amplifier, gain stage, and the power PMOS as the third stage.
Power PMOS is a common-source amplifier. Each stage corresponding transconductance, output impedance
and parasitic capacitance are denoted in the configuration as , , , , , , , ,
and respectively.
Figure 4. Proposed LDO open-loop configuration
The output impedance of the first stage, is small due to the diode-connected active load which
imposed approximately at its output. Therefore first stage gain is small and the pole is located at
higher frequency and doesn’t affect the stability. The second stage has a large output impedance ( ) due to
the active load formed by current mirror circuit. Therefore gain is higher. At this node, large gate
capacitance of power PMOS contributes to a high value , and therefore the dominant pole ( ) is
located at this node. The third stage output impedance, has a wide variation range which depending on
the large output load current, as per (2) and (3). Due to the large MP size, the is high, thus contributes to
high gain . The parasitic capacitance and output load capacitance contribute to second pole ( )
frequency and dependent on variation. A compensation capacitor is connected between the output of
first and third stage, and gate-drain capacitance of MP between second and third stage, are giving a pole
splitting effect for frequency compensation. The low frequency gain ( ), dominant pole ( ) and
second pole ( ) are respectively given by:
(4)
( )
(5)
( ) ( )
(6)
The transfer function, T(s) is given by (7):
T(s)=
( )
( )
≈
(
( )
)
( )( [
( ) ( )
]
( )
( )
(7)

71
The loop stability analysis to be focused in this work is on the worst case scenario where is
below . When falls below 100μA, becomes very large and so does as shown in (2) and
(3). This causes frequency to reduce tremendously moving toward UGF, and compromise the minimum
requirement of phase margin if √ . A solution is proposed to reduce using low-impedance
circuit. From (3), small value from low-impedance circuit dominates instead of . If reduces
below , the sensing circuit will cause VPT to decrease below Vth. M12 will start to draw more current
compare M11. As reduces, more current will be mirrored from M12 to M21 to obtain smaller impedance
value, . Thus prevent from further shifting to lower frequency. If is not low enough to
compromise the loop stability, only adequate amount of current is used to maintain the loop stability. In other
words, self-reduction current is performed when starts to increase from zero. However, at worst case
stability phenomenon where is zero, this current can be high. Instead of using excessive current to
maintain frequency, a self-compensation circuit method is proposed. The total gain is lowered without
influencing in order to shift UGF to lower frequency, away from as shown in Figure 5. This is done
by the SAC circuit with a current feedback. As reduces, VPT decreases, and drain current of M11 starts to
reduce. Lower current is mirrored from M11 to M6, and reduces the first stage gain.
Figure 5. Bode plot for < 100μA
Therefore the total gain has been reduced but location is not affected. In other words, as
reduces, a self-compensation mechanism take effect where the UGF is automatically reduces in order to
obtain a better phase margin. The proposed SAC circuit has not only reduced the excessive at low-
impedance circuit, but at same time, it further reduced the tail current at first stage amplifier. This has
contributed to the reduction of total quiescent current.
3. RESULTS AND DISCUSSION
The proposed LDO in this work has been implemented using CMOS process technology.
The frequency response at high load current is stable with phase margin higher than . This work focuses
on very low output load current phenomenon. The close-loop frequency response of proposed LDO at very
low load current is plotted as shown in Figure 6. When the load current is reduced, the decrement of second

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pole can be seen. It’s due to the self-reduction of additional current at low-impedance circuitry. It shows that
the gain is decreasing when the load current is reduced to zero, and the UGF shifted to lower frequency and
attained loop stability with phase margin higher than . The gain during zero load current doesn’t
compromise the application of LDO since it’s not in regulating mode. Maintaining adequate phase margin to
attain loop stability at zero load current is more important so that a quick response is obtained when the load
current is suddenly required at the LDO output. The resulst also shown an almost linear decrement of UGF
with the reduction of load current from 100μA.
Figure 6. LDO frequency response for very small load current
Figure 7(a) shows the graph of versus , where is the current used to keep output
impedance low during small load current. When increased from zero to , has reduced from
to for VCC=1.20V. This shows the self-reduction mechanism of current used in low-impedance
circuit. Figure 7(b) shows the graph of total quiescent current, versus . When reduces from
, the total quiescent current of LDO has been reduced from to for VCC=1.20V. The total
quiescent current reduction is around 30%.
(a) (b)
Figure 7. (a) (b) , versus of LDO

71
Figure 8 shows the efficiency performance of proposed LDO at load current below 100μA. The
result shows 60% efficiency even at very low load current at 25μA. The efficiency has became almost
constant at 70% and above when load current increased to 50μA.
Figure 8. Efficiency versus Iload
The die picture of the LDO is shown in Figure 9. Table 1 shows the comparison between the recent
reported LDO designs and this work. The reported LDO designs with proximity technology are chosen for
the comparison. This LDO is designed to deliver a maximum load current of 100mA. The proposed lower
power LDO supply voltage is 1.2V and the output voltage is 1.0V with dropout voltage of 200mV. The total
quiescent current is only at zero output load current, and at full output load current .
Figure 9. Die picture of proposed LDO
Table 1. Comparison of published LDO results
Published
LDO
Technology
(μm)
Supply
Voltage (V)
Dropout
Voltage (mV)
Output
voltage
(V)
Max. Load
Current
(mA)
Min.
Load
Current
(μA)
Max.
Quiescent
Current
(μA)
Compensation
Cap, Cc (F)
[11] 0.18 1.2 200 1.0 100 0 53.5 10p
[15] 0.13 >1.313 >113 1.2 70 - 93 external
[14] 0.13 1.2 100 1.1 100 - 27 8p
[16] 0.13 1.2 200 1.0 50 50 37.3 -
This work 0.13 1.2 200 1.0 100 0 17.7 8p
4. CONCLUSION
A low quiescent current LDO with self-compensation has been presented in this work. The proposed
LDO has improved the loop stability and efficiency issues at worst case scenario where output load current
is very low. These techniques are implemented by low-impedance circuit and SAC circuits. The

 ISSN: 2302-9285
70
variation of is sensed and feedback by SAC circuit. Firstly, the current used for keeping output
impedance low is self-reduced as slowly increases from zero. Secondly, a self-compensation method is
introduced for frequency compensation, instead of using excessive current to keep frequency higher. The
current feedback of the SAC circuit has also further reduced quiescent current. The results have shown that
this LDO has achieved the goal of reducing quiescent current by adopting current self-reduction technique.
On top of that, a self-compensation circuit technique on loop stability has also further decreased quiescent
current.The total quiescent current reduction has contributed to a higher efficiency of the LDO at low
load current.
REFERENCES
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implantable neural interface microsystems,” IEEE Trans. Biomed. Circuits Syst., vol. 5, no. 2, pp. 169–178, 2011.
[2] S. Fan, Z. Xue, H. Lu, Y. Song, H. Li, and L. Geng, “Area-Efficient On-Chip DC #x2013;DC Converter With
Multiple-Output for Bio-Medical Applications,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. Early Access
Online, 2014.
[3] T.-T. Zhang, P.-I. Mak, M.-I. Vai, P.-U. Mak, F. Wan, and R. P. Martins, “An ultra-low-power filtering technique
for biomedical applications,” 2011, pp. 1859–1862.
[4] Y. L. Lo and W. J. Chen, “A 0.7 v input output-capacitor-free digitally controlled low-dropout regulator with high
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with MPPT for vibrational energy harvesting,” Proc. - IEEE Int. Symp. Circuits Syst., pp. 6–9, 2017.
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[15] Q. Wu, W. Li, N. Li, and J. Ren, “A 1.2 V 70 mA low drop-out voltage regulator in 0.13 #x00B5;m CMOS
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BIOGRAPHIES OF AUTHORS
Chu-Liang Lee received his B.Sc. degree in Physics (Hon.) and M.Sc. degree in electronic
engineering (majoring microelectronic) from Universiti Putra Malaysia (UPM), Selangor,
Malaysia in 1997 and 2001 respectively. He is currently working toward Ph.D. degree at
Universiti Putra Malaysia, Selangor, Malaysia. From 2001 to 2005, he was an Integrated Circuit
Design Engineer with Malaysia Microelectronic Solutions Sdn. Bhd., where he was involved
with digital IC design from front-end to back-end, mainly for smartcard products. From 2005 to
2006, he switched to analog integrated circuit design with Mycrosem Electronics Sdn. Bhd., a
start-up company which involved fan driver IC using bipolar process. From 2006 to 2008, he
joined BlueChips Technology Bhd. as analog integrated circuit design engineer where he
involved DC/DC converter design using BCD and CMOS process. He was also involved in chip
testing and failure debugging of IC chips. He then joined PHY Semiconductor Sdn. Bhd. and
involved in optical transmitter and receiver design from 2008 to 2009, before joining academic
as a lecturer in Multimedia University, Cyberjaya, Malaysia. His research interests include
digital and analog integrated circuit design.

71
Roslina Mohd Sidek received the B.Sc. degree in Washington DC in 1990, and the M.Sc. and
Ph.D. degree from University of Southampton, United Kingdom in 1993 and 1999 respectively.
She is currently Associate Professor in Department of Electrical and Electronic Engineering,
University Putra Malaysia. She had involved in several industrial collaboration projects, namely
Flash Memory Design with MyMS Sdn Bhd, CMOS ESD Devices project wih Silterra Sdn Bhd,
and GaAs Devices and Circuits with TMRnD. She is also a member of professional affiliation of
MIEEE and MIEM, and registered with BEM. Her areas of expertise is in Semiconductor
Devices and Modelling, Integrated Circuit Fabrication, Integrated Circuit Design and Testing.
Nasri bin Sulaiman is a senior lecturer at the Department of Electrical and Electronic
Engineering, Faculty of Engineering, Universiti Putra Malaysia. He received a bachelor degree
in electronics and computer engineering from the Universiti Putra Malaysia (UPM), Malaysia in
1994 and a master degree in microelectronics system design from the University of
Southampton, United Kingdom in 1999. He also obtained a Ph.D degree in adaptive hardware
from the University of Edinburgh, United Kingdom in 2007. His areas of interest include
evolutionary algorithms, digital signal processing, digital communications and low power
VLSI designs
Fakhrul Zaman Rokhani received the B.S. degree in University of Technology Malaysia, and
the M.S. and Ph.D. degree from the University of Minnesota, USA. He was with Intel Penang
Design Center as visiting professor designing chipset for Intel Core i3/i5/i7 processor on 32nm
Intel process technology, was with Huawei Technologies for CEO coaching program, visiting
scholar at the ASIC & Systems State Key Lab in Fudan University, China, visiting assistant
professor at Al-Neelain University, Sudan, visiting professor at Celal Bayar University, Turkey
and engineer at MIMOS. He serves as an Editor-in-Chief for IEEE CASS (M) newsletter and
associate editor for IEEE CASS society newsletter, past chair for IEEE Consumer Electronics
(M) Chapter, executive committee in the IEEE CASS (M) Chapter and was a Treasurer for the
IEEE GOLD. He serves on the technical program committees and publication chair for many
flagship IEEE conferences.

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