A New Proposal for OFCC-based Instrumentation Amplifier

International Journal of Electrical and Computer Engineering (IJECE)
Vol. 7, No. 1, February 2017, pp. 134~143
ISSN: 2088-8708, DOI: 10.11591/ijece.v7i1.pp134-143  134
Journal homepage: http://iaesjournal.com/online/index.php/IJECE
A New Proposal for OFCC-based Instrumentation Amplifier
Deva Nand, Neeta Pandey
Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India
Article Info ABSTRACT
Article history:
Received Sep 14, 2016
Revised Nov 20, 2016
Accepted Dec 5, 2016
This contribution puts forward a new voltage mode instrumentation amplifier
(VMIA) based on operational floating current conveyor (OFCC). It presents
high impedance at input terminals and provides output at low impedance
making the proposal ideal for voltage mode operation. The proposed VMIA
architecture has two stages - the first stage comprises of two OFCCs to sense
input voltages and coverts the voltage difference to current while the second
stage has single OFCC that converts the current to voltage. In addition it
employs two resistors to provide gain and imposes no condition on the values
of resistors. The behavior of the proposed structure is also analyzed for
OFCC non idealities namely finite transimpedance and tracking error. The
proposal is verified through SPICE simulations using CMOS based
schematic of OFCC. Experimental results, by bread boarding it using
commercially available IC AD844, are also included.
Keyword:
AD844
Common-mode rejection ratio
instrumentation amplifier
Operational floating current-
conveyor
Voltage-mode Copyright © 2017 Institute of Advanced Engineering and Science.
All rights reserved.
Corresponding Author:
Deva Nand,
Department of Electronics and Communication Engineering,
Delhi Technological University,
Shahabad, Bawana Road, Delhi, India.
Email: devkamboj07@gmail.com
1. INTRODUCTION
Design and development of analog signal processing and generating circuits using current mode
(CM) building blocks has been mainstay for past few years. Current conveyor and its variants, being versatile
CM building blocks, have been used extensively for these applications. The operational floating current
conveyor (OFCC) [1] is a variant of current conveyor with attractive features of both high and low
impedance at input and output ports which make it suitable for sensing both currents and voltage and
providing the sensed variable in form of current and voltage. The OFCC has been used to develop variable
gain amplifier [1], basic amplifier circuits (voltage, current, transimpedance and transconductance) [2-4],
filters [5-10], instrumentation amplifier [11], [12], readout circuits [13], logarithmic amplifier [14],
rectifier [15], and wheatstone bridge [16] in recent past.
This papers aims at presenting an instrumentation amplifier (IA) which is inevitably used in areas
pertaining to industrial process control [17], automotive transducers [18], bio-potential acquisition
systems [19-20] and linear position sensing [21], to suppress unwanted common mode noise and to amplify
differential signals. In general, the IA structures are classified according to the active block used for
realization or on the basis of type of input/output it processes/provides. Taking the later classification into
consideration, the available IA may be viewed as voltage mode IA (VMIA), current mode IA (CMIA),
transimpedance mode IA (TIMIA) and transadmittance mode IA (TAMIA). The available VMIAs [11], [12],
[22-41] employ various active blocks and are compared on the basis of number and type of active block,
numbers of resistors/capacitors, input and output impedance, as shown in Table 1.
The findings are placed in Table 1 and following points are noted:
a. The structures presented in [30], [31] use large number of active blocks while those reported in
[12 Figure 4(a)], [22-24], [27], [39] employ many passive components.

IJECE ISSN: 2088-8708 
A New Proposal for OFCC-based Instrumentation Amplifier (Deva Nand)
135
b. The input impedance of all VMIAs is high while the output impedance of [11], [32-36], [38-41] is not
appropriate therefore an additional active block would be needed to access the output.
c. Though the active block count is less than or equal to three in [32-35], [38-41], but an additional active
block is needed to access output.
d. The VMIA [12 Figure 5(a)] uses three number of active blocks and resistors each and presents output at
proper impedance level.
e. Both VM and CM active blocks are employed in [29-31], [36], [37] therefore the bandwidth is governed
by VM block.
f. Component matching is needed in [12], [22-24], [27-31] for proper operation.
Table 1. Characteristics of Available VMIA Circuits
* current mirrors, ** current subtractor
It can be inferred from above discussion that the VMIA reported in [12 Figure 5(a)] uses least
component count but requires component matching. The main motivation of this work is to present OFCC
based VMIA that uses same active block count as [12 Figure 5(a)] and only two resistors without matching
constraint.
The paper is detailed in four Sections. Section 2 describes OFCC port relationship and proposed
OFCC based VMIA topology. This Section also includes the behavior of proposed topology in presence of
non-idealities namely finite transimpedance gain and tracking errors. The verification of theoretical
predictions is done both through simulations and experimentation. The corresponding results are put forward
in Section 3. The findings of the paper are concluded in Section 4.
2. PROPOSED OFCC BASED VMIA
2.1. Operational Floating Current Conveyor (OFCC)
The OFCC has two inputs and two outputs and is represented by circuit symbol shown in Figure 1.
The input ports Y and X (W and Z) is used respectively for sensing (providing) voltage and currents. The
ports X and W have low impedance whereas ports Y and Z present high impedance.
Ref. No. Active Block Used
Resistors/
CapacitorsUsed
Input
impedance
Output
impedance
[11] 2 OFCC 4 High High
[12 Figure 4(a)] 4OFCC 10 High Low
[12 Figure 5(a)] 3OFCC 3 High Low
[22]
[22]
[22]
2 opamps
3 opamps
4 opamps
5
7
6
High
High
High
Low
Low
Low
[23] 3 opamps 7 High Low
[29] 2 CCII+, 1 opamp 3 High Low
[30] 6CCII+, 1opamp 3 High Low
[31] 6CCII+, 1opamp 3, 1 capacitor High Low
[32] 2 CCII+ 3 High High
[36] 2CC, 2opamps 2 High High
[37] 3 opamps, 2 cm*, 1 cs** 2, 1 capacitor High Low
[38] 3 CCCII Nil High High
[39] 2 OC 6 High High
[40] 2CCCII 1 active resistor High High
[41] 2CCII 2 High High

 ISSN: 2088-8708
IJECE Vol. 7, No. 1, February 2017 : 134 – 143
136
Figure 1. Electrical symbol of the OFCC
The OFCC operation is based on the port relationship of (1):
[ ] [ ] [ ] (1)
Here, the term Zt represents open loop transimpedance and its value is very high, therefore feedback
between W and X port is essential for developing any application. The frequency dependence of parameter Zt
in (1) is represented using single pole model and is approximated as Zt (s) = 1/sCp at high frequencies where
Cp = Ztoωtc (Zto represents open loop transimpedance gain and ωtc corresponds to its cut off frequency). The
voltage and current transfers at X and Z ports have a multiplication factor of α and β. Ideal values of these
factors are unity, however, in practice there is deviation from this value. The effect of non-ideal voltage and
current transfers on circuit operation depends strongly on topology e. g. the performance of the circuit
remains unaffected if the terminals whose behaviour is affected by non – ideal behaviour are not used in case
of current terminal or corresponding voltage port is grounded.
2.2. Proposed Topology
The architecture of the proposed VMIA, as depicted in Figure 2, comprises of two stages. The first
stage, comprises of two OFCCs and a current determining resistor R1, provides current proportional to input
voltage difference (Vin1 - Vin2). A single OFCC (OFCC3) and a resistor are used in second stage which
converts the current output of first stage to voltage.
Figure 2. Proposed Instrumentation Amplifier

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137
Using the port relationships of (1), voltages at nodes P and Q in Figure 2 are computed as
(2)
(3)
which give current output (Iout) of the first stage as
( )
( ) (4)
where ( ) .
The third OFCC coverts Iout to output voltage (Vout). Routine analysis of the circuit gives Vout as
( ) ( ) (5)
where ( ) .
Substituting Iout in Equation (5) yields
( ) ( ) ( ) (6)
Representing Vin1 = VCM + Δ and Vin2 = VCM – Δ, differential mode gain (Ad) and common mode
gain (ACM) are computed respectively as:
( ) ( ) ( )
( )
( )( )
(7)
( ) ( ) ( )
( )
( )( )
(8)
It is clear from Equation (8) that if the OFCCs are matched, the current output (Iout) would be zero
for common mode input and would result in zero output voltage. There will be deviation from zero output if
the OFCCs at input stage are not matched which are discussed in the following Section. Using Eqs. (7) and
(8), the common mode rejection ratio (CMRR) is calculated as
( )
( )
(9)
In practice, the values of β1 and β2 are close to unity, therefore the proposed topology can give a
high value of CMRR. Considering α = 1, β1 =β2 =1 and frequencies much below ( ( ) ( )),
Equation (7) reduces to
(10)
It is clear from Equation (10) that no matching constraint is imposed on component values for
obtaining differential gain. Comparing the proposed VMIA with available OFCC based VMIAs
[12 Figure 5(a)] having similar input and output impedances, it is found that later uses equal resistors in first
stage.
3. SIMULATION AND EXPERIMENTAL RESULTS
The proposal is examined through SPICE simulations wherein CMOS based schematic of OFCC of
Figure 3 [1] is used. Model parameters of 0.5 µm technology from MOSIS (AGILENT) are used. The
dimensions of various MOS transistors are given in Table 2. The supply voltages is taken as
VDD = -VSS = 1.5V while the bias voltages of VB1 = -VB2 = 0.8V are considered. The passive components
values are taken as R1 = 1 kΩ and R2 as 5 kΩ, 10 kΩ, 15 kΩ and 20 kΩ to obtain gain values of 14 dB,
20 dB, 23.5 dB and 26 dB respectively.

 ISSN: 2088-8708
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Figure 3. Internal Structure of OFCC [1]
Table 2 MOS transistors Dimensions of the OFCC Structure shown in Figure 3 [1]
5.2/10013,9
5.2/408,6
5.2/2015,10,7,5
5.2/5014,12,11,4,3
1/502,1
)(/)(
MM
MM
MMMM
MMMMM
MM
mLmWTransistorMOS 
Figure 4. Gains of Proposed Topology with respect to Frequency
Figure 5. CMRRs of Proposed Topology with respect to Frequency

IJECE ISSN: 2088-8708 
139
Figure 6. Noise Analysis of Proposed Topology with respect to Frequency
For validation of simulated observations the proposal is prototyped. The OFCC is realized with
commercially available IC AD844AN [42] using the setup shown in Figure 7. Experimental observations are
plotted for frequency response and CMRR as shown in Figure 8(a) and Figure 8(b) respectively. Output
signal obtained through prototype for input signal at frequency of 100 kHz and 1 MHz is shown in
Figure 9(a) and Figure 9(b) respectively for authentication. Figure 10(a) shows practical performance for
sinusoidal, Figure 10(b) for square and Figure 10(c) for triangular input signals at frequency of 100 kHz each
as a proof of the proposal.
Various performance parameters such as CMRR, its bandwidth and CMRR gain bandwidth product
(GBP), are compared for available references along with proposed topology parameters and are listed in
Table 3. As the IAs given in [11], [12], [22-41] and the proposed one have been tested for different
differential gains and at different power supply voltages, it is not fair to compare these on the basis of gain
and power consumption.
It is found that proposed VMIA outperforms in terms of both CMRR and its CMRR gain bandwidth
product (GBP) as compared to OFCC based VM IA reported in [12 Figure 5 (a)]. As the data for CMRR
bandwidth is not available for [22-26], [29-32], [34], [37], [39-41], the comparison of CMRR GBP for the
proposed topology is best among all.
Figure 7. Realization of OFCC using AD844AN

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(a) Frequency Response (b) CMRR
Figure 8. Simulated and Experimental Results. (a) Frequency Response and (b) CMRR
(a) (b)
Figure 9. Outputs (1.04 V each) Observed for Input (200 mV each) of (a) 100 kHz and (b) 1 MHz Frequency
Table 3. Performance Parameters of Available and Proposed IA Circuits
NA: Not available
Ref. No. Mode CMRR (dB)
- 3dB frequency
(CMRR)
Power Supply
(Volts)
Experimental Results
available
[11] VM 76 185 kHz NA Yes
[12 Figure 4(a)] VM 81 148 kHz ±1.5 NA
[12 Figure 5(a)] VM 56 525 kHz ±1.5 NA
[22] VM 70-90 NA NA NA
[23] VM NA NA NA Yes
[24] VM NA NA NA NA
[25] VM 80 NA NA Yes
[26] VM >70 at 100 kHz NA NA Yes
[27] VM 62 65 kHz 3.3 (single) NA
[28] VM > 60 Upto 200 kHz NA NA
[30] VM 145 NA ±1.5 NA
[31] VM 149 NA ±1.5 NA
[34] VM >70 at100 kHz NA NA NA
[37] VM 130 NA ±2.5 Yes
[38] VM 147 35 kHz ±2.5 NA
[40] VM 142 NA ±3.3 NA
[41] VM NA NA NA Yes
Proposed VM 93.11 423.69 kHz ±1.5 Yes

IJECE ISSN: 2088-8708 
141
(a) Sinusoidal
Ch1:
Vout = 1.04 V (p-p), 100 kHz
R1 = 1kΩ, R2 = 5kΩ (gain = 14 dB).
Ch2:
Vin = 200 mV (p-p), 100 kHz
Sinusoidal
(b) Square
Ch1:
Vout = 1.04 V (p-p), 100 kHz
R1 = 1kΩ, R2 = 5kΩ (gain = 14 dB).
Ch2:
Vin = 200 mV (p-p), 100 kHz
Square
(c) Triangle
Ch1:
Vout = 1.04 V (p-p), 100 KHz
R1 = 1kΩ, R2 = 5kΩ (gain = 14 dB).
Ch2:
Vin = 200 mV (p-p), 100 kHz
Triangle
Figure 10. Experimental Results of the Proposed IA for (a) Sinusoidal (b) Square (c) Triangular Input
4. CONCLUSION
An OFCC based VMIA is proposed in this work that uses three OFCCs and two resistors. The input
and output impedances of the proposal are high and low respectively therefore the structure can be used to
sense signal from voltage sensor and interface output with system processing voltage signal. Effect of non
idealities on behavior of proposal is included. Workability of the proposal is verified through SPICE
simulations and experimentations. Comparison of the proposed VMIA with its available counterparts shows
that it has highest CMRR GBP and has lowest component count.
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BIOGRAPHIES OF AUTHORS
Deva Nand was born in 1982. He did his B.Tech in Electronics and Communication
Engineering, M.Tech in Microelectronics and VLSI Design from Kurukshetra University,
Kurukshetra, India and he is pursuing Ph.D. from Delhi Technological University, Delhi, India.
At present he is Assistant Professor in Department of Electronics and Communication
Engineering, Delhi Technological University, Delhi, India. A life member of ISTE, and member
of IEEE, USA. His research interests include Analog Mixed Signal VLSI Design.
Neeta Pandey was born in 1966. She did her M. E. in Microelectronics from Birla Institute of
Technology and Sciences, Pilani and Ph. D. from Guru Gobind Singh Indraprastha University
Delhi. She has served in Central Electronics Engineering Research Institute, Pilani, Indian
Institute of Technology, Delhi, Priyadarshini College of Computer Science, Noida and Bharati
Vidyapeeth’s College of Engineering, Delhi in Various capacities. At present, she is Assistant
Professor in ECE department, Delhi Technological University. A life member of ISTE, and
member of IEEE, USA. She has published papers in International, National Journals of repute
and conferences. Her research interests are Analog and Digital VLSI Design.

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