advanced_VLSIRajaram CMOS Characteristics.ppt
- 1. Courtesy : Prof Andrew Mason CMOS Inverter: DC Analysis By Dr.S.Rajaram, Thiagarajar College of Engineering
- 2. Courtesy : Prof Andrew Mason CMOS Inverter: DC Analysis • Analyze DC Characteristics of CMOS Gates by studying an Inverter • DC Analysis – DC value of a signal in static conditions • DC Analysis of CMOS Inverter – Vin, input voltage – Vout, output voltage – single power supply, VDD – Ground reference – find Vout = f(Vin) • Voltage Transfer Characteristic (VTC) – plot of Vout as a function of Vin – vary Vin from 0 to VDD – find Vout at each value of Vin
- 3. Courtesy : Prof Andrew Mason Inverter Voltage Transfer Characteristics • Output High Voltage, VOH – maximum output voltage • occurs when input is low (Vin = 0V) • pMOS is ON, nMOS is OFF • pMOS pulls Vout to VDD – VOH = VDD • Output Low Voltage, VOL – minimum output voltage • occurs when input is high (Vin = VDD) • pMOS is OFF, nMOS is ON • nMOS pulls Vout to Ground – VOL = 0 V • Logic Swing – Max swing of output signal • VL = VOH - VOL • VL = VDD
- 4. Courtesy : Prof Andrew Mason Inverter Voltage Transfer Characteristics • Gate Voltage, f(Vin) – VGSn=Vin, VSGp=VDD-Vin • Transition Region (between VOH and VOL) – Vin low • Vin < Vtn – Mn in Cutoff, OFF – Mp in Triode, Vout pulled to VDD • Vin > Vtn < ~Vout – Mn in Saturation, strong current – Mp in Triode, VSG & current reducing – Vout decreases via current through Mn – Vin = Vout (mid point) ≈ ½ VDD – Mn and Mp both in Saturation – maximum current at Vin = Vout – Vin high • Vin > ~Vout, Vin < VDD - |Vtp| – Mn in Triode, Mp in Saturation • Vin > VDD - |Vtp| – Mn in Triode, Mp in Cutoff Error in Fig : Replace VOH to VOL + VGSn - + VSGp - Vin < VIL input logic LOW Vin > VIH input logic HIGH •Drain Voltage, f(Vout) –VDSn=Vout, VSDp=VDD-Vout
- 5. Courtesy : Prof Andrew Mason Transistor operating regions Region nMOS pMOS A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff C Vout 0 Vin VDD VDD A B D E Vtn VDD /2 VDD +Vtp
- 6. Courtesy : Prof Andrew Mason Noise Margin • Input Low Voltage, VIL – Vin such that Vin < VIL = logic 0 – point ‘a’ on the plot • where slope, • Input High Voltage, VIH – Vin such that Vin > VIH = logic 1 – point ‘b’ on the plot • where slope =-1 • Voltage Noise Margins Error in Fig : Replace VOH to VOL – measure of how stable inputs are with respect to signal interference – VNMH = VOH - VIH = VDD - VIH – VNML = VIL - VOL = VIL – desire large VNMH and VNML for best noise immunity 1 Vout Vin
- 7. Courtesy : Prof Andrew Mason Switching Threshold • Switching threshold = point on VTC where Vout = Vin – also called midpoint voltage, VM – here, Vin = Vout = VM • Calculating VM – at VM, both nMOS and pMOS in Saturation – in an inverter, IDn = IDp, always! – solve equation for VM – express in terms of VM Error in Fig : Replace VOH to VOL – solve for VM Dp tp SGp p tn GSn n tn GSn OX n Dn I V V V V V V L W C I 2 2 2 ) ( 2 ) ( 2 ) ( 2 2 2 ) ( 2 ) ( 2 tp M DD p tn M n V V V V V tp M DD tn M p n V V V V V ) ( p n p n tn tp M V V VDD V 1
- 8. Courtesy : Prof Andrew Mason Effect of Transistor Size on VTC • Recall • If nMOS and pMOS are same size – (W/L)n = (W/L)p – Coxn = Coxp (always) • If • Effect on switching threshold – if n p and Vtn = |Vtp|, VM = VDD/2, exactly in the middle • Effect on noise margin – if n p, VIH and VIL both close to VM and noise margin is good L W k n n ' p p n n p n L W k L W k ' ' p n p n tn tp M V V VDD V 1 3 2or L W C L W C p n p oxp p n oxn n p n 1 , p n n p p n then L W L W since L normally min. size for all tx, can get betas equal by making Wp larger than Wn