AEC power amplifiers presentation..pptx

ANALOG ELECTRONIC CIRCUITS
(ECE34)
MODULE 5
POWER AMPLIFIERS

Aravinda K., Dept. of E&C, NHCE 2
Classifications of amplifiers
1. Audio and Radio amplifiers
2. Wideband and Narrowband amplifiers
3. Small signal and Large signal amplifiers
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Small signal amplifier Large signal amplifier
Preamplifier (mW) Power amplifier (W)
High voltage gain High current gain
Part of load line Complete load line
Linearity and gain Efficiency and impedance matching

Types of coupling
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Capacitive coupling (HF) Transformer coupling (LF)
Direct coupling
(All frequencies)

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Amplifier classes

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Class C

Amplifier type summary
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Class Output
availability
Quiescent
point
Operating
region
Efficiency
A Complete 360°
cycle
VCEQ = VCC/2,
ICQ = ICsat/2
Mid-
active
25 - 50%
AB In between 180°
& 360°
VCEQ > VCC/2,
ICQ < ICsat/2
Above
cut-off
50 - 78.5%
B Only for 180° VCEQ = VCC & VEE,
ICQ = 0
At cut-off ≤ 78.5%
C Less than 180° VCEQ = VCC,
ICQ = 0
Below
Cut-off
78.5 - 90%
D Pulse operation Switching
type (PWM)
Saturation
& cut-off
> 90%

Two load lines
• DC load line is with respect to the DC equivalent circuit.
• AC load line is with respect to the AC equivalent circuit.
• But the Q-point is the same with both of them.
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AC load line has a higher slope than the DC load line.
Rearranging & substituting the terms accordingly,
the equation for the AC load line is obtained as,
From the DC equivalent circuit, the equation
for the DC load line is obtained as,
ICQ = (VCC – VCEQ) / (RC + RE)
The endpoints of the AC load line are -

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UNFAITHFUL
AMPLIFICATION
FAITHFUL
AMPLIFICATION
The maximum peak output is, MP = ICQrc or VCEQ,
whichever is smaller. Therefore, MPP = 2MP.

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Exercise - 1
Determine
the DC and AC
load line
endpoints,
and also find
the maximum
peak-to-peak
output
voltage:

i) DC load line:
VBB = (68 X 30) / (490 + 68) = 3.66 V
ICQ = IE = (3.66 – 0.7) / 20 = 148 mA
VCEQ = 30 – (0.148 X 140) = 9.28 V
IC(sat) = 30 / 140 = 214 mA, and, VCE(cut-off) = VCC = 30 V
ii) AC load line:
rc = 120 || 180 = 72 Ω
ic(sat) = 0.148 + (9.28 / 72) = 277 mA
vce(cut-off) = 9.28 + (0.148 X 72) = 9.28 + 10.66 = 19.94 V
 MP = 9.28 V and MPP = 2 X 9.28 = 18.56 V
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Solution

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Exercise - 2
Determine the
DC and AC load
line endpoints,
and also find
the MPP
output voltage,
for the Emitter
follower power
amplifier:

i) DC load line:
VBB = (100 X 12) / (50 + 100) = 8 V
ICQ = IE = (8 – 0.7) / 16 = 456 mA
VCEQ = 12 – (0.456 X 16) = 4.7 V
IC(sat) = 12 / 16 = 750 mA, and, VCE(cut-off) = VCC = 12 V
ii) AC load line:
re = 16 || 16 = 8 Ω
ic(sat) = 0.456 + (4.7 / 8) = 1.04 A
vce(cut-off) = 4.7 + (0.456 X 8) = 4.7 + 3.65 = 8.35 V
 MP = 3.65 V and MPP = 2 X 3.65 = 7.3 V
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Solution

Class A Operation
i) Power gain = (Pout / Pin) X 100%
Pout = vrms
2
/ RL = vout
2
/ 8RL = MPP2
/ 8RL
Pin = vin
2
/ 8Zin
ii) Efficiency, η = (Pac / Pdc) X 100%
Pac = vout
2
/ 8RL
Pdc = Vcc X Idc
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Exercise - 3
Find out the transistor power dissipation, power gain and
efficiency for the circuit given in Exercise - 1, if the input
voltage is 200 mVpp, output voltage is 18 Vpp and the input
impedance of the base is 100 Ω.

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Solution
i) Transistor power dissipation = 9.28 X 0.148 = 1.37 W
ii) Output power = 182
/ (8 X 180) = 225 mW
Input power = 0.22
/ 8 (490 || 68 || 100) = 0.134 mW
 Power gain = 225 / 0.134 = 1679
iii) IB = 30 / (490 + 68) = 53.76 mA
Idc = IB + ICQ = 53.76 + 148 = 201.76 mA
Pdc = 30 X 0.20176 = 6.05 W
 Efficiency = 0.225 / 6.05 = 3.72%

Class A amplifier with fixed bias
Maximum Vo(ac) = VCC/2√2
Maximum Io(ac) = VCC/(2√2RC)
 Maximum Po(ac) = VCC
2
/8RC
Maximum Vi(dc) = VCC
Maximum Ii(dc) = VCC/(2RC)
 Maximum Pi(dc) = VCC
2
/2RC
Hence, maximum η = 2/8 = 25%
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Exercise - 4
Calculate the efficiency of the
amplifier circuit, for an input
voltage that results in a base
current of 10 mA peak.

Solution
IBQ = (20 - 0.7) / 1K = 19.3 mA
ICQ = 19.3 mA X 25 = 482.5 mA
 Pi(dc) = 20 X (19.3 + 482.5)m = 10.036 W
ic (rms) = (10 mA X 25) / √2 = 177 mA
 Po(ac) = (177 mA)2
X 20 Ω = 626.58 mW
 Efficiency = 0.62658 / 10.036 = 6.24%
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TRANSFORMER-COUPLED CLASS A AMPLIFIER
(Impedance transformation for better efficiency)
• If RL
′
is the impedance seen at
the primary side, then,
• Thus, when a step-down
transformer is used for signal
coupling, the impedance seen
at the primary side is larger
than the load resistance, and
the value of ic gets reduced.
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where a = turns ratio

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Exercise - 5: For the fixed bias transformer-coupled Class
A amplifier, if the load is a speaker of resistance 16 Ω,
find the turns ratio of the transformer such that the
effective primary resistance is 10 KΩ. Also, find the value
of ac current when VCC = 12 V.
Solution: N1 / N2 = √ (10 K / 16) = 25.
ic = VCEQ / RL
′
= VCC / RL
′
= 12 / 10 K = 1.2 mA.

Efficiency calculations
(From the characteristic curves)
vce(pp) = vce(max) -vce(min)
ic(pp) = ic(max) -ic(min)
 Po(ac) = (vce(max) -vce(min))(ic(max) -ic(min)) / 8
and, Pi(dc) = VCC X ICQ
• The maximum theoretical efficiency can be up to 50%, and
it is given by:
• The power dissipated by the transistor is,
PQ = Pi(dc) - Po(ac)
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Exercise - 6
Calculate the efficiency of a transformer-coupled Class A
amplifier for a supply of 12 V and peak output of 10 V.
Solution:
vce(max) = VCEQ + vp = 12 + 10 = 22 V
vce(min) = VCEQ - vp = 12 - 10 = 2 V
 η = 50 (22 - 2) / (22 + 2) = 41.67%

CLASS B AMPLIFIER OPERATION
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1. This operation is provided when
the transistor to be turned ON when
AC signal is applied.
2. Thus no DC bias and transistor
conducts for only one half of i/p
signal cycle
3. The output can be obtained for
complete full cycle with the push pull
circuit configuration as seen in Fig.
4. Power transistors in push pull circuit deliver
desired power to load and hence provide
more efficiency than Class A amplifiers

Efficiency of Class B Power Amplifier
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Input DC Power Output AC Power
Maximum Power efficiency
When VL(p) = Vcc, η = 78.57 %
Power dissipated by the transistors

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Problem:
Class B amplifier is providing 20 V peak signal to a
16 Ω load and a power supply of Vcc = 30 V; determine
input power, output power and circuit efficiency.
Solution:
IL(p) = 20/16 = 1.25 A
Idc = (2X1.25) / 3.14 = 0.796 A
Pi (dc)= 30X0.796 = 23.88 W
Po (ac)= 202
/ (2X16) = 12.5 W
Efficiency, η = 12.5 / 23.88 = 52.35 %

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Maximum Power Considerations:
Maximum output power :
Maximum input power :
Maximum Power dissipated by
each Transistor:
Maximum Power dissipated by output transistors
:

Phase Splitter Circuits
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Phase splitting with Center-Tapped
Transformer
Phase splitting using BJT
Phase splitting using
OPAMP

Transformer Coupled Push-Pull Amplifier
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During 1st
half cycle -> Q1 conducts & During 2nd
half cycle -> Q2
conducts.
Overall Signal developed varies over full cycle of operation.

Complementary Push Pull Circuits
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• Using NPN and PNP transistors it is possible to obtain a full
cycle output across load
• Disadvantage of this configuration is “CROSS-OVER DISTORTION”
• NPN is ON -> During +ve half cycle & PNP is ON -> During –ve
half cycle

Class AB operation
• To eliminate cross-over distortion, a slight
forward bias needs to be applied to each BE
junction. This means that the Q-point gets
located slightly above cut-off.
• In general, an ICQ from 1% to 5% of IC(sat) is
enough to eliminate crossover distortion.
• Because of this slight forward bias, the
conduction angle will be slightly greater than
180°, and hence, this operation is referred to as
Class AB.
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Examples for Class-AB
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VOLTAGE
DIVIDER BIAS
DIODE
BIAS
The input signal is
applied at the junction
of R2 / diodes.

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Quasi-complementary Push Pull Circuit

Problem on Comp. Push-Pull Amplifier
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Calculate input Power, Output
Power, Power handled by each
transistor and circuit efficiency if
Input = 12V rms, +Vcc=25 V, -Vcc = -
25 V, RL= 4Ω
Solution:
Vi(p)=17 V VL(P)= 17 (since Av=1)
IL(p)=4.25 A Idc= 2.71 A
Pi (dc)= 67.75 W Po( ac)= 36.125 W
Efficiency η = 53.3 %
PQ=15.8 W

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Calculate the maximum input Power , Maximum
output power , input voltage for maximum power
operation and power dissipated by the output
transistor for the same circuit.
Maximum Input Power = 99.47 W
Maximum Output Power = 78.125 W
Maximum Efficiency = 78.54 %
Input voltage for maximum Power = 25 V
Power dissipated by output transistors= 21.3 W

AMPLIFIER DISTORTION
• A pure sinusoidal signal has equal amounts of
variation in positive and negative cycles.
• But if any signal varies over less than the full
360° cycle, then it is called as “distortion”.
• Amplitude distortion occurs due to the non-
linear device characteristics.
• Frequency distortion occurs due to the
difference in frequency response of the circuit
elements.
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• The Fourier analysis defines the signal as the
fundamental frequency, and its integer
multiples as the harmonics.
• Therefore, the distorted signal contains the
fundamental frequency along with the
second harmonic, third harmonic, and so on,
but with reducing amplitudes.
• Total harmonic distortion is given by,
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DISTORTION DUE TO SECOND HARMONIC

Problem: Calculate the total harmonic
distortion for an output signal having the
fundamental amplitude of 2.5 V, second
harmonic amplitude of 0.25 V, third harmonic
amplitude of 0.1 V, and fourth harmonic
amplitude of 0.05 V.
Answer: D2=0.25/2.5=0.1, D3=0.1/2.5=0.04,
D4=0.05/2.5=0.02.
% THD = sqrt (0.12
+ 0.042
+ 0.022
) X 100
= 10.95%
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Expression
for 2nd
harmonic
distortion
• The instantaneous current is given by,
ic = ICQ + I0 + I1cosωt + I2cos2ωt
where ICQ = quiescent current, I0 = additional dc
current, I1cosωt = fundamental component, I2cos2ωt
= second harmonic component.
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• In the curve, at point 1,
ic = ICmax = ICQ+I0+I1cos0+I2cos0 = ICQ+I0+I1+I2
ic = ICQ = ICQ+I0+I1cos(π/2)+I2cos π = ICQ+I0-I2
ic = ICmin = ICQ+I0+I1cosπ+I2cos(2 π) = ICQ+I0-I1+I2
• Solving these equations yields,
•  D2 = I2 / I1. Or,
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TRANSISTOR
POWER RATING
• The maximum power handled by a transistor is
specified at ambient temperature.
• When the temperature exceeds the ambient one,
then in order to prevent the destruction of the
transistor, either a larger heat sink has to be used,
or the power needs to be derated.
•  P2 = P1 - [(T2-T1)DF] where DF = Derating Factor.
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Problem: Determine the maximum power
dissipation allowed for an 80 W Silicon transistor, if
derating is required above 25°C, by a derating
factor of 0.5 W/°C at a case temperature of 125°C.
Answer: Power at 125°C = 80-[(125-25)0.5] = 30 W.
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CLASS C AMPLIFIER-INTRODUCTION
• In Class C operation, the collector current flows for
less than half cycle.
• The conduction period is less than 180˚
• The efficiency of class C amplifier is 100%
• Class C amplifier is intended to amplify narrow band
of frequencies on both sides of centre frequency .
• The centre frequency is resonant frequency of
parallel resonant circuit connected at the collector of
Class C Amplifier.
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Class C Tuned RF Amplifier
Tuned Class C Amplifier Unbiased DC equivalent
circuit
Ac input voltage drives base and an amplified inverted
signal at collector is capacitively coupled to the load
resistance.
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AC equivalent circuit
Output voltage is maximum at the
resonant frequency ½∏√ LC
DC load line is vertical and the
winding resistance is very low
When AC signal is present, instantaneous Q point moves up and
maximum collector current is Vcc/rc
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DC CLAMPING OF INPUT SIGNAL
Significance of conduction Period
Input signal clamped at base
Collector current flows in pulses
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DC CLAMPING OF INPUT SIGNAL
Significance of conduction Period
Ac Collector Circuit
Collector Voltage Waveform
Resonant circuit offers high
impedance at fundamental
frequency producing high
gain. Low impedance at
harmonics reducing gain.
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EXAMPLE
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CLASS C FORMULAS
• BW of a resonant circuit is f2-f1
• f1 = lower half power frequency
• F2 = Upper half power frequency
• At half power frequencies, voltage gain equals
0.707 times maximum voltage gain.
If Q=10, BW is 10% less than
of resonant frequency.
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CLASS C FORMULAS
Series equivalent resistance for
inductor
Parallel equivalent resistance for
inductor
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CLASS C FORMULAS
• Duty Cycle = W/T
• Conduction angle =Ф/360
• Maximum Voltage = 2Vcc
• Maximum power dissipation = (MPP X
MPP)/40rc
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CLASS D AMPLIFIER
Class D
amplifier
is designed
to operate
with
digital or
pulse type
signals
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Block diagram of Class D amplifier
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Important formulae
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