Ah2418191827

International Journal of Modern Engineering Research (IJMER)
www.ijmer.com Vol.2, Issue.2, Mar-Apr 2012 pp-1819-1827 ISSN: 2249-6645

Performance of Symmetrical and Asymmetrical Multilevel Inverters

K. Lakshmi Ganesh , U. Chandra Rao
1,2
(Department of Electrical and Electronics Engineering, Sri Vasavi Engineering College, India 

Abstract: Distributed Energy Resources (DER) are systems powerprocessing interface is required and is Commercial,
that produce electrical power at the site where the power is homes, factories and utility grid standards [4],[7].
needed. If only electrical power is used then the technology is Differing converter topographies have been acquired
called Distributed Generation (DG). The objective of this DERs establish effectual power flow control performance of
paper is to study a novel more than five level multistring DERs. DER systems may be either connected to the local
inverter topology for DERs based DC/AC conversion system. electric power grid or isolated from the grid in stand-alone
The distributed energy resource based single-phase inverter is applications [7], [10].
usually adopted in the microgrid system. In order to reduce the The dc-dc converters are two types. They are without
conversion losses, the key is to saving costs and size by galvanic isolation and with galvanic isolation (high frequency
removing any kind of transformer as well as reducing the transformer).The with galvanic isolation converter (high power
power switches. In this study, a high step-up converter is applications) are used corresponding to size, weight, expense
introduced as a front-end stage to improve the conversion reduces. So low and medium power applications without
efficiency of conventional boost converters and to stabilize the galvanic isolation means make no use of transformers
output DC voltage of various DERs such as photovoltaic for corresponding to reduces the size, weight expense [7], [8].
use with the simplified multilevel inverter. In addition, two The next procedure the output voltage level increases
active switches are operated under line frequency. In this of the inverter output then automatically harmonic component
project a novel asymmetrical configuration is proposed. The of the output voltage of inverter reduces and also
proposed asymmetrical configuration uses less number of corresponding to small size of filters are used simultaneously
switches to get more levels. It will reduce the cost, reduce the
the cost reduces. The differing multilevel topographies are
number of sources, complexity, losses and improves reliability.
usually characterizing by strong reduction of switching power
The proposed converter is simulated by Matlab/Simulink
losses and electromagnetic interference (EMI) [6], [7], [8].
software and simulation results are presented.
A new simplified single-phase multistring five-level
multilevel inverter topography of dc/ac power conversion with
Key words: DC/AC power conversion, multilevel inverter,
auxiliary circuit proposed [8], [9]. This topography are used,
harmonic analysis and Total Harmonic Distortion (THD).
the number of switching devices and output harmonics are
reduced. The THD of the multistring five-level inverter is
I. INTRODUCTION
The continuous economic development of many much less than the conventional multistring three-level inverter
countries and the environmental issues (gas emissions and the because of additional auxiliary circuit has high switching
losses [9].
green house effect) observed in the last decades forced an
The objective of this paper is to study a newly
intense research in renewable energy sources. Distributed
constructed transformerless five level multistring inverter
energy resources are small, modular, energy generation and
topology for DERS. In this letter aforesaid GZV-based
storage technologies that provide electric capacity or energy
inverter is reduced to a multistring multilevel inverter
where you need it. Typically producing less than 10 megawatts
topography that require only 6 active switches instead of
(MW) of power, DER systems can usually be sized to meet
existing cascaded H-bridge multilevel inverter have eight
your particular needs and installed on site.
switches[10].Multi string multilevel inverter have six active
DER technologies include wind turbines, photo
switches. They are middle two switches are operated
voltaic (PV), fuel cells, micro turbines, reciprocating engines,
fundamental frequency and remaining four switches are
Hydro, combustion turbines and energy storage systems are the
operated switching frequency. A high efficiency dc-dc boost
most explored technologies due to their considerable
converter reduction of transformer and device voltage and
advantages [1],[2], such as reliability, reasonable installation
current stresses with continuous input current leakage
and energy production costs, low environmental impact,
inductance energy recovery, and avoiding the use of
capability to support micro grid [3].
electrolytic capacitor due to reduced ripple current[13].
The renewable energy resources consists of
Operation of the system configuration of operation is shown
photovoltaic, fuel cells are generate the voltage are dc voltage.
below. The performance of symmetrical and asymmetrical
But I want the ac voltage because of mostly used the loads are
single phase multilevel inverter with respect to harmonics
ac loads. So we are convert the dc power to ac
content and number of switches and input voltage source is DC
is simulated by MATLAB/Simulink. A detailed harmonic

www.ijmer.com 1819 | P a g e

analysis is done on the multilevel inverter by considering up to 2.1. High Step-Up Converter Stage
23rd harmonics for 7 levels to 13 levels operation. In this study, High Efficiency Converter with Charge
Pump and Coupled Inductor for Wide Input Photovoltaic AC
II. SYSTEM CONFIGURATION OF OPERATION Module Applications [13].This simplified multilevel inverter
PRINCIPLES combines the behavior of three different converter topologies:
boost, flyback and charge pump. The flyback aspect of the
topology allows the design to be optimized in terms of the
transformer turns-ratio, allowing for much higher voltage gains
than would be possible with a boost converter. However,
flyback converters are notoriously inefficient and are very
sensitive to leakage inductance, which can cause undue
voltage-stress on switches and diodes. By using a clamp-
circuit- identical to the output of a boost-converter-after the
main switch, much of the efficiency issues can be resolved and
Fig.1 Different type of DERs are system configuration of
the transformer design becomes less complicated. Finally,
Multistring Inverter
adding a charge-pump capacitor across the primary and
The above Fig.1 shows the DERs have photovoltaics secondary windings of the transformers gives higher converter
or Fuel cell inverter are taken as [14].The individual dc/dc voltage-gain and reduced peak current stress by allowing the
boost converter are connected to the photovoltaic modules or current of the primary-windings to continuous.
Fuel cell. The bidirectional (buck-boost) dc/dc converter is The equivalent circuit of the proposed converter is
connected to the only for battery storage. The individual dc/dc shown in Fig.3. The coupled inductor is modeled as a
boost converter is connected to the multistring inverter. These magnetizing inductor Lm an ideal transformer with a turn’s
common inverter for interface with all dc/dc converters of
DERs [15]. The two modes of operation above Fig.1. They are
ratio of N s : N p primaryleakage inductor LLk1 and secondary
standalone mode and grid connected mode. In grid connected leakage inductor LLk 2 . Cc is the clamp capacitor, S is the
mode, the battery storage energy is not connected to the grid.
In standalone operation, the battery storage energy is Active switch, D0 is the output diode C pump is the charge
connected to the load. pump capacitor.
According to voltage-seconds balance condition of the
magnetizing inductor, the voltage of the primary winding can
be derived as
v pri
 Vin 1D
D
(1)

Where Vin represents each the low-voltage dc energy input
sources and voltage of the secondary winding is

 N. S
 N. S D
v sec v pri V in
1 D
(2)
Fig.2 Single phase simplified multistring five-level inverter N P N P
topography for high stepup converter from DERs Similar to that of the boost converter, the voltage of the
charge-pump capacitor C pump and clamp capacitor Cc can be
The above Fig.2 shows DER module-1 is connected
to the high step up dc/dc converter and DER module-2 is expressed as
1
connected to high step up dc/dc converter. These two
vC v  Vin . (3)
converters are connected to their individual dc-bus capacitor pump Cc 1 D
and a simplified multilevel inverter. The resistive load is Hence, the voltage conversion ratio of the high step-up
connected output of the simplified multilevel inverter from converter, named input voltage to bus voltage ratio, can be
DER through high step up dc/dc converter. The input sources derived as [13].
of DERs are photovoltaic or Fuel cells. The basic circuit have
 
eight switches of cascaded H-bridge Multilevel inverter (CHB)  2  NS
 .D 
with phase shift carrier pulse width modulation scheme are V 0

NP   (4)
used. The simplified multilevel inverter have six switches then
V in
1 D
best merits of improved output waveforms, reduced the filter
size, low EMI and THD [11],[12]. It should be noted that, by
using independent voltage regulation control of the individual
high step-up converter, voltage balance control for the two bus
capacitors Cbus1 , Cbus2 can be achieved normally.



Fig.3. Equivalent circuit of the high step-up boost converter
2.2 Simplified Multilevel Inverter Stage

(a)

Fig.4 Basic Five-level inverter Circuitry of six switches

The simplified multilevel inverter is the conventional
circuit of five level inverter Fig.4 shows above. A new single
phase multistring topography, as a new basic circuitry in
Fig.4.Referring to Fig.2, it is should assumed that, in this
configuration, the two capacitors in the capacitive voltage
divider are connected directly across the dc bus and all
switching combinations are activated in an output cycle. The (b)
dynamic voltage balance between the two capacitors is Fig.5. Modulation strategy a) Carrier/reference signals
automatically controlled by the preceding high step-up (b) modulation logic
converter stage. Then, we can assume Vs1  Vs 2  Vs .
This circuit has six power switches compare the basic Table-I
circuit of cascaded H-bridge has eight power switches which Simplified Five Level Inverter Switching Combination
drastically reduces the power circuit complexity and simplifies Sa2 S b1 Sb 2 Sb 3 V AB
modulation circuit design and implementation. The phase S a1 Sa3
disposition (PD) pulse width modulation (PWM) control 0 1 0 1 0 1 2VS
scheme is introduced to generate switching signals and to
produce five output voltage levels: 0,Vs ,2Vs ,Vs and 2Vs
0 1 1 1 0 0 VS
This inverter topology uses two carrier signals and 1 1 0 0 0 1 VS
one reference signal to generate the PWM signals for the 1 1 1 0 0 0 0
switches the modulation strategy and its implemented logic
0 0 0 1 1 1 0
scheme in Fig.5 (a) and (b) area widely used alternative for
Phase disposition modulation. With the exception of an offset 1 0 0 0 1 1  VS
value equivalent to the carrier signal amplitude. Two
comparators are used in this scheme with identical carrier
0 0 1 1 1 0  VS
signals Vtri1 and Vtri 2 toprovidehigh– 1 0 1 0 1 0  2VS
frequencyswitchingsignals for S a1 , S b1 , S a 3 and Sb 3 . Another
Table-I lists switching combinations that generate the required
comparator is used for zero-crossing detection to provide line-
five output levels. The corresponding operation modes of the
frequency switching signals for switches S a 2 and S b 2 . simplified multilevel inverter stage are described clearly as
For Fig.4 the switching function of the switch defined as follows.
follows. 1) Maximum positive output voltage ( 2VS ): Active
S aj = 1, S aj ON switches S a 2 , S b 3 and S b1 are ON. The voltage applied to the
S aj = 0, S aj OFF for j=1, 2, 3 LC output filter is 2VS .
S bj = 1, S bj ON 2) Half level positive output voltage (  VS ): The two
S bj = 0, S bj OFF for j=1, 2, 3 switching combinations are there. One switching combination


is that active switches S a 2 , S a 3 and S b1 are ON, the other is 2.3 Basic circuit of Cascaded H-Bridge (CHB) Inverter

active switches S a 2 , S a1 and Sb 3 are ON. During this
operating stage, the voltage applied to the LC output filter
 VS .
3) Zero Output, (0): This output condition either one of the leg
are left or right all switches are ON. The load is short-
circuited, and the voltage applied to the load terminals zero.
4) Half level negative output voltage (  VS ): the two
switching combinations are there. One switching combination
is such that active switches S a1 , S b 2 and S b 3 are ON, the
other switching is active switches S b 2 , S b1 and S a 3 .
5) Maximum negative output (  2VS ): During this stage, Fig.7 Basic circuit of five-level inverter topology of CHB
inverter have eight switches
active switches S a1 , S a 3 and Sb 2 are ON, and the output
voltage applied to the LC output filter  2VS . The above figure shows the Basic circuit of five level
inverter CCHB inverter have eight switches. The carrier based
In these circuit operations, it can be observed that the open sinusoidal phase shift carrier pulse width modulations are used
voltage stress of the active power switches S a1 , S b1 , S a 3 and in the basic circuit of CHB inverter. The eight switches are
Sb 3 is equal to input voltage VS and the main active switches operated of the switching frequency. The CHB inverter are
operate at the switching frequency is same as18.06kHz the
S a 2 and Sb 2 are operated at the line frequency. Hence, the same modulation index ma =0.7.
switching losses are reduced in the new topology and the The simplified multilevel inverter and Cascaded H-
overall conversion efficiency is improved. bridge inverter are operated the same switching frequency and
In Fig.5 control circuit diagram as shown, mt  is the same modulation index ma ,the same input voltage VS =100V
sinusoidal modulation signal. Both Vtri1 and Vtri 2 are two and output L-C filter, L0 =20mH, C0 =200uF, R-load
carrier signals. The magnitude value and frequency of the =10Ohms. Table VII and Table VIII shows the harmonic
sinusoidal modulation signal are given as m peak =0.7 and component and THD Cascaded H-Bridge Inverter and
f m =60Hz. The peak to peak value of the triangular Simplified multilevel inverter. The simplified multilevel
inverter have the lesser THD compare to the Cascaded H-
modulation signals is equal to 1 and the switching frequency bridge inverter. So the low values of LC filter.
f tri1 and f tri 2 are both given as 18.06 kHz. The symmetrical multilevel inverters are Cascaded
The two input voltage sources feeding from the high step up H-bridge inverter and Simplified multilevel inverter. These are
converter is controlled at 100V that is taken the equal voltage values. The symmetrical multilevel
inverters above are operated with PWM method. The
Vs1  Vs 2  100V. The five level output of the phase voltage
Proposing methods of asymmetrical multilevel inverters are
of the simulation waveform is shown in Fig.6. repeating sequence is used for Seven, Nine, Eleven and
Thirteen levels. The seven level have 6switches and Nine,
Eleven and Thirteen level have 8 switches. The Seven, Nine,
Eleven and Thirteen levels are get by using 12,16,20,24
switches are necessity in symmetrical configuration of
Cascaded H-bridge inverter. So the less number of switches
are in asymmetrical configuration to get more number of
voltage levels, lesser the THD, low cost, reducing the DC
sources, reduce the complexity and driving circuits.

Fig.6 Simplified multilevel five level output phase
voltage of simulation waveform V AB


III. PROPOSED SYTEM 3.3Eleven Level Multilevel inverter (MLI)
3.1Seven Level Multi Level Inverter (MLI) Table- IV
Eleven level multilevel Inverter (MLI)
Table- II
Seven Level Multilevel Inverter (MLI) S1 S2 S3 S4 S5 S6 S7 S8 V0
S a1 Sa2 Sa3 S b1 Sb 2 Sb3 V0 0 1 0 1 1 0 1 0 5VS
1 1 0 1 0 0 1 0 4VS
0 1 0 1 0 1 3VS 0 1 0 0 1 0 1 1 3VS
1 1 0 0 0 1 1 1 0 0 0 0 1 1 2VS
2VS
0 1 1 1 1 0 0 0 VS
0 1 1 1 0 0 1 1 1 1 0 0 0 0 0
VS
0 0 0 0 1 1 1 1 0
1 1 1 0 0 0 0
1 0 0 0 0 1 1 1  VS
0 0 0 1 1 1 0
0 0 1 1 1 1 0 0  2VS
1 0 1 1 0 1 0 0  3VS
1 0 0 0 1 1  VS 0 0 1 0 1 1 0 1  4VS
0 0 1 1 1 0  2VS 1 0 1 0 0 1 0 1  5VS
1 0 1 0 1 0  3VS
The above Table II is shows the active switches operation of The above Table VI is shows the active switches
operation of eight switches with eleven level, 1 means the
seven level, 1 means the switch is ON, the 0 means the switch
switch is ON, the 0 means the switch is OFF. Then we will get
is OFF. Then we will get the seven level output voltage from
the eleven level output voltage from the eight switches only.
the six switches only.
3.4 Thirteen Level multi Level inverter
3.2Nine Level Multi Level Inverter (MLI)
Table-V
Table- III Thirteen level multi level inverter (MLI)
Nine level Multilevel (MLI)
S1 S2 S3 S4 S5 S6 S 7 S8 V0
S1 S2 S3 S4 S5 S6 S7 S8 V0
0 1 0 1 1 0 1 0 4VS 0 1 0 1 1 0 1 0 6VS
1 1 0 1 0 0 1 0 3VS
0 0 0 1 1 1 1 0 0 1 0 0 1 0 1 1 5VS
2VS
0 1 1 1 1 0 0 0 1 1 0 1 0 0 1 0 4VS
VS
1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 3VS
0 1 1 1 1 0 0 0 2VS
0 0 0 0 1 1 1 1 0
0 0 0 1 1 1 1 0 VS
1 0 0 0 0 1 1 1  VS
1 1 1 1 0 0 0 0 0
1 1 1 0 0 0 0 1  2VS 0 0 0 0 1 1 1 1 0
0 0 1 0 1 1 0 1  3VS 1 1 1 0 0 0 0 1  VS
1 0 1 0 0 1 0 1  4VS 1 0 0 0 0 1 1 1  2VS
0 0 1 1 1 1 0 0  3VS
The above Table III is shows the active switches
operation of eight switches with nine level, 1 means the switch 0 0 1 0 1 1 0 1  4VS
is ON, the 0 means the switch is OFF. Then we will get the
nine level output voltage from the eight switches only.
1 0 1 1 0 1 0 0  5VS
1 0 1 0 0 1 0 1  6VS


The above Table V is shows the active switches
operation of eight switches with thirteen level, 1 means the
switch is ON, the 0 means the switch is OFF. Then we will get
the thirteen level output voltage from the eight switches only.
3.5Different voltages are taken as the source voltages of
the asymmetrical multilevel inverters
TABLE VI
DIFFEERENT VOLTAGES
No of No of V1 V2 V3 Output
levels Voltage in Fig.10 shows the output voltage with LC filter of CHB inverter
Switches V of M.I=0.7
7 6 VS 2VS - 3VS
9 8 VS VS 2VS 4VS
11 8 VS 2VS 2VS 5VS
13 8 VS 2VS 3VS 6VS
The seven level output voltage are get only from six
switches only. The nine level, eleven level and thirteen level
output voltage are get only from eight switches corresponding
to respective voltage sources are taken.
The above table VI shows different voltages are taken for Fig.11shows the unity power factor at the R-Load with LC
asymmetrical multilevel inverters. The asymmetrical multilevel filter of CHB inverter of M.I=0.7
inverters are simulated the output voltage are designed by
using 200V. The seven level output voltage are get by using
V1=66.66V, V2=133.33V. The nine level output voltage are get by
using V1=50V, V2=50V, V3=100V. The eleven level output voltage
are get by using V1=40V, V2=80V, V3=80V. The thirteen level
output voltage are get by using V1=66.66V, V2=99.99V,
V3=33.33V. The asymmetrical multilevel inverters are simulate the
above written voltage values.

IV. MATLAB/SIMULATION RESULTS
4.1Basic circuit of Cascaded H-Bridge five level Inverter
Fig.12 shows the five level output voltage CHB inverter
without LC of M.I=0.8

Fig.8 shows the five level inverter CHB simulink circuit
Fig.13 shows the output voltage with LC filter of CHB inverter
of M.I=0.8

Fig.9 shows the five level output voltage CHB inverter without
LC of M.I=0.7


Fig.14 shows the unity power factor at the R-Load with LC
filter of CHB inverter of M.I=0.8

Table-VII
Harmonics of CHB Inverter with and without LC

The Table VII shows the CHB inverter operating two
modulation indexes. They are 0.7 and 0.8 without and with LC
filter.
4.2 Simplified Five level Inverter
filter of simplified five level inverter of M.I=0.7

Fig.19 shows the five level output voltage simplified five level
Fig.15. The simulink of simplified five level multilevel inverter without LC of M.I=0.8
inverter

Fig.20 shows the output voltage with LC filter of simplified
five level inverter of M.I=0.8
Fig.16 shows the five level output voltage of simplified five
level inverter without LC of M.I=0.7

Harmonics ma =0.7 ma =0.8
Fundamental 1 154.02 183.84
h3 2.40 3.31
h5 1.19 0.11
h7 0.24 0.07
h9 0.05 0.20
h11 0.02 0.09
filter simplified five level inverter of M.I=0.8
%THD 0.146 0.114
WITHOUT LC Table-VIII
%THD WITH 0.015 0.013 Harmonics of Simplified Five Level Inverter with and
LC without LC
Harmonics ma =0.7 ma =0.8
Fundamental 1 157.77 185.66
h3 0.81 1.98
h5 0.25 0.17
h7 0.17 0.32
h9 0.06 0.06
h11 0.07 0.05
%THD 0.0701 0.0684
Fig.17 shows the output voltage with LC filter of simplified WITHOUT LC
five level inverter of M.I=0.7 %THD WITH 0.005 0.003
LC


The Table VIII shows the simplified five level
inverter operating two modulation indexes. They are 0.7 and
0.8 without and with LC filter.
The modulating frequency (Switching frequency) is
18060Hz.
The CHB five level inverter operated with ma =0.7
and ma =0.8 with phase shift carrier pulse width modulation Fig.26 Nine level multilevel Inverter output voltage
technique then I would get the fundamental component voltage
increases and THD value decreases when modulation index
ma =0.8 compare to the ma =0.7.The simplified five level
inverter operated the same modulation index with phase
disposition pulse width modulation technique then I would get
the fundamental component voltage increases and THD value
decreases compare to the CHB inverter. After clearly
understand reduce the number of switches, improved output Fig.27 THD value of the nine level multilevel inverter using
waveforms, smaller filter size and lower EMI of simplified FFT analysis
multistring five level inverter compared to the CHB inverter.
4.3 Proposing system of Seven Level multilevel 4.4 Proposing System of Eleven Level multilevel inverter
inverter

Fig.28 Eleven level mulitlevel Inverter output voltage

Fig.22 Simulink of the seven level multilevel inverter

Fig. 29 THD value of the eleven level multilevel inverter
using FFT analysis
Fig.23 Seven level multivlevel Inverter output voltage 4.5Proposing System of Thirteen Level multilevel inverter

Fig.30 Thirteen level multilevel Inverter ouput voltage
Fig.24THD value of the Seven level multilevel inverter
using FFT analysis

4.4 Proposing System of Nine Level multilevel inverter

Fig.31 THD value of the thirteen level multilevel inverter
using FFT analysis
Fig.25 .Simulink of the nine, eleven and thirteen level
multilevel inverter


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