Alternative approach to design matching network for differential drive 2016

Contents lists available at ScienceDirect
Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo
Alternative approach to design matching network for differential drive
rectifier used in RF energy harvesting
Shailesh Singh Chouhan
⁎
, Kari Halonen
Department of Micro and Nano Sciences, School of Electrical Engineering, Aalto University, Espoo, Finland
A R T I C L E I N F O
Keywords:
RF energy harvesting
Differential drive rectifier
Matching network
RF-to-DC converter
Oscillator
A B S T R A C T
In this work, a measurement-based technique to determine LC-matching network for RF-to-DC converter is
proposed. It is shown that the differential drive rectifier can be configured as the differential CMOS LC-oscillator
by swapping input and output terminals. Thus, this oscillator can then be used to find the inductor (L) and
capacitor (C) component values for the rectifier matching network at the intended frequency, which is the
oscillation frequency of the oscillator. Measured results show that the absolute frequency error between
resonant frequency obtained from oscillator mode and matching frequency obtained as rectifier is less than 2%.
The switching core used in this work has been implemented in a standard 0.18 μm CMOS technology and
external discrete passive components are used to form the LC network.
1. Introduction
Nowadays, wireless sensor network (WSN) is increasingly used in
many areas of everyday lives like health, environment, geographic
regions monitoring, etc. [1]. These spatially distributed nodes monitor
ambient parameters which are then processed and transmitted to the
interrogator. The power consumption of these sensor nodes is one of
the major constraints of these systems as they are spread over large
geographic area [2]. Hence, the use of energy harvesting methods is
preferred to save vast human resources which are required for
changing battery of the sensor nodes [3]. Various energy harvesting
methods like solar energy harvesting, vibration energy harvesting, etc.,
are proposed in the literature [4]. In these methods, the omnipresence
of RF signals makes the RF-based energy harvesting as the potential
candidate to power-up wireless sensor nodes [5].
A typical block diagram of the RF-based energy harvesting system is
shown in Fig. 1. It can be seen from the figure that the front-end of the
RF-energy harvester is the rectifier, which converts the received RF-
power from antenna to the DC-power. This rectified DC-power is used
by the wireless sensor node to perform various operations.
Different rectifier architectures are proposed by the researchers,
which have been broadly classified as single-input [6,7] and differen-
tial-input rectifier circuits [8,9,15]. Generally, the differential-input
rectifier topology is preferred over single-input for on-chip implemen-
tation due to their higher power conversion efficiency [8,9].
One of the challenging issues in designing rectifiers is the depen-
dency of their quality factor on device sizing [9]. Hence, a careful
design of the matching network is essential to reduce the transmission
loss that occurs from antenna to the rectifier circuit for transfer of the
maximum power [16]. This network is preferably implemented off-chip
due to ease of tuning. Different methods are proposed in the literature
to design matching network off-chip which, are equally applicable for
the RF- rectifier. Some of the design strategies are, tunable inductor
concept [10], Q-based design process [11], or adaptive matching
network [12,13]. All of these methods have been applied in the cases
involving load variation or frequency drift. Most recently, a concept of
resistance compression network is proposed to increase the efficiency
of differential drive rectifier in [14].
In this work, a method for matching-network designing is pro-
posed, particularly for the differential-drive rectifier published in [8,9].
The measured results show that it is possible to determine and
successfully implement the LC matching network by configuring
differential rectifier as a complementary CMOS LC-oscillator [17] by
swapping the input and output terminals. The architecture is imple-
mented using a standard 0.18 μm CMOS technology and the off-chip
LC matching network is designed by using surface mount inductor and
capacitor.
This paper is organized as follows: Design consideration are
discussed in Section 2, experimental steps and the measurement
results are given in Section 3, and finally, the conclusions are presented
in Section 4.
http://dx.doi.org/10.1016/j.mejo.2016.10.008
Received 3 March 2016; Received in revised form 23 August 2016; Accepted 21 October 2016
⁎
Corresponding author.
E-mail address: shailesh.chouhan@aalto.fi (S.S. Chouhan).
Microelectronics Journal 58 (2016) 39–43
0026-2692/ © 2016 Elsevier Ltd. All rights reserved.
crossmark

2. Design process steps
The differential drive CMOS-rectifier [8] and complementary
CMOS LC -oscillator [17] are shown in Fig. 2a and b respectively. In
the figure, nomination N and P refers to the nMOSFET and pMOSFET,
Cfly, Cblk are the pumping and DC blocking capacitors, and L, C
represents the inductor and capacitor respectively.
It can be observed in Fig. 2 that both circuits have the same cross-
coupled CMOS switching core, but their input and output terminals are
swapped and as a result, the functionality changes from a rectifier to an
oscillator and vice-versa.
2.1. Sizing of transistors for the rectifier
The primary aim of this work is to obtain the matching network for
the rectifier. Hence, a simulation-based strategy was adopted to obtain
the aspect-ratio of the transistors used in the rectifier. The circuit
setup, which was used for the simulation is shown in Fig. 3. In the
figure, ideal balun has been used to obtain true-differential stimulation.
The transient simulations were performed using Spectre simulator in
the Cadence® environment. In these post layout simulations, longer
simulation period (>1000 cycles) was selected to get a steady state
output DC voltage from the rectifier.
The simulation environment is given in Table 1. The value of output
DC voltage by varying width of the transistors (N and P) are shown in
Fig. 4. It can be seen from the figure that the maximum DC output
voltage, which is obtained from each frequency do not share a common
peak. Therefore, in this experiment the width of the transistors was
selected 65 μm as highlighted in Fig. 4. Since, for this transistor-width
the output DC voltage from each frequency is relatively same with a
good accuracy.
2.2. Determination of LC matching network
In order to obtain the matching network, the rectifier is configured
as the oscillator (Fig. 2b) and ISM 433 MHz [19] was selected as the
target oscillating frequency. The circuit setup used in simulations is
shown in Fig. 5. It can be seen from the setup that the open-ended
terminals of the capacitors (Cfly) have been connected to the ground
node. As a result, nodes (a) and (b) have become the output terminals.
The most important consideration in this circuit setup is the value of
supply voltage, which has been fixed at 4Vth. The requirement of
stringent supply voltage is well known [17] and can be considered as
limitation of the proposed method, however, it is essential to verify the
matching network. Since, the LC network will be implemented
externally hence, the S-parameters based models of the various
inductors and capacitors used in the simulations were obtained from
Fig. 1. Block diagram of RF-based energy harvesting system.
Fig. 2. (a) Differential drive CMOS rectifier with matching network (b) Complementary CMOS LC oscillator.
Fig. 3. Simulation setup used for rectifier characterization.
Table 1
Simulation environment.
S.No. Parameter Value
1 Transistor length 0.18 µm (minimum)
2 Transistor width 5–100μm
3 Fly-capacitor (Cfly) size 10 pF (MIM capacitor)
4 RC load value RL=10 KΩ, CL=20 pF
5 Input RF peak amplitude 300 mV
6 Input RF frequency 400 MHz, 800 MHz, 1 GHz
Fig. 4. Variation of output DC voltage with width of transistors.
S.S. Chouhan, K. Halonen Microelectronics Journal 58 (2016) 39–43
40

[18].
An inductor (L) of value 20 nH was selected and the capacitor (C)
value was obtained by estimating total capacitance present at the
node(a). The model circuit with parasitic capacitances is shown in
Fig. 6. It can be estimated from the model that the net capacitance
(Ctot) [20] present at the node (a) is:
  
C C C C C C C
C
= + + + + + +
2
tot fly dbN gdN w gdP dbP
parasitic capacitances (1)
where Cfly is the fly capacitance, CdbN is the drain-body and CgdN is
the gate-drain capacitances of nMOSFET (N), CdbP is the drain-body
and CgdP is the gate-drain capacitances of pMOSFET (P), Cw is the
interwiding capacitance [21] of the inductor and C is the value of
external capacitor.
In (1), Cfly was selected as 10 pF, net parasitic capacitance at node
(a) was estimated as 0.5 pF and thus, the value of external capacitance
(C) was calculated to be 3 pF by using (2) at the targeted oscillating
frequency (f) of 433 MHz.
f
π LC
=
1
2 tot (2)
The post layout spectrum plot of the output signal is shown in
Fig. 7. The spectra has been calculated by using rectangular window
with 4096 samples obtained from 2 μs long transient simulation. It can
be observed from Fig. 7 that the spectral peak appears at 430.8 MHz.
In the next stage, to verify the proposed concept the circuit was
configured as a rectifier and the post-layout S-parameters were
obtained by using SP-analysis feature of the spectre simulator. The
plot of differential-input-reflection coefficient (Sdd11) is shown in
Fig. 8.
It can be observed by comparing Figs. 7 with 8 that the error in the
tuning/matching frequency is approximately 4 MHz. This inaccuracy is
a result of change in the terminal impedance because of swapping of
their role.
3. Experimental steps and measurement results
The switching core was implemented in a standard 0.18 μm CMOS
technology. The micrograph of the chip and the PCB are shown in
Fig. 9. The PCB was designed using a standard FR4 substrate and was
milled in the laboratory. This experiment was performed in three steps:
Step-1: The switching network was configured as an oscillator as
shown in Fig. 2b, as mentioned earlier the ISM 433 MHz was selected
as target frequency.
The external multilayer ceramic capacitor (MCH18) of value 0.5 pF
from ROHM®
and inductor (LL1005-FH) of value 18 nH from TOKO®
were used in the experiment by using Eq. (2). The measured spectrum
of the output signal by using Agilent® 4395A Spectrum Analyzer is
shown in Fig. 10. It can be observed that the oscillator is generating a
Fig. 5. Simulation setup used for oscillator characterization.
Fig. 6. Parasitic capacitances present at node (a).
Fig. 7. Simulated spectra of output signal.
Fig. 8. Simulated mixed mode differential-input-reflection-coefficient.
41

430.9375 MHz signal with the supply voltage of 1.25 V which is
approximately 4Vth. This voltage was delivered to the circuit by using
Agilent® N6705A power supply.
Step-2: In the next stage, the designed architecture is configured as
a rectifier as shown in Fig. Fig. 2a. In order to locate the selected
frequency the frequency-characterization was done. In this character-
ization, the RF signal was supplied by R & H signal generator
SMIQ06B® which was split into a differential signal by using two-way
180° power splitter ZSFCJ-2-4 from Mini Circuit®. The input RF-power
delivered to the rectifier was set as −10 dBm and the output DC voltage
was measured across an impedance of value Ω1 nF 30 k by varying RF
Fig. 9. (a) Micro graph of cross coupled CMOS switches (b) PCB used to perform the
experiment with on-board LC components.
Fig. 10. Meausred spectrum plot.
Fig. 11. Output DC voltage for different RF frequency values.
Fig. 12. Measurement plot of mixed mode differential-input-reflection-coefficient
Sdd11.
Table 2
Measurement results for different L and C combinations.
Component Frequency Frequency Frequency Sdd11 Peak
(L and C) (Step-1) (Step-2) (Step-3) (dB) PCE(%)@
Pin(dBm)
10 nH, 4 pF 801.2 MHz 795 MHz 797.28 MHz −13.2 19%@
−4 dBm
5.6 nH, 9 pF 715.08 MHz 712 MHz 714.62 MHz −14.6 24%@
−4 dBm
10 nH, 7 pF 660.12 MHz 665 MHz 668.62 MHz −16.2 28%@
−5 dBm
39 nH, 5 pF 343.14 MHz 347 MHz 352.37 MHz −12 39%@
−5.5 dBm
42

signal frequency in the steps of 20 MHz. It should be noted that the
tuning frequency resolution was decreased near frequency of interest to
locate the exact frequency value corresponding to the peak output DC
value. The measured output DC voltage values at different input RF
frequencies have been plotted in Fig. 11. It can be seen from the figure
that the maximum DC level of 380 mV is delivered to the load, at the
input RF frequency of 437.5 MHz. Thus, the frequency tuning error of
1.5% exists between the frequencies obtained from Step-1 and Step-2
for the rectifier. It can be noticed when compare with Figs. 7 and 8 that
measurement results show around 66% additional error from the
simulations. This increase in the matching error was expected since,
in the simulations, only parasitic capacitances contribution of the
transistors were selected. However, in the measurement the additional
parasitics are appeared due to soldering of the components, PCB
tracks, variation in the Q values of the components from lot-to-lot
variations, bond-wire inductance of the IC and selection of the package
type.
Step-3: Finally, to validate Step-1 and Step-2, the single ended S-
parameters were measured by using the Agilent 8722ES network
analyzer®. The single ended S-parameters were then converted into
the mixed-mode parameters by using the Matlab® program. The mixed-
mode differential-input reflection coefficient Sdd11 shows the match-
ing at 437.5 MHz, which is shown in Fig. 12, which finally formalized
the proposed approach. The measured peak power conversion effi-
ciency of rectifier is 37.3% @−5 dBm input power level, across the
selected load was obtained after implementing the proposed matching
network design approach. The measured additional results to support
the proposed method is shown in Table 2. In the table the value of
Sdd11 (dB) and peak PCE are also appended where, it can be observed
that the PCE is decreasing with increase in the input RF frequency. The
reason for this pattern is mainly parasitics associated with the
measurement setup including the integrated implementation. This
behavior can also be verified from [8].
4. Conclusion
In this work, by using experimental approach a simple method has
been proposed which is useful to obtain the matching network for the
differential drive rectifier. Here, the L and C component values of the
matching network have been obtained for the differential rectifier by
configuring it as a CMOS LC-oscillator by swapping input and output
terminals. The difference in the matching frequency obtained by using
the proposed method is in acceptable range as it can be seen from the
measured plots. Apart from the proposed application, this method can
be used in transmitting exact matching frequency to an interrogator or
transmitters available in wireless sensor network.
Acknowledgment
This work is funded by the TEKES Project Dnro 3246/31/2014 of
the Tekes - the Finnish Funding Agency for Innovation Finland.
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