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![Design a device which writes to a register whenever
any address in its range is written
25
32-bit Reg
D[31:0]
Q[31:0]
EN
C
We are assuming APB only gets lowest 8 bits of address here…
What if we want to have the LSB of this register
control an LED?
PREADY
PWDATA[31:0]
PWRITE
PENABLE
PSEL
PADDR[7:0]
PCLK
LED](https://image.slidesharecdn.com/amba-230109084509-09a957de/75/amba-ppt-25-2048.jpg)
![Reg A should be written at address 0x00001000
Reg B should be written at address 0x00001004
26
32-bit Reg A
D[31:0]
Q[31:0]
EN
C
We are assuming APB only gets lowest 8 bits of address here…
32-bit Reg B
D[31:0]
Q[31:0]
EN
C
PREADY
PWDATA[31:0]
PWRITE
PENABLE
PSEL
PADDR[7:0]
PCLK](https://image.slidesharecdn.com/amba-230109084509-09a957de/75/amba-ppt-26-2048.jpg)
![Let’s say we want a device that provides data from
a switch on a read to any address it is assigned.
(so returns a 0 or 1)
28
Mr.
Switch
PWRITE
PENABLE
PSEL
PADDR[7:0]
PCLK
PREADY
PRDATA[32:0]](https://image.slidesharecdn.com/amba-230109084509-09a957de/75/amba-ppt-28-2048.jpg)
![Device provides data from switch A if address
0x00001000 is read from. B if address 0x00001004
is read from
29
Mr.
Switch
Mrs.
Switch
PWRITE
PENABLE
PSEL
PADDR[7:0]
PCLK
PREADY
PRDATA[31:0]](https://image.slidesharecdn.com/amba-230109084509-09a957de/75/amba-ppt-29-2048.jpg)
![All reads read from register, all writes write…
30
PWDATA[31:0]
PWRITE
PENABLE
PSEL
PADDR[7:0]
PCLK
PREADY
32-bit Reg
D[31:0]
Q[31:0]
EN
C
We are assuming APB only gets lowest 8 bits of address here…
PREADY
PRDATA[31:0]](https://image.slidesharecdn.com/amba-230109084509-09a957de/75/amba-ppt-30-2048.jpg)
![Verilog!
32
/*** APB3 BUS INTERFACE ***/
input PCLK, // clock
input PRESERN, // system reset
input PSEL, // peripheral select
input PENABLE, // distinguishes access phase
output wire PREADY, // peripheral ready signal
output wire PSLVERR, // error signal
input PWRITE, // distinguishes read and write cycles
input [31:0] PADDR, // I/O address
input wire [31:0] PWDATA, // data from processor to I/O device (32 bits)
output reg [31:0] PRDATA, // data to processor from I/O device (32-bits)
/*** I/O PORTS DECLARATION ***/
output reg LEDOUT, // port to LED
input SW // port to switch
);
assign PSLVERR = 0;
assign PREADY = 1;](https://image.slidesharecdn.com/amba-230109084509-09a957de/75/amba-ppt-32-2048.jpg)
![37
AHB-Lite signal definitions
• Global signals
– HCLK: the bus clock source (rising-edge triggered)
– HRESETn: the bus (and system) reset signal (active low)
• Master out/slave in
– HADDR[31:0]: the 32-bit system address bus
– HWDATA[31:0]: the system write data bus
– Control
• HWRITE: indicates transfer direction (Write=1, Read=0)
• HSIZE[2:0]: indicates size of transfer (byte, halfword, or word)
• HBURST[2:0]: indicates single or burst transfer (1, 4, 8, 16 beats)
• HPROT[3:0]: provides protection information (e.g. I or D; user or handler)
• HTRANS: indicates current transfer type (e.g. idle, busy, nonseq, seq)
• HMASTLOCK: indicates a locked (atomic) transfer sequence
• Slave out/master in
– HRDATA[31:0]: the slave read data bus
– HREADY: indicates previous transfer is complete
– HRESP: the transfer response (OKAY=0, ERROR=1)](https://image.slidesharecdn.com/amba-230109084509-09a957de/75/amba-ppt-37-2048.jpg)
![44
Transfers can be of four types (HTRANS[1:0])
• IDLE (b00)
– No data transfer is required
– Slave must OKAY w/o waiting
– Slave must ignore IDLE
• BUSY (b01)
– Insert idle cycles in a burst
– Burst will continue afterward
– Address/control reflects next transfer in
burst
– Slave must OKAY w/o waiting
– Slave must ignore BUSY
• NONSEQ (b10)
– Indicates single transfer or first transfer of
a burst
– Address/control unrelated to prior
transfers
• SEQ (b11)
– Remaining transfers in a burst
– Addr = prior addr + transfer size](https://image.slidesharecdn.com/amba-230109084509-09a957de/75/amba-ppt-44-2048.jpg)
![45
A four beat burst with master busy and slave wait
One wait state
added by slave
by asserting
HREADY low
Master busy
indicated by
HTRANS[1:0]](https://image.slidesharecdn.com/amba-230109084509-09a957de/75/amba-ppt-45-2048.jpg)
![46
Controlling the size (width) of a transfer
• HSIZE[2:0] encodes the size
• The cannot exceed the data bus
width (e.g. 32-bits)
• HSIZE + HBURST is determines
wrapping boundary for wrapping
bursts
• HSIZE must remain constant
throughout a burst transfer](https://image.slidesharecdn.com/amba-230109084509-09a957de/75/amba-ppt-46-2048.jpg)
![47
Controlling the burst beats (length) of a transfer
• Burst of 1, 4, 8, 16, and undef
• HBURST[2:0] encodes the type
• Incremental burst
• Wrapping bursts
– 4 beats x 4-byte words wrapping
– Wraps at 16 byte boundary
– E.g. 0x34, 0x38, 0x3c, 0x30,…
• Bursts must not cross 1KB
address boundaries](https://image.slidesharecdn.com/amba-230109084509-09a957de/75/amba-ppt-47-2048.jpg)
amba.ppt
- 1. 1 EECS 373 Design ofMicroprocessor-Based Systems Prabal Dutta University of Michigan AMBA: Advanced Microcontroller Bus Architecture AHB: AMBA High-performance Bus APB: Advanced Peripheral Bus Slides developed in part by Mark Brehob & Prabal Dutta
- 2. Busses: the gluethat connects the pieces 2 Timers Central Processing Unit Software Hardware Internal External System Buses AHB/APB ldr (read) str (write) ISA EECS 370 USART DAC/ADC Internal & External Memory GPIO/INT C Assembly Machine Code Interrupts bl (int)
- 3. Today… MMIO: Memory-Mapped I/Oreview AMBA: Advanced Microcontroller Bus Architecture APB: Advanced Peripheral Bus AHB: AMBA High-performance Bus 3
- 4. 4 Memory-Mapped I/O (MMIO) •I/O model in which the same address bus/space is used to – Do memory accesses (e.g. to RAM) – Do I/O operations (e.g. to I/O pins or peripheral registers) • Reading and writing memory addresses allows us to – Read peripheral state (e.g. value of an I/O pin or FSM’s DFF) – Issue peripheral commands (e.g. set an I/O pin or FSM’s state) • How? – Memory has an address and value – Can equate a pointer to desired address – Can set/get de-referenced value to change memory – Can control peripheral state in this way
- 5. 5 #define PBS_REG 0xB0000003 intisBlueButtonPressed() { return (*((uint32_t *)PBS_REG) & 0x00000004) >> 2; } Reading register bits with MMIO • How? – Let’s say that red, green, and blue pushbuttons are mapped to memory address 0xB0000003 at bits 0, 1, and 2, respectively – When pushed, we will read a ‘1’ from the corresponding bit – When released, we will read a ‘0’ from the corresponding bit Address Bit 31 24 23 16 15 8 7 210 0xB0000003-------- -------- -------- ----- – Must mask (and perhaps shift) to select target bits for reading
- 6. 6 #define LED_REG 0xB0000004 voidsetRedLed() { *((uint32_t *)LED_REG) |= 0x1; } void setGreenLed() { *((uint32_t *)LED_REG) |= 0x2; } Writing register bits with MMIO • How? – Let’s say that red, green, and blue LEDs are mapped to memory address 0xB0000004 at bits 0, 1, and 2, respectively – Writing a ‘1’ (‘0’) to the corresponding bit turns on (off) the LED Address Bit 31 24 23 16 15 8 7 210 0xB0000004-------- -------- -------- ----- – When updating (set/clear) bits, must preserve remaining contents – Use bitmask to select target bits for manipulation, e.g. #define LED_REG 0xB0000004 void clearRedLed() { *((uint32_t *)LED_REG) &= ~(0x00000001); } void clearBlueLed() { *((uint32_t *)LED_REG) &= ~(0x00000004); }
- 7. 7 Some useful Ckeywords • const – Makes variable value or pointer parameter unmodifiable – const foo = 32; • register – Tells compiler to locate variables in a CPU register if possible – register int x; • static – Preserve variable value after its scope ends – Does not go on the stack – static int x; • volatile – Opposite of const – Can be changed in the background – volatile int I;
- 8. Today… MMIO: Memory-Mapped I/Oreview AMBA: Advanced Microcontroller Bus Architecture APB: Advanced Peripheral Bus AHB: AMBA High-performance Bus 8
- 9. Advanced Microcontroller BusArchitecture (AMBA) - Advanced/AMBA High-performance Bus (AHB) - Advanced Peripheral Bus (APB) AHB • High performance • Pipelined operation • Burst transfers • Multiple bus masters • Split transactions APB • Low power • Latched address/control • Simple interface • Suitable of many peripherals 9
- 10. 10 Actel SmartFusion system/busarchitecture
- 11. Today… MMIO: Memory-Mapped I/Oreview AMBA: Advanced Microcontroller Bus Architecture APB: Advanced Peripheral Bus AHB: AMBA High-performance Bus 11
- 12. 12 APB: a simplebus that is easy to work with • Low-cost • Low-power • Low-complexity • Low-bandwidth • Non-pipelined • Ideal for peripherals
- 13.
- 14. 14 APB bus statemachine • IDLE – Default APB state • SETUP – When transfer required – PSELx is asserted – Only one cycle • ACCESS – PENABLE is asserted – Addr, write, select, and write data remain stable – Stay if PREADY = L – Goto IDLE if PREADY = H and no more data – Goto SETUP is PREADY = H and more data pending Setup phase begins with this rising edge Setup Phase Access Phase
- 15. 15 APB signal definitions •PCLK: the bus clock source (rising-edge triggered) • PRESETn: the bus (and typically system) reset signal (active low) • PADDR: the APB address bus (can be up to 32-bits wide) • PSELx: the select line for each slave device • PENABLE: indicates the 2nd and subsequent cycles of an APB xfer • PWRITE: indicates transfer direction (Write=H, Read=L) • PWDATA: the write data bus (can be up to 32-bits wide) • PREADY: used to extend a transfer • PRDATA: the read data bus (can be up to 32-bits wide) • PSLVERR: indicates a transfer error (OKAY=L, ERROR=H)
- 16. APB bus signalsin action • PCLK – Clock • PADDR – Address on bus • PWRITE – 1=Write, 0=Read • PWDATA – Data written to the I/O device. Supplied by the bus master/processor. 16
- 17. APB bus signals •PSEL – Asserted if the current bus transaction is targeted to this device • PENABLE – High during entire transaction other than the first cycle. • PREADY – Driven by target. Similar to our #ACK. Indicates if the target is ready to do transaction. Each target has it’s own PREADY 17
- 18. 18 A write transferwith no wait states Setup phase begins with this rising edge Setup Phase Access Phase
- 19. 19 A write transferwith wait states Setup phase begins with this rising edge Setup Phase Access Phase Wait State Wait State
- 20. 20 A read transferwith no wait states Setup phase begins with this rising edge Setup Phase Access Phase
- 21. 21 A read transferwith wait states Setup phase begins with this rising edge Setup Phase Access Phase Wait State Wait State
- 22. Example setup • Wewill assume we have one bus master “CPU” and two slave devices (D1 and D2) – D1 is mapped to 0x00001000-0x0000100F – D2 is mapped to 0x00001010-0x0000101F
- 23. CPU stores tolocation 0x00001004 with no stalls 23 D1 D2
- 24. Writes Let’s do somehardware examples! 24
- 25. Design a devicewhich writes to a register whenever any address in its range is written 25 32-bit Reg D[31:0] Q[31:0] EN C We are assuming APB only gets lowest 8 bits of address here… What if we want to have the LSB of this register control an LED? PREADY PWDATA[31:0] PWRITE PENABLE PSEL PADDR[7:0] PCLK LED
- 26. Reg A shouldbe written at address 0x00001000 Reg B should be written at address 0x00001004 26 32-bit Reg A D[31:0] Q[31:0] EN C We are assuming APB only gets lowest 8 bits of address here… 32-bit Reg B D[31:0] Q[31:0] EN C PREADY PWDATA[31:0] PWRITE PENABLE PSEL PADDR[7:0] PCLK
- 27. Reads… 27 The key thinghere is that each slave device has its own read data (PRDATA) bus! Recall that “R” is from the initiator’s viewpoint—the device drives data when read.
- 28. Let’s say wewant a device that provides data from a switch on a read to any address it is assigned. (so returns a 0 or 1) 28 Mr. Switch PWRITE PENABLE PSEL PADDR[7:0] PCLK PREADY PRDATA[32:0]
- 29. Device provides datafrom switch A if address 0x00001000 is read from. B if address 0x00001004 is read from 29 Mr. Switch Mrs. Switch PWRITE PENABLE PSEL PADDR[7:0] PCLK PREADY PRDATA[31:0]
- 30. All reads readfrom register, all writes write… 30 PWDATA[31:0] PWRITE PENABLE PSEL PADDR[7:0] PCLK PREADY 32-bit Reg D[31:0] Q[31:0] EN C We are assuming APB only gets lowest 8 bits of address here… PREADY PRDATA[31:0]
- 31. Things left out… •There is another signal, PSLVERR (APB Slave Error) which we can drive high if things go bad. – We’ll just tie that to 0. • PRESETn – Active low system reset signal – (needed for stateful peripherals) • Note that we are assuming that our device need not stall. – We could stall if needed. • I can’t find a limit on how long, but I suspect at some point the processor would generate an error. 31
- 32. Verilog! 32 /*** APB3 BUSINTERFACE ***/ input PCLK, // clock input PRESERN, // system reset input PSEL, // peripheral select input PENABLE, // distinguishes access phase output wire PREADY, // peripheral ready signal output wire PSLVERR, // error signal input PWRITE, // distinguishes read and write cycles input [31:0] PADDR, // I/O address input wire [31:0] PWDATA, // data from processor to I/O device (32 bits) output reg [31:0] PRDATA, // data to processor from I/O device (32-bits) /*** I/O PORTS DECLARATION ***/ output reg LEDOUT, // port to LED input SW // port to switch ); assign PSLVERR = 0; assign PREADY = 1;
- 33. Actel/Microsemi implementation ofCoreAPB3 33 • ARM APB spec is silent about sharing signals – PSEL, PREADY, PRDATA are shared – Hence, every peripheral needs its own decode logic…which is cumbersome • Actel CoreAPB3 (and other) module(s) help • Allocates per-slave signals – PSEL, PREADY, PRDATA, PSLVERR broken out – CoreAPB3 supports 16 slaves – Performs address decoding for PSEL – De-multiplexes PSEL signal – Multiplexes PREADY, PRDATA, PSLVERR
- 34. Today… MMIO: Memory-Mapped I/Oreview AMBA: Advanced Microcontroller Bus Architecture APB: Advanced Peripheral Bus AHB: AMBA High-performance Bus 34
- 35. 35 AHB-Lite supports singlebus master and provides high-bandwidth operation • Burst transfers • Single clock-edge operation • Non-tri-state implementation • Configurable bus width
- 36. 36 AHB-Lite bus master/slaveinterface • Global signals – HCLK – HRESETn • Master out/slave in – HADDR (address) – HWDATA (write data) – Control • HWRITE • HSIZE • HBURST • HPROT • HTRANS • HMASTLOCK • Slave out/master in – HRDATA (read data) – HREADY – HRESP
- 37. 37 AHB-Lite signal definitions •Global signals – HCLK: the bus clock source (rising-edge triggered) – HRESETn: the bus (and system) reset signal (active low) • Master out/slave in – HADDR[31:0]: the 32-bit system address bus – HWDATA[31:0]: the system write data bus – Control • HWRITE: indicates transfer direction (Write=1, Read=0) • HSIZE[2:0]: indicates size of transfer (byte, halfword, or word) • HBURST[2:0]: indicates single or burst transfer (1, 4, 8, 16 beats) • HPROT[3:0]: provides protection information (e.g. I or D; user or handler) • HTRANS: indicates current transfer type (e.g. idle, busy, nonseq, seq) • HMASTLOCK: indicates a locked (atomic) transfer sequence • Slave out/master in – HRDATA[31:0]: the slave read data bus – HREADY: indicates previous transfer is complete – HRESP: the transfer response (OKAY=0, ERROR=1)
- 38. 38 Key to timingdiagram conventions • Timing diagrams – Clock – Stable values – Transitions – High-impedance • Signal conventions – Lower case ‘n’ denote active low (e.g. RESETn) – Prefix ‘H’ denotes AHB – Prefix ‘P’ denotes APB
- 39. 39 Basic read andwrite transfers with no wait states Pipelined Address & Data Transfer
- 40. 40 Read transfer withtwo wait states Two wait states added by slave by asserting HREADY low Valid data produced
- 41. 41 Write transfer withone wait state One wait state added by slave by asserting HREADY low Valid data held stable
- 42. 42 Wait states extendthe address phase of next transfer One wait state added by slave by asserting HREADY low Address stage of the next transfer is also extended
- 43. Today… MMIO: Memory-Mapped I/Oreview AMBA: Advanced Microcontroller Bus Architecture APB: Advanced Peripheral Bus AHB: AMBA High-performance Bus - Low-level details included for completeness - But we’ll skip most of these details 43
- 44. 44 Transfers can beof four types (HTRANS[1:0]) • IDLE (b00) – No data transfer is required – Slave must OKAY w/o waiting – Slave must ignore IDLE • BUSY (b01) – Insert idle cycles in a burst – Burst will continue afterward – Address/control reflects next transfer in burst – Slave must OKAY w/o waiting – Slave must ignore BUSY • NONSEQ (b10) – Indicates single transfer or first transfer of a burst – Address/control unrelated to prior transfers • SEQ (b11) – Remaining transfers in a burst – Addr = prior addr + transfer size
- 45. 45 A four beatburst with master busy and slave wait One wait state added by slave by asserting HREADY low Master busy indicated by HTRANS[1:0]
- 46. 46 Controlling the size(width) of a transfer • HSIZE[2:0] encodes the size • The cannot exceed the data bus width (e.g. 32-bits) • HSIZE + HBURST is determines wrapping boundary for wrapping bursts • HSIZE must remain constant throughout a burst transfer
- 47. 47 Controlling the burstbeats (length) of a transfer • Burst of 1, 4, 8, 16, and undef • HBURST[2:0] encodes the type • Incremental burst • Wrapping bursts – 4 beats x 4-byte words wrapping – Wraps at 16 byte boundary – E.g. 0x34, 0x38, 0x3c, 0x30,… • Bursts must not cross 1KB address boundaries
- 48. 48 A four beatwrapping burst (WRAP4)
- 49. 49 A four beatincrementing burst (INCR4)
- 50. 50 An eight beatwrapping burst (WRAP8)
- 51. 51 An eight beatincrementing burst (INCR8) using half-word transfers
- 52. 52 An undefined lengthincrementing burst (INCR)
- 53. 53 Multi-master AHB-Lite requires amulti-layer interconnect • AHB-Lite is single-master • Multi-master operation – Must isolate masters – Each master assigned to layer – Interconnect arbitrates slave accesses • Full crossbar switch often unneeded – Slaves 1, 2, 3 are shared – Slaves 4, 5 are local to Master 1
- 54.