An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full Adder

An Explicit Cell-Based Nesting Robust
Architecture and Analysis of Full Adder
Bandan Kumar Bhoi, Tusarjyoti Das, Neeraj Kumar Misra
and Rashmishree Rout
Abstract Moving towards micrometre scale to nanometre scale device shrinks down
emerging nanometre technology such as quantum-dot cellular automata as a nesting
success. The introduced architecture is robust where the explicit design of full adder
andfullsubtractionusesforEx-ORdesign.AnewarchitectureofEx-ORbasedonone
majority gate is proposed, which its most optimized architecture and its placement
of cells from the novel design. The analysis based on simulation showed that the
introduced Ex-OR and full adder makes only 11 and 46 cells count, respectively. In
proposed Ex-OR design, first output is received with no any latency which can be a
suitable design for implementation of the high-speed full adder design. In addition,
powerestimationresultsareobtainedaftersimulationofproposeddesignsinQCAPro
tool. Therefore, the novel designs improve the energy dissipation parameters such
as mean leakage energy dissipation, mean switching energy dissipation and total
energy dissipation 75, 11.28 and 82.19% in comparison with the most robust design
in existing.
Keywords Nanometre scale · Full adder · Quantum-dot cellular automata
Complexity · Majority gate
1 Introduction
Quantum-dot cellular automata (QCA) is an emerging technology, which has the fea-
tures to overcome the limitation of CMOS technology in scaling [1]. This promising
technology is very simple as its basic building block in a QCA cell, where interaction
between cells is purely Columbia rather than transportation of charge. Hence, there
B. K. Bhoi (B) · T. Das · R. Rout
Department of Electronics & Telecommunication, Veer Surendra Sai
University of Technology, Burla 768018, India
e-mail: bkbhoi_etc@vssut.ac.in
N. K. Misra
Bharat Institute of Engineering and Technology, Hyderabad, India
© Springer Nature Singapore Pte Ltd. 2019
A. Khare et al. (eds.), Recent Trends in Communication, Computing,
and Electronics, Lecture Notes in Electrical Engineering 524,
https://doi.org/10.1007/978-981-13-2685-1_52
547

548 B. K. Bhoi et al.
is absent of leakage current. This technology also provides excellent optimization for
complex circuits. Any Boolean function can be implemented by a different arrange-
ment of these cells in QCA Technology [2–4]. Hence, QCA is becoming one of the
most promising areas of research in the field of the era of nanoelectronics.
In this work efficient 1-bit, full adder is introduced and analyses the performance
parameters. The full adder uses two Ex-OR gates [5, 6], which takes three inputs,
namely A, B and Ci. These two Ex-OR gates are connected in series that gives the
final sum output (SA⊕B⊕Ci), and another three number inputs majority gate
is used to produce the carry out (CoAB+BC+AC). The Ex-OR gate used here
is the most efficient one as it requires only 11 number of QCA cells and occupies
a very small area of 0.02 µm2
. This Ex-OR gate comprises of only one two-input
majority gate, and an inverter is used to design the proposed circuit that occupies an
area of 0.06 µm2
. The newly introduced design is a coplanar type circuit. The logical
operation of the proposed work is verified using QCADesigner Simulator tool [6]. In
this design, the carry out is produced without having any delay and the sum output is
produced after one clock delay. Hence, the proposed 1-bit full adder is very efficient
in the area, cell count and clock delay.
The remaining part of this paper is arranged in the following manner. Section 2
describes the basic idea and operating principle of QCA. Section 3 shows the QCA
implementation and simulation result of the proposed full adder circuit. The com-
parison result of the proposed and other existing full adder circuits is tabulated in
Sect. 4. Finally, the paper is concluded in Sect. 5.
2 Basics of QCA
In a QCA circuit design, the basic component is a QCA cell. The QCA cell is a
square box having four quantum dots located at its four corners. Each cell has two
electrons placed in two quantum dots those are diagonally opposite to each other
because of coulombs interaction. The cells have two basic binary states, i.e. logic
‘0’ and logic ‘1’ which is determined by the location of electrons. Unlike CMOS,
transportation of charge between cells does not occur in QCA. It is purely Columbia
in case of QCA. State of a cell at a given time is determined by the state of its nearby
cells during a previous clock cycle.
In QCA, there are four clock zones, namely clock-zone 0, clock-zone 1, clock-
zone 2, clock-zone 3. Clock-zone 0 is referred as SWITCH state and is indicated by
green colour. Similarly, clock-zone 1 is referred as HOLD and indicated by magenta
colour, clock-zone 2 is referred as RELEASE and indicated by blue colour, and
clock-zone 3 is referred as RELAX and indicated by white colour. Two types of
crossovers are allowed in QCA design, namely coplanar crossover and multilayer
crossover. Coplanar crossover involves only a single layer and uses two types of
cells, i.e. regular cell and rotated cell, whereas the multilayer crossover involves
more layers of cells.

An Explicit Cell-Based Nesting Robust Architecture and Analysis … 549
Fig. 1 QCA preliminary a QCA cell. b Majority gate. c Inverter d QCA wire
2.1 Basic QCA Elements
By doing various physical arrangements of several numbers of QCA cells, we can
get different QCA devices such as (a) QCA wire (b) QCA inverter (c) QCA majority
gates.
Binary logic ‘0’ and logic ‘1’ are represented by QCA cells which are represented
in Fig. 1a.
QCA Majority Gate: A three-input majority gate can be implemented by arranging
the cells in the way shown in Fig. 1b. Majority gate gives the majority of inputs at
its output. The output function of the majority gate is M(A, B, C)AB+BC+AC
where A, B, C are the three inputs. If we set any of its inputs to logic ‘0’ or logic ‘1’
then the majority gate will function as AND gate and OR gate, respectively. Then by
connecting a QCA inverter at its output, we can achieve NAND and NOR gate also.
Therefore, by using this majority gate we can design any arithmetic circuit.
QCA inverter: To design a QCA inverter, cells should be arranged in the fashion
shown in Fig. 1c. According to the working principle of a NOT gate or an inverter,
it flips the provided input and gives its complement as output.
QCA wire: It is the series arrangement of QCA cells (Fig. 1d). In a QCA wire,
the cells are clocked in a regular manner.
3 Proposed Work
In this section delay, efficient full adder circuit has been detailed. This full adder is
implemented using an efficient Ex-OR gate. The Ex-OR gate used here comprises
only 11 number of cells. It also requires an area of 0.02 µm2
. The Ex-OR gate is
made up of only one majority gate and an inverter. The proposed design of logic
design, cell layout, and simulation result are presented in Fig. 2a, b, c, respectively.
Here in the design of the 1-bit full adder circuit, we have used two Ex-OR gates.
These two Ex-OR gates are cascaded, and the output of this cascade connection
serves as the sum of the full adder. Another majority gate is used to implement the
carry out of the full adder circuit. So the proposed design comprises a total of three
majority gates and two inverters. The full adder circuit requires only 46 number of
cells and an area of 0.06 µm2
. The logical diagram, QCA structure and simulation
result of the full adder are shown in Fig. 3a, b, c, respectively.

Fig. 2 The proposed
Ex-OR. a logical truth table
b QCA implementation. c
Simulation result
This simulation result implemented using QCADesigner shows the functionality
result of the proposed 1-bit full adder. Here, from the output waveform shown in
Fig. 3c, it can be observed that the carry out (Co) of the full adder is produced
without any clock delay, whereas the sum output (S) is having a single clock delay.
4 Comparison
The proposed 1-bit full adder is compared with various existing full adders on the
basis of parameters such as area, cell count, delay, number of majority gates and
inverters used. The comparison result is shown in Table 2. In few cases, present full
adder designs have lesser area [7], but in overall, the proposed one has better perfor-
mance than others, which is clearly indicated by the tabulation. So we can conclude
that the proposed design has higher efficiency than the existing circuits. For energy
dissipation, related parameters are estimated by QCAPro tool by the QCA design.

Fig. 3 The proposed full adder. a Block diagram. b QCA structure. c Simulation result
Table 1 presents the energy-related parameters such as mean leakage energy dissi-
pation, mean switching energy dissipation and total energy dissipation. Total energy
dissipation is the sum of mean leakage and mean switching. The extracted energy
dissipation-related parameters are estimated by distinct energy levels such as 0.5, 1,
1.5 Ek and the 2 K selected for operating temperature. Further, the energy dissipation
thermal map of Ex-OR and full adder designs at a 2 K temperature and 0.5 Ek is
presented in Fig. 4a, b, respectively. In thermal map, darker the cell is presented
the more power dissipation in the design. Table 1 presents the energy dissipation
comparisons parameters results comparison to existing designs. These tables can
evidence the efficient energy dissipation parameters of our introduced designs. As
per comparisons table evidence that the design achieves the lower energy dissipa-
tion at different tunnelling energy level in comparisons to the existing designs. The

Fig. 4 Thermal layout map of proposed designs with 0.5 Ek at 2 K temperature. a Ex-OR. b Full
adder
better energy dissipation results are achieved by nonrotating cell and no-crossover
in the proposed design. This is the cause to achieve lower energy dissipation. In a
real comparison of energy dissipation parameters result in existing and presented
design in Table 1, the proposed design achieves on mean leakage energy dissipation,
mean switching energy dissipation and total energy dissipation 75, 11.28 and 82.19%
less energy as compared to existing at 0.5 Ek, respectively, whereas mean leakage
energy dissipation, mean switching energy dissipation and total energy dissipation
77.51, 85.16 and 81.34% less energy as compared to existing at 1 Ek, respectively,
similarly mean leakage energy dissipation, mean switching energy dissipation and
total energy dissipation 78.72, 85.71 and 81% less energy as compared to existing
at 1 Ek, respectively.
5 Conclusion
In this article, the new architecture of Ex-OR was presented with the intention of
being robust and no latency-based design. In this way, robust and no latency-based
Ex-OR design was proposed to be used as an efficient full adder design. Further,
the explicit cell approach was introduced in QCA for the physical realization of the
robust full adder design. The comparative analysis of the new full adder with the prior
designs showed that the introduced are optimized in different parameters intention
to the complexity, area and latency. For future work in this way, the new architecture
of Ex-OR and full adder modules can be extended for synthesizing robust multiplier,
and divider unit.

Table
1
Power
estimation
comparison
results
New
Design
Mean
Leakage
energy
dissipation
(eV)
0.5,
1,
1.5
Ek
Mean
switching
energy
dissipation
(eV)
0.5,
1,
1.5
Ek
Mean
Energy
consumption
(eV)
0.5,
1,
1.5
Ek
Ex-OR
0.00408
0.01049
0.01733
0.00748
0.00625
0.00523
0.01156
0.01674
0.02256
References
[8]
0.068
0.209
0.376
0.269
0.236
0.203
0.337
0.445
0.579
FA
0.017
0.047
0.080
0.042
0.035
0.029
0.060
0.083
0.110

Table 2 Comparison of proposed QCA design and existing designs
Full adders # Maj # Inverter Area (in
µm2)
Cell count Latency Layer type
Reference
[7]
3 2 0.038 52 1 clk Coplanar
Reference
[9]
3 1 0.127 53 1 clk Multilayer
Reference
[10]
3 2 0.097 102 2 clk Coplanar
Reference
[11]
3 2 0.16 145 – Coplanar
Reference
[12]
2 (one 3i/p,
one 5i/p)
2 0.16 145 2 clk Multilayer
Reference
[13]
3 1 0.07 70 1 clk Multilayer
Proposed 3 2 0.06 46 1 clk Coplanar
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