Analog Layout basic Analog Layout basic Analog Layout basic

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Analog Layout Training
References used in creating these Analog Layout Training Methods:
“The Art of Analog Layout” by Alan Hastings
“Digital Integrated Circuits” by Jan M. Rabaey

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Table of Contents: Page
What is analog layout 4
Transistor Matching 5
Transistor Matching/dummy devices 11
Transistor Matching/Proximity and Origin of Devices 15
Transistor Matching/Common Centroid 20
Transistor Matching/Important Principles to Follow 29
Noise Considerations 35
Noise Considerations/Latch Up & Guard Rings 37
Noise Considerations/Cross Talk 40
Noise Considerations/Shielding 41
Noise Considerations/Signal Balancing 44
Noise Considerations/Nwells as Shields 46
Noise Considerations/Shared Diffusion 47
General Analog Layout Guidelines 50

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Analog Layout:
Why is this type of layout different from other layout?
Analog signals are very sensitive to noise and
parasitics. The analog signal will propagate any noise
that has been attached to it. The intent of the analog
circuit is to propagate a signal without or with little
distortion/noise associated with it. Special layout
techniques have to be used to ensure the analog signal’s
integrity will be kept.
Notes…analog layout usually involves more high
precision matching than traditional layout.

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Transistor Matching:
Doping diagram next page.
The n-type transistor process goes like this:
Heavily doped n-type (arsenic) source and drain regions are
implanted (or diffused) into a lightly doped p-type (boron) substrate.
A thin layer of silicon dioxide (SiO2) is grown over the region
between the source and drains and is covered by a conductive
material, most often polycrystalline silicon (or polysilicon, for short).
The conductive material forms the gate of the transistor.
Neighboring devices are insulated from each other with the aid of a
thick layer of SiO2 (called the field oxide) and a reverse-biased np-
diode formed by adding an extra p+ region, called the channel-stop
implant (or field implant).

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Doping diagram

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A variety of two-dimensional effects can cause the effective sizes of
components to differ from the sizes of the layout masks when
integrated components are processed using lithographic techniques
(doping/implant). Well area will typically be larger than its mask due
to the lateral diffusion that occurs not just during the ion
implantation but also during later high-temperature steps. Another
effect, known as over etching, occurs when layer such as polysilicon
or metal are being etched. Over etching can cause the polysilicon
layer to be smaller than the corresponding mask layout. A third
effect is when the field implant under the field-oxide causes the
effective substrate doping to be greater at the sides of the
transistors than elsewhere. Even if the implant angle used is zero,
the angle is zero for only part of the wafer. Where it isn’t zero,
devices with different source and drain orientations may not be as
optimally matched as they could be. This increased doping raises
the effective transistor threshold voltage near the sides of the
transistors and therefore decreases the channel-charge density at
the edges. The result is that the effective width of the transistor is
less than the width drawn on the layout mask.

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original
drawing
gate degrades in
manufacturing fix by new
design rules
A B C

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The Source and Drain of the transistor can differ in resistance and
capacitance when the “real” silicon is created due to the contact to
poly spacing (view B page 8). By increasing the space of the
diffusion contacts to poly, the transistor’s source to drain will be more
closely matched.
This is a good practice for very high precision layout. The capacitance
and resistance will be increased when following this recommendation,
but this is ok because most analog layout is typically composed of
slower devices.

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Other effects caused by doping characteristics include those
caused by boundary conditions of an object, the size of the
opening in a protective layout through which etching occurs,
and the unevenness of the surface of the microcircuit.
Matching size error effects is done mainly by making larger
objects out of several unit-sized components connected
together. Also, for best accuracy, the boundary conditions
around all objects should be matched, even when this means
adding extra unused components (dummy devices).

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Dummy Devices:
Dummy devices are devices that are added to the layout to
decrease matching errors that occur during the doping
process of the device.
When laying out the device, all fingers should be inside
fingers only. Outside, or dummy, fingers would only be
included for better matching accuracy and would have no
other function. The gates of these dummy fingers are
normally connected to the most negative power-supply
voltage to ensure they are always turned off (or they are
connected to the positive power supply in the case of p-
channel transistors). The source/drain are normally tied to
the same power supply as the gate.
Diagram shown on next page.

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Dummy Devices Diagram: Poly dummies added to each end
to maintain device matching during planaration
Poly dummy Poly dummy

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Dummy Devices Diagram:

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Proximity and Origin of Devices:
Source and Drain orientation of matched devices must by the
same.
This also helps match diffusion capacitance on these
source/drain nodes. A requirement of matching devices is to
match in all their aspects, including the source and drain
junction capacitance. A horizontal transistor cannot be well
matched to a vertical one.
Both transistors orientation must be the same and the drains
must be in the same orientation also. If the drain of one
transistor is at the right side, the drain of the matching
transistor must also be at the right side or they are not
matched well.
S S S S
D D D D

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Proximity and Origin of Devices:
Devices are often legged for speed. More legs lesson capacitance.
The amount of legs of a device is always even and each leg of equal
size to the other legs with the connections to VCC/VSS on the
outsides. This is to allow minimum node
capacitance.
Inter-digitated Nor gate

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The source and the drain of the matching transistors need to “see”
the same surrounding field oxide region. This is difficult sometimes
when the source/drain of one transistor is being shared and the
matched transistor isn’t sharing source/drain region. This would be
one example of a time to add a dummy device so the matching
transistors are seeing the same field region. This will require
additional layout area to meet the optimal matching of the
transistors.
This transistors “sees” diff and
poly
on both east and west sides
This transistor does
not “see” diff and
poly
on the east side

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Common Centroid Style Layout
Why? The Gradient-induced (differences across the die due to
temperature, distance, etc.) mismatches can be minimized by
reducing the distance between the centroids (center of mass) of the
matched devices. Some types of layout can actually reduce the
distance between the centroids to zero. These common-centroid
layouts can entirely cancel the effects of long-range variations as
long as these are linear functions of distance. The more compact
the common-centroid layout can be made, the less susceptible it
becomes to nonlinear (non-constant output with respect to the
input) gradients. The best layouts for transistors combine exact
alignment of the centroids with compactness.
MOS transistors are usually divided into segments, or fingers, to
allow the construction of a compact array. The simplest types of
arrays involve the placement of multiple device fingers in parallel. If
these fingers are properly interdigitated, then the centroids of the
matched devices will align at a point midway along the axis of
symmetry bisecting the array.

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This layout uses the interdigitation patterns ABBA to ensure exact
alignment of the centroids. If source and drain fingers are denoted
by subscripts, then the pattern becomes dAsBdBsAd . Notice that
the A-segment on the right has its drain on the right, while the A-
segment on the left has its drain on the left. Similarly, the B-segment
on the right has its source on the right, while the B-segment on the
left has its source on the left. Each transistor thus contains one
segment oriented in either direction.
Suppose one transistor consists entirely of segments with drains on
the left, while a second transistor consists entirely of segment with
drains on the left, while a second transistor consists entirely of
segments with drains on the right. If left-oriented and right-oriented
segments differ in any way, then the two transistors will not match.
If both transistors consist entirely of segments oriented in the same
direction, then the effect of the orientation on each transistor will be
the same. If each transistor consists of an equal number of left-
oriented and right-oriented segments, then the effects of orientation
will cancel and the transistors will again match.

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Common Centroid
Style Layout
Gate names are:
i10 & i7 on the left
differential pair
(i10 i7 i7 i10
i7 i10 i10 i7)
&
i07 & i38 on the right
differential pair
(i38 i07 i07 i38
i07 i38 i38 i07)

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The interdigitation patterns for common-centroid transistor arrays
are often difficult to construct, as it is not easy to satisfy all the
rules of common-centroid layout. The RULES are as follows:
#1 Coincidence: The centroids of the matched devices should at
least approximately coincide. Ideally, the centroids should
exactly coincide. Definition of coincide:
To occupy exactly corresponding or equivalent positions on a scale
or in a series.
#2 Symmetry: The array should be symmetric around both the X-
and Y-axes. Ideally, this symmetry should arise from the
placement of segments in the array and not from the symmetry of
the individual segments themselves.
#3 Dispersion: The array should exhibit the highest possible degree
of dispersion; in other words, the segments of each device
should be distributed throughout the array as uniformly as
possible.

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#4 Orientation: Each matched device should consist of an equal
number of segments oriented in either direction; more generally,
the matched devices should posses equal chirality. An example
of Chirality is: each transistor consists of an equal number of
left-oriented and right-oriented segments, then the effects of
orientation will cancel and the transistors will again match.
#5 Compactness: The array should be as compact as possible.
Ideally, it should be nearly square.
“Common Centroid Layout” diagram next page

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1. Shared Diffusion – minimize capacitance on Node Z
2. All Routing is Balanced – Symmetry
3. Minimized number of bends/crossovers/corners
4. Same Number of contacts/vias
5. Criss-cross and perfect matching & balancing
in capacitance and routing length.
6. Keep amount if crossovers the same
Find the problem with
crossover
matching in this picture.

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Some Examples of a Common Centroid array patterns:
d = drain s = source
A/B = transistors A/B/C = transistors
dAsBdBsAd
dBsAdAsBd
dAsBdBsAd
dBsAdAsBd
dAsBdBsAd
dBsAdAsBd
dAsBdBsAdAsBdBsAd
dBsAdAsBdBsAdAsBd
dAsBdBsAdAsBdBsAd
dBsAdAsBdBsAdAsBd
dAsBdBsAdAsBdBsAd
dBsAdAsBdBsAdAsBd
ABCCBA
CBAABC
ABCCBAABC
CBAABCCBA
ABCCBAABC
CBAABCCBA
ABCCBAABC
ABCCBAABC
CBAABCCBA
CBAABCCBA
ABCCBAABC

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The most important principles of transistor matching:
1. Use identical finger geometries - Transistors fingered with same widths and
lengths as all other fingers.
2. Use large active areas: Device size will be larger than digital layout, you will
need more area for matching purposes.
Analog
layout
Digital
layout

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3. Orient transistors in the same direction.
Not the same orientation
Mirror images
same orientation

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4. Place transistors in close proximity.
5. Keep the layout of the matched transistors as compact as possible.
6. Where practical, use common-centroid layouts.
7. Place dummy segments on the ends of arrayed transistors.
Check to see that
symmetry, (shape, balance)
uniformity, (sameness)
and alignment (line up)
are identical.
Make sure all poly, diff.,
contacts, vias, etc. are on
the same plane of symmetry.

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8. Place transistors in areas of low stress gradients – they should reside at
least 10 mils (250um) away from any side of the die. The stress distribution
reaches a maximum in the die corners, so avoid placing any matched
transistors near corners.

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11. Place precisely matched transistors on axes of symmetry of the die. The
axis of symmetry of the array should align with one of the two axis of
symmetry of the die.
12. Connect gate fingers using metal straps rather than poly for moderately or
precisely matched transistors.
13. Use thin-oxide devices in preference to thick-oxide devices. The transistors
with thinner gate oxide generally exhibit better matching characteristics than
those with thick gate oxides.
14. Consider using NMOS transistors rather than PMOS transistors. NMOS
transistors generally match better than PMOS transistors.

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Noise Considerations:
Well/Substrate Taps vt Variation:
N-Well contacts should be no more that 10 microns to the farthest P-
diffusion and should be as large and as frequent as empty N-Well area
permits. P-substrate contacts should also be made as frequently as
empty area permits. These well and substrate contacts should not
violate, but be used to compliment any dummy diffusion necessary to
balance diffusion near the matched transistors.

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Well/Substrate Taps vt Variation:
By maximizing the number of well and substrate contacts, the gate
threshold shifting due to substrate voltage shifting will be minimized.
Gate threshold voltage is when a voltage is applied to the gate that is
larger than a given value called the threshold voltage Vt, a conducting
channel is formed between drain and source. The threshold voltage
(Vt) has a positive value for a typical NMOS device, while it is negative
for a normal PMOS transistor. The voltage at which the channel just
begins to form is called the threshold voltage Vt. For an NMOS
transistor this voltage is ~.7V and for a PMOS transistor this voltage is
typically ~-.7V.
Parasitics: Built-in characteristics of semiconductor layers including
metals that are usually resistive and capacitive in nature. Their effects
increase as device dimensions are reduced. Parasitics introduce
noise on the circuit behavior and are responsible for a number of
different types of electrical failures.

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Latch Up: Where the combination of wells and substrates results in the
formation of parasitic n-p-n-p structures. Triggering these thyristor-like devices
leads to a shorting of the VDD and VSS lines, usually resulting in a destruction
of the chip, or at best a system failure that can only be resolved by power-
down. When one of the transistors gets forward biased (due to current flowing
through the well, or substrate), it feeds the base of the other transistor. This
positive feedback increases the current until the circuit fails or burns out. To
avoid latchup, the resistances Rnwell and Rpsubs should be minimized. This
can be achieved by providing numerous wells and substrate contacts, placed
close to the source connections of the NMOS/PMOS devises. Devices carrying
a lot of current (such as transistors in the I/O drivers) should be surrounded by
guard rings. Multiple well and substrate contacts supplemented with guard
rings help avoid the onset of this destructive effect.

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Cross Talk: DEFINITION:
An unwanted coupling from a neighboring signal wire to a network node
introduces an interference that is generally called cross talk. The resulting
disturbance acts as a noise source and can lead to hard-to-trace intermittent
errors, since the injected noise depends upon the transient (impermanent,
temporary, transitory) value of the other signals routed in the neighborhood. In
integrated circuits, this intersignal coupling can be both capacitive and
inductive, shown in Figure 3.1. Capacitive cross talk is the dominant effect at
current switching speeds. Capacitive crosstalk between signals on the same
layer can be reduced by keeping the distance between the wires large enough
or by inserting a shielding wire-GND or VDD-between the two signals.
This effectively turns the interwire capacitance into a capacitance-to-ground and
eliminates interference.

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Shielding: Technique used to avoid cross talk
•Minimum of 2X – 3X (min. space) from signal to be shielded
•4X minimum metal for vss shield
•3X minimum metal for signal route
•Increase vss shield between shielded signals to 1+ microns

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Shielding:
Green wire represents metal 2 (M2)
Blue wire represents metal 1 (M1)
The shielded signal is shielded in both M2 and
M1.
The shield should be power or ground depending
on the signal reference.
Shielded Signal
shield
shield

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Shielded
signal
Shield
Shield
Shield
Shield M3 -
pink
Shield
Shield
Shielded
signal
Shield
Shield
Shielded signal pink M3
Shield M3 -
pink
Cross Talk: Signal Shielding techniques used to avoid cross talk.
The shielding signal is shielded in M2 and M3
The shield width should exceed the width of the signal it’s shielding to
avoid fringe capacitance.

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Signal Balancing

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Signal Balancing

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Guard rings for shielding ..
Nwells as Shields: reduces substrate noise
layout from PLL loop filter cap
Pink layer is
Solid
NWELL

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Shared Diffusion: Transistors with even number of sections always
contain odd numbers of source/drain fingers. Such transistors are
usually constructed with source fingers at either end. Not only does
this allow the use of abutting backgate contacts on either or both
ends, but it also reduces the number of drain fingers by one. This
arrangement minimizes parasitic drain junction capacitance at the
expense of source capacitance. Drain capacitance usually has more
effect upon circuit performance than source capacitance, so a
reduction in drain capacitance at the expense of source capacitance
usually improves circuit performance.
Transistors sharing common source or drain connections are frequently
merged to save space or to minimize parasitic junction capacitance.
The merger is a relatively simple matter so long as both transistors
contain sections of the same width. Differing widths require the use
of a notched moat. The spacing between poly and moat forces a
slight increase in the area of the shared source/drain finger, but one
shared finger still consumes less area than two separate fingers.

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Shared Diffusion:

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Shared Diffusion: CMOS layout makes extensive use of merged
devices to save space and to minimize capacitance as in nand or nor
type devices.
The signal node is usually
the shared diffusion.
Density flows sometimes
prohibits the ability to follow
all of these guidelines.

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General Analog Layout Guidelines:
Floor planning: Separate analog from digital circuits.
Keeping switching circuits away from static analog circuits…
(ex. Reference voltage of a diffamp should not be placed
next to a toggling flip flop)
Transistor construction:
1. Place poly connection at center of transistor between the p and
the n gates.
2. Double contacts to poly gates – connect gates in metal rather
than poly.
3. Double vias when you place any vias
4. When a legged device is used, always make even number of legs
5. When a legged device is used, always place the source on the
outer edges of the diffusion.
6. Poly direction on matched devices is always the same.
7. Source and drain on matched devices is in the same orientation.

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General Analog Layout Guidelines:
Transistor, capacitor and resistor matching all use the same
matching concepts.
Inductors use the same structure as shielding in 3D or coax type of
layout.

Analog Layout basic Analog Layout basic Analog Layout basic

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