Analysis of different bit carry look ahead adder using verilog code 2

International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME
214
ANALYSIS OF DIFFERENT BIT CARRY LOOK AHEAD ADDER USING
VERILOG CODE
R.Kathiresan1
, M.Thangavel (Ph.D.)2
, K.Rathinakumar M.Tech 3
, S.Maragadharaj M.E4
1
(M.E)VLSI DESIGN
2
Professor /ECE,
3
Assistant Professor/ECE
4
Assistant Professor/ECE
1, 2, 3, 4
Knowledge Institute of Technology.Salem-637 504, Tamilnadu.
ABSTRACT
Adders are one of the widely used digital components in digital integrated circuit design. In
this paper, various adder structures can be used to execute addition such as serial and parallel
structures and most of researches have done research on the design of high-speed, low-area, or low-
power adders. Adders like ripple carry adder, carry select adder, carry look ahead adder, carry skip
adder, carry save adder [2] exist numerous adder implementations each with good attributes and
some drawbacks. This paper focuses on the implementation and simulation of 4-bit, 8-bit and 16-bit
carry look-ahead adder based on Verilog code [3] and compared for their performance in Xilinx [1].
We have recorded the performance improvements in propagating the carry and generating the sum
when compared with the traditional carry look ahead adder designed in the same technology [4] [5].
Keywords - Addition, Carry-Look ahead Adder (CLA), High Performance, Verilog Simulation,
Xilinx, FPGA.
I. INTRODUCTION
Adders are widely used in generic computer for adding data in the processor, it is also
commonly used in various electronic applications e.g. digital signal processing to perform various
algorithms like FIR, IIR. In past, the major challenge for VLSI designer is to reduce area of chip by
using efficient optimization techniques and then the next phase is to increase the speed of the
operation to achieve fast calculations. Arithmetic logic unit is the main component of central
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processing unit, where the addition, multiplication, comparison and other logical operations are
performed. There are lots of research going on to the reduce power consumption in VLSI circuits [8].
There are three performance parameter on which a VLSI designer has to optimize their
design, which are Area, Speed, and Power. Moreover, there are various types of adders such as
Ripple Carry Adder (RCA), Carry-Lookahead Adder (CLA), Carry Save Adder (CSA), Carry Select
Adder, Carry-Bypass Adder or Carry Skip Adder (CSK) discussed [2].
A. Ripple Carry Adder (RCA)
The Ripple carry adder is constructed by using cascading full adder(FA) blocks in series.The
basic computation elements is a full adder(FA).It accepts three binary inputs A,B and Cin called
addend, augend and carry in respectively the two outputs are the sum and the carry-out(Cout).A
RCA is built by connecting the full adder, So that the carry out from each full adder is the carry –out
from each full-adder is the carry-in to the next stages, the sum and carry bits are generated
sequentially starting from the LSB,the Speed of the RCA is determined by the carry propagating
time. The main advantages of this RCA are low power consumption and compact layout design
smaller chip area [2].
B. Carry Lookahead Adder (CLA)
Carry lookahead-adder is designed to eliminate the ripple carry delay and to overcome the
latency introduced by the rippling effect of the carry bits [1]. This method based on the carry
generating and the carry propagating functions of the full adder. This adder is based on the principle
of looking at the lower bits of the augends and addend if a higher order is generated. This adder
reduces the carry delay by reducing the number of gates through which a carry signal must propagate
[2].
C. Carry Save Adder (CSA)
The carry-save adder reduces the addition of 3 numbers to the addition of 2 numbers. The
carry-save unit consists of ‘n’ full adders, each of which computes a single sum and carries bit based
on the corresponding bits of the three inputs numbers. The entire sum can then be computed by
shifting the carry sequence left by one place and appending a 0 to the front of the partial sum
sequence and adding this sequence with RCA produces the resulting n+ 1 bit values applied in the
partial product line of array multipliers will speed up the carry propagation in the array [2].
D. Carry Select Adder (CSLA)
To solve the carry propagation delay, CSLA is developed which drastically reduces the area
and delay to a great extent. The CSLA is used in many computational systems design to moderate the
problem of carry propagation delay by independently generating multiple carries and then select a
carry to generate the sum. It uses independent ripple carry adders (for Cin=0 and Cin=1) to generate
the resultant sum. The final sum and carry are selected by the multiplexers (mux). A carry-select
adder speeds faster than RCA by performing additions in parallel and reducing the maximum carry
path. Because of the simulation technique the required area and power consumption of this adder is
particularly doubles with respect to RCA [2].

216
E. Carry Skip Adder (CSkA)
A carry-Skip consists of a simple ripple carry-adder with a special up carry chain called a
skip chain. Carry skip adder is a fast adder compared to ripple carry adder.A carry-skip adder is
designed to speed up a wide adder by aiding the propagation of a carry bit around a portion of the
entire adder. However the industrial demands nowdays, which most desktop computers use word
lengths of 32-bits like multimedia processors, makes the carry skip structure more interesting. These
adders have different performance in terms of delay, area and power for same length of binary
numbers. [2]
The paper is organized as follows: section II provides the overview of CLA adder, different
section of CLA adder and its functioning. Section III presents the simulation results along with
device utilization summary following with conclusion
II. OVERVIEW OF CARRY LOOK-AHEAD ADDER
A fast method of adding numbers is called carry-look ahead. This method does not require
the carry signal to propagate stage by stage, causing a bottleneck. Adder based on the carry look-
ahead principle are the dominant trend at the moment, since this structure allows the propagation
delay of the carry-out to be reduced by calculating the carries in each stage in parallel. To compute a
sum, An RCA requires in the worst case , n stage-propagation delays. For high speed processors, this
scheme is undesirable. One way to improve adder performance is to use parallel processing in
computing the carries. That is why Carry look ahead adders are introduced [4] [5]. The carry-look
ahead adder calculates one or more carry bits before the sum calculates, Due to this reduces the
delay time to calculate the result of the larger number of value bits.
Let Ai and Bi be the I bits of the input data and Ci-1 the carry-in for stage i. the usual method
computing the carry-out Ci is
Ci=Gi+PiCi-1 For i=0,1,2,3 …, (1)
Where The generate 'Gi ' in a full adder is given by
Gi=AiBi For i=0,1,2,3 …, (2)
And The propagate 'Pi' in a full adder is given by
Pi=Ai Xor Bi For i=0,1,2,3…, (3)
Expanding equ(1) The carry is generated by
Ci=Gi+piGi-1+PiPi-1Gi-2+……+PiPi-1….p1C0. For i=0,1,2,3.., (4)
The sum is generated by
Si=Ci-1 Xor Ai Xor Bi = Ci-1 Xor Pi for i=0, 1, 2, 3.., (5)

217
Figure 1: Block diagram of 4 Bit Carry Look ahead Adder
III. SIMULATION RESULT
This section presents the simulated results of different bits of carry look ahead adder. The
different bits carry look ahead adder simulation was carried out using the Xilinx software. In every
design circuit compulsory to check the design circuits works with required specification. The design
is simulated at different bit levels by using Xilinx 12.1 Simulation results show that different bits are
simulated so power consumption and propagation delay is varied.
TABLE 1
Comparison of different parameters
ADDERS Number of
slices
Number of 4 i/p
LUTS
Logic level Delay
4 bit CLA 6 12 4 7.863
8 bit CLA 11 21 9 12.895
16 bit CLA 18 32 16 19.848

218
Fig 2: No of slices and No of 4 i/p LUTS Fig 3: Logic level and Delay
Fig 4: Block Schematic of 8-Bit CLA
0
5
10
15
20
25
4 Bit CLA 8 Bit CLA 16 Bit CLA
Logic Level
Delay
0
2
4
6
8
10
12
14
16
18
20
4 bit
CLA
8 bit
CLA
16
bit
CLA
Number of
slices
Number of 4
i/p LUTS

219
Fig 7: Simulation Result of 4-bit CLA
IV. CONCLUSION
We studied about different bits of adders theoretically as well as practically and by
implementation and among compared them by different measures like Area, Delay and then Area-
Delay Product. Comparing the performance metrics of adders for different word lengths using
Verilog [3] and Xilinx as synthesis tool, The Carry Look Ahead Adder had the least Area-Delay
product [4]. It is suitable for situations where both low power and fastness application places.
Different bits of Carry-look ahead adder design is simulated tested and implemented onto the Spartan
3E FPGA kit. To use the CLA in constant delay for the wider-bit adders it is not possible, since there
will be a substantial loading capacitance, and larger delay and larger power consumption.

220
REFERENCES
1). Rajender Kumar, Sandeep Dahiya, “Performance Analysis of Different Bit Carry Look
Ahead Adder Using VHDL Environment”, International Journal of Engineering Science and
Innovative Technology (IJESIT) Volume 2, Issue 4, July 2013
2). S. Knowles, “A Family of Adders,” Proc. 15th
IEEE Symposium onComputer Arithmetic, pp
277-281, 2001.
3). Nazieh M. Botros, “HDL programming (VHDL and Verilog)”, Dreamtech Press (Available
through John Wiley- India and Thomson Learning) 2006 Edition.
4). Jin-Fu Li, Jiunn-Der Yu, and Yu-Jen Huang, “A Design Methodology for Hybrid Carry-
Lookahead/Carry-Select Adders with Reconfigurability”, IEEE International Symposium on
Circuits and Systems (ISCAS 2005), 23-26, May 2005.
5). G.A.Ruiz, M.granda,”An Area –Efficient Staic Cmos Carry-Select Adder Based On A
Compact Carry-Look Ahead Unit”. Microeletronic Journal, Vol No 35, 2004.
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vol. 46, no. 2, pp. 248-253, Feb. 1997.
7). R. Zimmermann, and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor
logic, “IEEE J.Solid State Circuits, vol. 32, no. 7, pp. 1079-1090, Jul. 1997.
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Addison Wesley, 1993.
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pp. 92 - 107, ISSN Print: 0976 – 6367, ISSN Online: 0976 – 6375.
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